D. Andersson, S. Kristiansson, L. Svensson, P. Larsson-Edefors, K. Jeppson
We have investigated the interaction between power delivery and substrate coupling in terms of noise. From our results, we identify that an increased density of substrate contacts does not to any significance decrease noise on the power supply lines. However, the current injected into the substrate is highly dependent on higher-level grid/package inductance and substrate contact density. We have derived statistically that substrate noise variations could be related to these two design parameters to 69.75%. Based on linear fitting, a model that describes the injected current as function of substrate contact density and power delivery inductance is developed.
{"title":"Noise Interaction Between Power Distribution Grids and Substrate","authors":"D. Andersson, S. Kristiansson, L. Svensson, P. Larsson-Edefors, K. Jeppson","doi":"10.1109/ISQED.2008.147","DOIUrl":"https://doi.org/10.1109/ISQED.2008.147","url":null,"abstract":"We have investigated the interaction between power delivery and substrate coupling in terms of noise. From our results, we identify that an increased density of substrate contacts does not to any significance decrease noise on the power supply lines. However, the current injected into the substrate is highly dependent on higher-level grid/package inductance and substrate contact density. We have derived statistically that substrate noise variations could be related to these two design parameters to 69.75%. Based on linear fitting, a model that describes the injected current as function of substrate contact density and power delivery inductance is developed.","PeriodicalId":243121,"journal":{"name":"9th International Symposium on Quality Electronic Design (isqed 2008)","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113957191","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
As critical dimensions (CDs) of integrated circuit (IC) continue to scale down, subwavelength lithography has become the mainstream of chip manufacture. Various resolution enhancement techniques (RETs) such as the popular model-based optical proximity correction (OPC) have become an indispensable part of mask data preparation. However, traditional full-chip OPC will lead to mask data explosion and prohibitive runtime. In this paper, we propose a novel kind of cellwise OPC which can reuse the results of standard-cell-based OPC. To achieve this goal, we construct a reduced standard cell library composed of merely three kinds of basic cells, which have the same size and can realize all logics of traditional standard cell library. This library is manufacture-friendly, and reuse of its OPC results can improve the efficiency of chip manufacture greatly and significantly reduce the need for large storage. The electrical simulation results of the library on several benchmark circuits also show that its overhead of area, delay, as well as power is quite minor or even competitive compared with traditional standard cell library.
{"title":"Cellwise OPC Based on Reduced Standard Cell Library","authors":"Hailong Jiao, Lan Chen","doi":"10.1109/ISQED.2008.54","DOIUrl":"https://doi.org/10.1109/ISQED.2008.54","url":null,"abstract":"As critical dimensions (CDs) of integrated circuit (IC) continue to scale down, subwavelength lithography has become the mainstream of chip manufacture. Various resolution enhancement techniques (RETs) such as the popular model-based optical proximity correction (OPC) have become an indispensable part of mask data preparation. However, traditional full-chip OPC will lead to mask data explosion and prohibitive runtime. In this paper, we propose a novel kind of cellwise OPC which can reuse the results of standard-cell-based OPC. To achieve this goal, we construct a reduced standard cell library composed of merely three kinds of basic cells, which have the same size and can realize all logics of traditional standard cell library. This library is manufacture-friendly, and reuse of its OPC results can improve the efficiency of chip manufacture greatly and significantly reduce the need for large storage. The electrical simulation results of the library on several benchmark circuits also show that its overhead of area, delay, as well as power is quite minor or even competitive compared with traditional standard cell library.","PeriodicalId":243121,"journal":{"name":"9th International Symposium on Quality Electronic Design (isqed 2008)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121832485","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
R. Kanj, R. Joshi, Keunwoo Kim, Richard Q. Williams, S. Nassif
We study the yield improvements of mixed/split gate designs in 45 nm FinFET technology. The original contributions of this paper are: fast statistical analysis for FinFET designs including 6T and 8T column- decoupled designs, and the proposed low-voltage 6T- column-decoupled SRAM cell using stacked_and FinFET devices. Sensitivities of the cell yield to device design uncertainties and process variations are evaluated. Statistical analysis indicates that column-decoupled cells can help lower the stability requirement on the cell beta ratio and hence relax the design limitations with FinFET technology such as quantization penalties. Furthermore, physical cell image diagrams show that the 6T-decoupled cell suffers very small area penalties compared to the traditional double gate designs. Fast statistical analysis techniques are used to estimate yield trend. Numerical device/circuit mix-mode simulations support the predicted trends. Threshold voltage variations due to random dopant fluctuations are estimated using a macroscopic modeling method. The impact of fin-height variations is also evaluated.
{"title":"Statistical Evaluation of Split Gate Opportunities for Improved 8T/6T Column-Decoupled SRAM Cell Yield","authors":"R. Kanj, R. Joshi, Keunwoo Kim, Richard Q. Williams, S. Nassif","doi":"10.1109/ISQED.2008.24","DOIUrl":"https://doi.org/10.1109/ISQED.2008.24","url":null,"abstract":"We study the yield improvements of mixed/split gate designs in 45 nm FinFET technology. The original contributions of this paper are: fast statistical analysis for FinFET designs including 6T and 8T column- decoupled designs, and the proposed low-voltage 6T- column-decoupled SRAM cell using stacked_and FinFET devices. Sensitivities of the cell yield to device design uncertainties and process variations are evaluated. Statistical analysis indicates that column-decoupled cells can help lower the stability requirement on the cell beta ratio and hence relax the design limitations with FinFET technology such as quantization penalties. Furthermore, physical cell image diagrams show that the 6T-decoupled cell suffers very small area penalties compared to the traditional double gate designs. Fast statistical analysis techniques are used to estimate yield trend. Numerical device/circuit mix-mode simulations support the predicted trends. Threshold voltage variations due to random dopant fluctuations are estimated using a macroscopic modeling method. The impact of fin-height variations is also evaluated.","PeriodicalId":243121,"journal":{"name":"9th International Symposium on Quality Electronic Design (isqed 2008)","volume":"2010 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123816496","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Srinivasa R. Stg, J. Srivatsava, Narahari Tondamuthuru R
Integrated circuit manufacturability in DSM is directly dependent on how well the manufacturing variations are accounted for during the design of circuits. This paper reviews the effect of various process variations in DSM especially systematic and random variations in three process generations 90 nm, 65 nm & 45 nm by doing SPICE simulation and analysis to look at the derating factors depending on the sensitivity to variations. Few individual standard cells are studied as apart of this exercise to see the effect of variation on their delays. Random variations are becoming a significant portion of the overall variations at 45 nm and below. The results suggests the need for selective, location based and variation aware analysis (SLVA) for the designs going forward.
{"title":"Process Variability Analysis in DSM Through Statistical Simulations and its Implications to Design Methodologies","authors":"Srinivasa R. Stg, J. Srivatsava, Narahari Tondamuthuru R","doi":"10.1109/ISQED.2008.87","DOIUrl":"https://doi.org/10.1109/ISQED.2008.87","url":null,"abstract":"Integrated circuit manufacturability in DSM is directly dependent on how well the manufacturing variations are accounted for during the design of circuits. This paper reviews the effect of various process variations in DSM especially systematic and random variations in three process generations 90 nm, 65 nm & 45 nm by doing SPICE simulation and analysis to look at the derating factors depending on the sensitivity to variations. Few individual standard cells are studied as apart of this exercise to see the effect of variation on their delays. Random variations are becoming a significant portion of the overall variations at 45 nm and below. The results suggests the need for selective, location based and variation aware analysis (SLVA) for the designs going forward.","PeriodicalId":243121,"journal":{"name":"9th International Symposium on Quality Electronic Design (isqed 2008)","volume":"137 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121500936","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The value of guardband reduction is a critical open issue for the semiconductor industry. For example, due to competitive pressure, foundries have started to incent the design of manufacturing-friendly ICs through reduced model guardbands when designers adopt layout restrictions. The industry also continuously weighs the economic viability of relaxing process variation limits in the technology roadmap [2]. Our work gives the first-ever quantification of the impact of modeling guardband reduction on outcomes from the synthesis, place and route (SP&R) implementation flow. We assess the impact of model guard- band reduction on various metrics of design cycle time and design quality, using open-source cores and production (specifically, ARM/TSMC) 90 nm and 65 nm technologies and libraries. Our experimental data clearly shows the potential design quality and turnaround time benefits of model guardband reduction. For example, we typically (i.e., on average) observe 13% standard-cell area reduction and 12% routed wirelength reduction as the consequence of a 40% reduction in library model guardband; 40% is the amount of guardband reduction reported by IBM for a variation-aware timing methodology [8]. We also assess the impact of guardband reduction on design yield. Our results suggest that there is justification for the design, EDA and process communities to enable guardband reduction as an economic incentive for manufacturing-friendly design practices.
{"title":"Quantified Impacts of Guardband Reduction on Design Process Outcomes","authors":"Kwangok Jeong, A. Kahng, K. Samadi","doi":"10.1109/ISQED.2008.155","DOIUrl":"https://doi.org/10.1109/ISQED.2008.155","url":null,"abstract":"The value of guardband reduction is a critical open issue for the semiconductor industry. For example, due to competitive pressure, foundries have started to incent the design of manufacturing-friendly ICs through reduced model guardbands when designers adopt layout restrictions. The industry also continuously weighs the economic viability of relaxing process variation limits in the technology roadmap [2]. Our work gives the first-ever quantification of the impact of modeling guardband reduction on outcomes from the synthesis, place and route (SP&R) implementation flow. We assess the impact of model guard- band reduction on various metrics of design cycle time and design quality, using open-source cores and production (specifically, ARM/TSMC) 90 nm and 65 nm technologies and libraries. Our experimental data clearly shows the potential design quality and turnaround time benefits of model guardband reduction. For example, we typically (i.e., on average) observe 13% standard-cell area reduction and 12% routed wirelength reduction as the consequence of a 40% reduction in library model guardband; 40% is the amount of guardband reduction reported by IBM for a variation-aware timing methodology [8]. We also assess the impact of guardband reduction on design yield. Our results suggest that there is justification for the design, EDA and process communities to enable guardband reduction as an economic incentive for manufacturing-friendly design practices.","PeriodicalId":243121,"journal":{"name":"9th International Symposium on Quality Electronic Design (isqed 2008)","volume":"206 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131397026","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Yue Fu, Jin He, Feng Liu, Jie Feng, Chenyue Ma, Lining Zhang
This paper investigates the transport properties of the silicon-germanium nanowire MOSFETs with core-shell structure by using a finite element numerical method for electronic structure, energy level, and channel current computation. Coupled Poisson's equation to Schrodinger's equation for electrostatics calculation and electron structure to current transport equation for channel current computation, the electronic structure, quantized energy levels, relevant wave functions and charge distribution are solved selfconsistently for the core-shell structure MOSFETs. Furthermore, based on these findings, the transistor performances, including the capacitance characteristics and drain current, are also predicted.
{"title":"Study on the Si-Ge Nanowire MOSFETs with the Core-Shell Structure","authors":"Yue Fu, Jin He, Feng Liu, Jie Feng, Chenyue Ma, Lining Zhang","doi":"10.1109/ISQED.2008.77","DOIUrl":"https://doi.org/10.1109/ISQED.2008.77","url":null,"abstract":"This paper investigates the transport properties of the silicon-germanium nanowire MOSFETs with core-shell structure by using a finite element numerical method for electronic structure, energy level, and channel current computation. Coupled Poisson's equation to Schrodinger's equation for electrostatics calculation and electron structure to current transport equation for channel current computation, the electronic structure, quantized energy levels, relevant wave functions and charge distribution are solved selfconsistently for the core-shell structure MOSFETs. Furthermore, based on these findings, the transistor performances, including the capacitance characteristics and drain current, are also predicted.","PeriodicalId":243121,"journal":{"name":"9th International Symposium on Quality Electronic Design (isqed 2008)","volume":"177 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115133554","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper addresses the problem of optimizing metallization patterns of back-end connections for the DMOS based driver since the back-end connections trend to dominate the overall on-resistance Ron. We propose a heuristic algorithm to seek for better shapes for the patterns targeting at minimizing Ron and at balancing the current distribution. In order to speed up the analysis, the equivalent resistance network of the driver is modified by inserting ideal switches to keep the conductance matrix constant. Simulation on two drivers from industrial TEG data demonstrates that our algorithm can reduce Ron effectively by shaping metals appropriately within a given routing area.
{"title":"Fast Shape Optimization of Metallization Patterns for DMOS Based Driver","authors":"Bo Yang, S. Nakatake, H. Murata","doi":"10.1109/ISQED.2008.98","DOIUrl":"https://doi.org/10.1109/ISQED.2008.98","url":null,"abstract":"This paper addresses the problem of optimizing metallization patterns of back-end connections for the DMOS based driver since the back-end connections trend to dominate the overall on-resistance Ron. We propose a heuristic algorithm to seek for better shapes for the patterns targeting at minimizing Ron and at balancing the current distribution. In order to speed up the analysis, the equivalent resistance network of the driver is modified by inserting ideal switches to keep the conductance matrix constant. Simulation on two drivers from industrial TEG data demonstrates that our algorithm can reduce Ron effectively by shaping metals appropriately within a given routing area.","PeriodicalId":243121,"journal":{"name":"9th International Symposium on Quality Electronic Design (isqed 2008)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134178319","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper presents a heuristic cell-based approach to reduce leakage power in multi-million gate design ASICs in 90 nm/65 nm processes by swapping low-Vt cells with high-Vt cells on less critical timing paths in the design. It uses heuristics to avoid frequent time-consuming full-design timing updates and has significant run-time improvement over currently available approaches. Unlike traditional approaches, proposed generic approach fits well in the design flow and works on any kind of design having mixture of all type of Vt cells available in the library. The proposed algorithm gives active leakage reduction of up to 64% with run time of 3-15 hours for multi-million gate designs.
{"title":"A Novel Cell-Based Heuristic Method for Leakage Reduction in Multi-Million Gate VLSI Designs","authors":"S. Gupta, Jayajit Singh, Abhijit Roy","doi":"10.1109/ISQED.2008.145","DOIUrl":"https://doi.org/10.1109/ISQED.2008.145","url":null,"abstract":"This paper presents a heuristic cell-based approach to reduce leakage power in multi-million gate design ASICs in 90 nm/65 nm processes by swapping low-Vt cells with high-Vt cells on less critical timing paths in the design. It uses heuristics to avoid frequent time-consuming full-design timing updates and has significant run-time improvement over currently available approaches. Unlike traditional approaches, proposed generic approach fits well in the design flow and works on any kind of design having mixture of all type of Vt cells available in the library. The proposed algorithm gives active leakage reduction of up to 64% with run time of 3-15 hours for multi-million gate designs.","PeriodicalId":243121,"journal":{"name":"9th International Symposium on Quality Electronic Design (isqed 2008)","volume":"254 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134339591","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
We present a new dynamic-like static circuit family called feedback-switch logic (FSL) that is suitable for high-speed low-power applications. FSL is a derivative of cascode voltage switch logic (CVSL) family. However, it does not suffer from the contention problems of clockless CVSL, and it consumes much less power than clocked CVSL (dual-rail domino). FSL gates offer fast switching, reduced capacitance, and input-switching dependent activity factor without the need of clock connection. An 18-bit majority voting circuit is simulated in a 90-nm technology, in order to compare static, clockless CVSL, dual-rail domino and FSL. Simulation results show that FSL reduces delay by 21% compared to static logic, and offers at least 46% power reduction compared to dynamic dual-rail domino logic with two-phase skew-tolerant clocking.
{"title":"Feedback-Switch Logic (FSL): A High-Speed Low-Power Differential Dynamic-Like Static CMOS Circuit Family","authors":"Charbel J. Akl, M. Bayoumi","doi":"10.1109/ISQED.2008.36","DOIUrl":"https://doi.org/10.1109/ISQED.2008.36","url":null,"abstract":"We present a new dynamic-like static circuit family called feedback-switch logic (FSL) that is suitable for high-speed low-power applications. FSL is a derivative of cascode voltage switch logic (CVSL) family. However, it does not suffer from the contention problems of clockless CVSL, and it consumes much less power than clocked CVSL (dual-rail domino). FSL gates offer fast switching, reduced capacitance, and input-switching dependent activity factor without the need of clock connection. An 18-bit majority voting circuit is simulated in a 90-nm technology, in order to compare static, clockless CVSL, dual-rail domino and FSL. Simulation results show that FSL reduces delay by 21% compared to static logic, and offers at least 46% power reduction compared to dynamic dual-rail domino logic with two-phase skew-tolerant clocking.","PeriodicalId":243121,"journal":{"name":"9th International Symposium on Quality Electronic Design (isqed 2008)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134426070","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Young-Gu Kim, Soo-Hwan Kim, H. Lim, Sanghoon Lee, Keun-Ho Lee, Young-Kwan Park, Moon-Hyun Yoo
Increase of the process variability with aggressive technology scaling causes many productivity issues in VLSI manufacturing. Analysis about the relationship between process variability and failure has been performed to specify guidelines in both technology and design aspects for yield optimization. By applying the proposed methodology, the core scheme and the operating voltage of the 200 MHz SRAM were determined to secure the immunity to operational failures. In DFM point of view, the statistical circuit analysis for failure characteristics is indispensable to guarantee an optimal yield in manufacturing.
{"title":"The Statistical Failure Analysis for the Design of Robust SRAM in Nano-Scale Era","authors":"Young-Gu Kim, Soo-Hwan Kim, H. Lim, Sanghoon Lee, Keun-Ho Lee, Young-Kwan Park, Moon-Hyun Yoo","doi":"10.1109/ISQED.2008.108","DOIUrl":"https://doi.org/10.1109/ISQED.2008.108","url":null,"abstract":"Increase of the process variability with aggressive technology scaling causes many productivity issues in VLSI manufacturing. Analysis about the relationship between process variability and failure has been performed to specify guidelines in both technology and design aspects for yield optimization. By applying the proposed methodology, the core scheme and the operating voltage of the 200 MHz SRAM were determined to secure the immunity to operational failures. In DFM point of view, the statistical circuit analysis for failure characteristics is indispensable to guarantee an optimal yield in manufacturing.","PeriodicalId":243121,"journal":{"name":"9th International Symposium on Quality Electronic Design (isqed 2008)","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115711485","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：