B. Mohammad, M. Saint-Laurent, P. Bassett, J. Abraham
A novel circuit approach to increase SRAM static noise margin (SNM) and enable lower operating voltage is described. Increasing process variability [1] [2] for new technologies coupled with increased reliability effects like negative bias temperature instability (NBTI) [3] all contribute to raising the minimum voltage required for stable SRAM. Our strategy is to improve the noise margin of the 6T SRAM cell by reducing the effect of parametric variation of the cell [4], especially in the low voltage operation mode. This is done using a novel circuit that selectively reduces the voltage swing on the world line and reduces the memory supply voltage during write operation. The proposed design increases the SRAM static noise margin (SNM) and write margin using a single voltage supply and with minimum impact to chip area, complexity, and timing. The technique supports both on-chip corner identification to adapt the SRAM behavior to silicon, and software controllability to tradeoff yield, power, and performance.
{"title":"Cache Design for Low Power and High Yield","authors":"B. Mohammad, M. Saint-Laurent, P. Bassett, J. Abraham","doi":"10.1109/ISQED.2008.49","DOIUrl":"https://doi.org/10.1109/ISQED.2008.49","url":null,"abstract":"A novel circuit approach to increase SRAM static noise margin (SNM) and enable lower operating voltage is described. Increasing process variability [1] [2] for new technologies coupled with increased reliability effects like negative bias temperature instability (NBTI) [3] all contribute to raising the minimum voltage required for stable SRAM. Our strategy is to improve the noise margin of the 6T SRAM cell by reducing the effect of parametric variation of the cell [4], especially in the low voltage operation mode. This is done using a novel circuit that selectively reduces the voltage swing on the world line and reduces the memory supply voltage during write operation. The proposed design increases the SRAM static noise margin (SNM) and write margin using a single voltage supply and with minimum impact to chip area, complexity, and timing. The technique supports both on-chip corner identification to adapt the SRAM behavior to silicon, and software controllability to tradeoff yield, power, and performance.","PeriodicalId":243121,"journal":{"name":"9th International Symposium on Quality Electronic Design (isqed 2008)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115537735","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Michael N. Skoufis, Kedar Karmarkar, T. Haniotakis, S. Tragoudas
Coupling and increasing wire resistance on interconnect fabrics undermine the speed of the transient electrical signals. A brute-force approach for a crosstalk-reduced design relies on increasing the distance of interconnects from each other and using additional repeated logic. A pipelined bus-architecture exploiting the existing electrical noise is proposed. Process variations are taken into consideration in the analysis. The proposed technique is validated for the 65 nm and 90 nm CMOS processes for interconnects of various lengths.
{"title":"A High-Performance Bus Architecture for Strongly Coupled Interconnects","authors":"Michael N. Skoufis, Kedar Karmarkar, T. Haniotakis, S. Tragoudas","doi":"10.1109/ISQED.2008.21","DOIUrl":"https://doi.org/10.1109/ISQED.2008.21","url":null,"abstract":"Coupling and increasing wire resistance on interconnect fabrics undermine the speed of the transient electrical signals. A brute-force approach for a crosstalk-reduced design relies on increasing the distance of interconnects from each other and using additional repeated logic. A pipelined bus-architecture exploiting the existing electrical noise is proposed. Process variations are taken into consideration in the analysis. The proposed technique is validated for the 65 nm and 90 nm CMOS processes for interconnects of various lengths.","PeriodicalId":243121,"journal":{"name":"9th International Symposium on Quality Electronic Design (isqed 2008)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122631289","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Summary form only given. This part of the tutorial will discuss in detail the manufacturing challenges in nanoscale VLSI and consequent design for manufacturability (DFM) approaches by taking a holistic approach in analyzing and addressing different process variability effects. We review the dominant process variations in semiconductor manufacturing process that affect the design yield, show their impact on layout quality, and present currently practiced DFM techniques to mitigate the effect of these variations. We also discuss various manufacturing-aware physical and circuit design methodologies and techniques for parametric yield improvement. This includes correct-by-construction methodologies such as Restricted Design Rules (RDRs) as well as manufacturing aware design approaches. In addition, we will briefly mention some of the many accepted and possible mitigation techniques in design post processing (after tape-out) and will introduce the concept of manufacturing for design (MFD) through design-intent processing.
{"title":"Tutorial 6: Enhancing Yield through Design for Manufacturability (DFM)","authors":"P. Elakkumanan","doi":"10.1109/ISQED.2008.177","DOIUrl":"https://doi.org/10.1109/ISQED.2008.177","url":null,"abstract":"Summary form only given. This part of the tutorial will discuss in detail the manufacturing challenges in nanoscale VLSI and consequent design for manufacturability (DFM) approaches by taking a holistic approach in analyzing and addressing different process variability effects. We review the dominant process variations in semiconductor manufacturing process that affect the design yield, show their impact on layout quality, and present currently practiced DFM techniques to mitigate the effect of these variations. We also discuss various manufacturing-aware physical and circuit design methodologies and techniques for parametric yield improvement. This includes correct-by-construction methodologies such as Restricted Design Rules (RDRs) as well as manufacturing aware design approaches. In addition, we will briefly mention some of the many accepted and possible mitigation techniques in design post processing (after tape-out) and will introduce the concept of manufacturing for design (MFD) through design-intent processing.","PeriodicalId":243121,"journal":{"name":"9th International Symposium on Quality Electronic Design (isqed 2008)","volume":"1120 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123345670","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Qiang Fu, W. Luk, Jun Tao, Changhao Yan, Xuan Zeng
A spectral domain method for intra-die spatial correlation function extraction is presented. Based on theoretical analysis of random field, the spectral density, as the spectral domain counterpart of correlation function, is employed to estimate the parameters of the correlation function effectively in the spectral domain. Compared with the existing extraction algorithm in the original spatial domain, the proposed method can obtain the same quality of results in the spectral domain. In actual measurement process, the unavoidable measurement error with arbitrary frequency components would greatly confound the extraction results. A filtering technique is further proposed to diminish the high frequency components of the measurement error and recover the data from noise contamination for parameter estimation. Experimental results have shown that the proposed method is practical and stable.
{"title":"Characterizing Intra-Die Spatial Correlation Using Spectral Density Method","authors":"Qiang Fu, W. Luk, Jun Tao, Changhao Yan, Xuan Zeng","doi":"10.1109/ISQED.2008.134","DOIUrl":"https://doi.org/10.1109/ISQED.2008.134","url":null,"abstract":"A spectral domain method for intra-die spatial correlation function extraction is presented. Based on theoretical analysis of random field, the spectral density, as the spectral domain counterpart of correlation function, is employed to estimate the parameters of the correlation function effectively in the spectral domain. Compared with the existing extraction algorithm in the original spatial domain, the proposed method can obtain the same quality of results in the spectral domain. In actual measurement process, the unavoidable measurement error with arbitrary frequency components would greatly confound the extraction results. A filtering technique is further proposed to diminish the high frequency components of the measurement error and recover the data from noise contamination for parameter estimation. Experimental results have shown that the proposed method is practical and stable.","PeriodicalId":243121,"journal":{"name":"9th International Symposium on Quality Electronic Design (isqed 2008)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123378966","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Increasing power density (due to faster clock and high device integration density) coupled with limited cooling capacity of the package causes die overheating and leads to reliability concerns. In this paper, we present a methodology to mitigate temperature-induced reliability problems by transferring the heat dissipated in a region of high activity (such as the ALU in a processor that creates localized "hotspot") to regions of lower activity (such as on-chip cache). We propose to use carbon nanotubes (CNTs) as "thermal interconnect" for on-die heat transfer since CNTs have significantly higher thermal conductivity than typical heat-spreader materials. We note that the proposed heat transfer framework is particularly suitable to thermal management in silicon-on-insulator (SOI) devices, which suffer from fine-grained thermal gradient. Simulation results indicate that the use of CNTs for heat conduction from hotspot to a region of lower activity (which we denote as a 'coolspot'), achieves 13% (16degC) decrease in temperature at the hotspot and only 3% (1.5degC) increase in temperature at the coolspot of an alpha microprocessor model.
{"title":"Towards Uniform Temperature Distribution in SOI Circuits Using Carbon Nanotube Based Thermal Interconnect","authors":"Yu Zhou, Somnath Paul, S. Bhunia","doi":"10.1109/ISQED.2008.163","DOIUrl":"https://doi.org/10.1109/ISQED.2008.163","url":null,"abstract":"Increasing power density (due to faster clock and high device integration density) coupled with limited cooling capacity of the package causes die overheating and leads to reliability concerns. In this paper, we present a methodology to mitigate temperature-induced reliability problems by transferring the heat dissipated in a region of high activity (such as the ALU in a processor that creates localized \"hotspot\") to regions of lower activity (such as on-chip cache). We propose to use carbon nanotubes (CNTs) as \"thermal interconnect\" for on-die heat transfer since CNTs have significantly higher thermal conductivity than typical heat-spreader materials. We note that the proposed heat transfer framework is particularly suitable to thermal management in silicon-on-insulator (SOI) devices, which suffer from fine-grained thermal gradient. Simulation results indicate that the use of CNTs for heat conduction from hotspot to a region of lower activity (which we denote as a 'coolspot'), achieves 13% (16degC) decrease in temperature at the hotspot and only 3% (1.5degC) increase in temperature at the coolspot of an alpha microprocessor model.","PeriodicalId":243121,"journal":{"name":"9th International Symposium on Quality Electronic Design (isqed 2008)","volume":"2 3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123636728","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper dual-K (DKCMOS) technology is proposed as a method for gate leakage power reduction. An integer linear programming (ILP) based algorithm is proposed for its optimization during architectural synthesis. The algorithm uses device-level gate leakage models for precharacterizing register-transfer level (RTL) datapath component library and minimizes the leakage delay product (LDP). The proposed algorithm is tested for several circuits for 45nm CMOS technology node. The experiments show that average gate leakage reduction are 67.7 % and 80.8 % for SiO2- SiON and SiO2-Si3N4, respectively.
{"title":"ILP Based Gate Leakage Optimization Using DKCMOS Library during RTL Synthesis","authors":"S. Mohanty","doi":"10.1109/ISQED.2008.9","DOIUrl":"https://doi.org/10.1109/ISQED.2008.9","url":null,"abstract":"In this paper dual-K (DKCMOS) technology is proposed as a method for gate leakage power reduction. An integer linear programming (ILP) based algorithm is proposed for its optimization during architectural synthesis. The algorithm uses device-level gate leakage models for precharacterizing register-transfer level (RTL) datapath component library and minimizes the leakage delay product (LDP). The proposed algorithm is tested for several circuits for 45nm CMOS technology node. The experiments show that average gate leakage reduction are 67.7 % and 80.8 % for SiO2- SiON and SiO2-Si3N4, respectively.","PeriodicalId":243121,"journal":{"name":"9th International Symposium on Quality Electronic Design (isqed 2008)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129676037","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
T. Niiyama, Piao Zhe, K. Ishida, M. Murakata, M. Takamiya, T. Sakurai
The minimum operating voltage (VDDmin) of 90-nm CMOS ring oscillators (RO's) is investigated in order to clarify the lower limit of supply voltage (VDD) for logic circuits. The measured VDDmin is determined by the intra-die threshold voltage random variations and increased from 91 mV to 224 mV when the number of RO stages increased from 11 to 1001, which hinders the VDD scaling. Lowering VDDmin is difficult, since it would require an impractical inverter-by-inverter adaptive body bias control. Therefore, the fine-grain adaptive VDD control will be more effective for the ultra low voltage logic circuits to reduce the power consumption.
{"title":"Dependence of Minimum Operating Voltage (VDDmin) on Block Size of 90-nm CMOS Ring Oscillators and its Implications in Low Power DFM","authors":"T. Niiyama, Piao Zhe, K. Ishida, M. Murakata, M. Takamiya, T. Sakurai","doi":"10.1109/ISQED.2008.59","DOIUrl":"https://doi.org/10.1109/ISQED.2008.59","url":null,"abstract":"The minimum operating voltage (VDDmin) of 90-nm CMOS ring oscillators (RO's) is investigated in order to clarify the lower limit of supply voltage (VDD) for logic circuits. The measured VDDmin is determined by the intra-die threshold voltage random variations and increased from 91 mV to 224 mV when the number of RO stages increased from 11 to 1001, which hinders the VDD scaling. Lowering VDDmin is difficult, since it would require an impractical inverter-by-inverter adaptive body bias control. Therefore, the fine-grain adaptive VDD control will be more effective for the ultra low voltage logic circuits to reduce the power consumption.","PeriodicalId":243121,"journal":{"name":"9th International Symposium on Quality Electronic Design (isqed 2008)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116989977","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Summary form only given. The product development challenges for high-tech companies are even greater than most industries, thanks in large part to their dependence on an increasingly distributed and complex global value chain and extreme pressure to deliver innovation to market quicker than their fierce competition.That chain of frequently independent companies collaborating on these shrinking project timeline stretches from product conception to chip design, product development, production/assembly, testing, packaging, and delivery. Central to addressing these challenges are solutions and interoperable IT enterprise architectures that can streamline this innovation pipeline. In this presentation the author discusses the opportunities to shrink product time-to-market by more quickly, efficiently, and securely collaborating and integrating with product development value chain partners.
仅提供摘要形式。高科技公司在产品开发方面面临的挑战甚至比大多数行业都要大，这在很大程度上要归功于它们对日益分散和复杂的全球价值链的依赖，以及比激烈的竞争对手更快将创新产品推向市场的巨大压力。要应对这些挑战，关键在于能够简化创新流程的解决方案和可互操作的 IT 企业架构。在本演讲中，作者将讨论通过更快速、高效、安全地与产品开发价值链合作伙伴协作和集成，缩短产品上市时间的机会。
{"title":"Plenary Speech 1P1: Shrinking time-to-market through global value chain integration","authors":"Drew Gude","doi":"10.1109/ISQED.2008.181","DOIUrl":"https://doi.org/10.1109/ISQED.2008.181","url":null,"abstract":"Summary form only given. The product development challenges for high-tech companies are even greater than most industries, thanks in large part to their dependence on an increasingly distributed and complex global value chain and extreme pressure to deliver innovation to market quicker than their fierce competition.That chain of frequently independent companies collaborating on these shrinking project timeline stretches from product conception to chip design, product development, production/assembly, testing, packaging, and delivery. Central to addressing these challenges are solutions and interoperable IT enterprise architectures that can streamline this innovation pipeline. In this presentation the author discusses the opportunities to shrink product time-to-market by more quickly, efficiently, and securely collaborating and integrating with product development value chain partners.","PeriodicalId":243121,"journal":{"name":"9th International Symposium on Quality Electronic Design (isqed 2008)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126519735","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
S. Jairam, S. M. Stalin, Jean-Yves Oberle, H. Udayakumar
A methodology to estimate electromagnetic (EM) emission from SoCs is presented. The solution works on estimating current spectral components at the SoC periphery by performing power integrity analysis based on simultaneously switching outputs (SSO). These components are then converted to electric and magnetic dipoles. The dipoles are then analysed by a customised field solver, which computes, the field radiation patterns. Antenna models have been generated through the lead frames for quad flat and ball grid array packages. The proposed approach enables unification of SoC periphery analysis platform for timing, signal, power integrity alongwith EM emission estimation. Finally the approach has been demonstrated on various SoC periphery analysis scenarios. A memory interface of a 90 nm SOC design has been analysed and results have been compared with silicon measurements.
{"title":"An SSO Based Methodology for EM Emission Estimation from SoCs","authors":"S. Jairam, S. M. Stalin, Jean-Yves Oberle, H. Udayakumar","doi":"10.1109/ISQED.2008.15","DOIUrl":"https://doi.org/10.1109/ISQED.2008.15","url":null,"abstract":"A methodology to estimate electromagnetic (EM) emission from SoCs is presented. The solution works on estimating current spectral components at the SoC periphery by performing power integrity analysis based on simultaneously switching outputs (SSO). These components are then converted to electric and magnetic dipoles. The dipoles are then analysed by a customised field solver, which computes, the field radiation patterns. Antenna models have been generated through the lead frames for quad flat and ball grid array packages. The proposed approach enables unification of SoC periphery analysis platform for timing, signal, power integrity alongwith EM emission estimation. Finally the approach has been demonstrated on various SoC periphery analysis scenarios. A memory interface of a 90 nm SOC design has been analysed and results have been compared with silicon measurements.","PeriodicalId":243121,"journal":{"name":"9th International Symposium on Quality Electronic Design (isqed 2008)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122316661","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A new six transistor (6 T) SRAM cell with PMOS access transistors is proposed in this paper for reducing the leakage power consumption while enhancing the data stability and the integration density of FinFET memory circuits. With the proposed SRAM circuit, the voltage disturbance at the data storage nodes during a read operation is reduced by utilizing PMOS access transistors. The read stability is enhanced by 60% while reducing the leakage power by 21% as compared to a standard tied-gate FinFET SRAM cell with the same size transistors. One gate of each pull-up FinFET of the cross- coupled inverters is permanently disabled in order to achieve write-ability with minimum sized transistors. The proposed independent-gate FinFET SRAM circuit with P-type data access transistors reduces the idle mode leakage power, the read power, the write power, and the cell area by 61%, 20%, 11.4%, and 17.5%, respectively, as compared to a standard tied-gate FinFET SRAM cell sized for similar data stability in a 32 nm FinFET technology.
{"title":"Compact FinFET Memory Circuits with P-Type Data Access Transistors for Low Leakage and Robust Operation","authors":"S. Tawfik, V. Kursun","doi":"10.1109/ISQED.2008.70","DOIUrl":"https://doi.org/10.1109/ISQED.2008.70","url":null,"abstract":"A new six transistor (6 T) SRAM cell with PMOS access transistors is proposed in this paper for reducing the leakage power consumption while enhancing the data stability and the integration density of FinFET memory circuits. With the proposed SRAM circuit, the voltage disturbance at the data storage nodes during a read operation is reduced by utilizing PMOS access transistors. The read stability is enhanced by 60% while reducing the leakage power by 21% as compared to a standard tied-gate FinFET SRAM cell with the same size transistors. One gate of each pull-up FinFET of the cross- coupled inverters is permanently disabled in order to achieve write-ability with minimum sized transistors. The proposed independent-gate FinFET SRAM circuit with P-type data access transistors reduces the idle mode leakage power, the read power, the write power, and the cell area by 61%, 20%, 11.4%, and 17.5%, respectively, as compared to a standard tied-gate FinFET SRAM cell sized for similar data stability in a 32 nm FinFET technology.","PeriodicalId":243121,"journal":{"name":"9th International Symposium on Quality Electronic Design (isqed 2008)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130878354","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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