Pub Date : 1994-06-20DOI: 10.1109/DRC.1994.1009456
Y. Chan, J. Chyi, C. Wu, H. Hwang, M. Yang, R. Lin, J. Shieh
By increasing the In composition in the In,Gal_,As channel, the so-called pseudomorphic channel on GaAs substrates can substantially improve the device performance due to a better carrier confinement and higher drift velocity. However, for further increasing the In content in the InxGal-,As channel is always limited by critical thickness. Therefore, the unstrained or so-called metamorphic layer design was proposed to break the limitation of critical thickness. This approach used the graded approach to gradually increase the In content in the buffer. As long as the interfacial dislocations are confined in this graded buffer, a dislocation-free and stress-free layer with a high In content can be obtained simultaneously on the top of this metamorphic buffer[l]. In this study, we used a step-garded In,Gai_,As buffer to increase the In composition up to x a . 3 0 on GaAs substrates, and fabricated various electronic devices based on this In0.2gQ.7 1As/Ino.3Gag.7As heterostructure.
{"title":"In/sub 0.29/Al/sub 0.71/As/In/sub 0.3/Ga/sub 0.7/As heterostructure devices grown on GaAs substrates with a metamorphic buffer design","authors":"Y. Chan, J. Chyi, C. Wu, H. Hwang, M. Yang, R. Lin, J. Shieh","doi":"10.1109/DRC.1994.1009456","DOIUrl":"https://doi.org/10.1109/DRC.1994.1009456","url":null,"abstract":"By increasing the In composition in the In,Gal_,As channel, the so-called pseudomorphic channel on GaAs substrates can substantially improve the device performance due to a better carrier confinement and higher drift velocity. However, for further increasing the In content in the InxGal-,As channel is always limited by critical thickness. Therefore, the unstrained or so-called metamorphic layer design was proposed to break the limitation of critical thickness. This approach used the graded approach to gradually increase the In content in the buffer. As long as the interfacial dislocations are confined in this graded buffer, a dislocation-free and stress-free layer with a high In content can be obtained simultaneously on the top of this metamorphic buffer[l]. In this study, we used a step-garded In,Gai_,As buffer to increase the In composition up to x a . 3 0 on GaAs substrates, and fabricated various electronic devices based on this In0.2gQ.7 1As/Ino.3Gag.7As heterostructure.","PeriodicalId":244069,"journal":{"name":"52nd Annual Device Research Conference","volume":"199 ","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113982780","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-06-20DOI: 10.1109/DRC.1994.1009458
D. Eason, W. C. Hughes, J. Ren, K. Bowers, Z. Yu, J. Cook, J. Schetzina, G. Cantwell, W. Harsh
II-VI heterostructures composed of ZnSe-ZnTeSe layers have been employed to develop high-brightness green light-emitting diodes operating at peak wavelengths in the pure green spectral region (508-514 nm). The brightest devices produce 792 mu W (10 mA, 4V) peaked at 510 nm. This corresponds to an external efficiency of 2% and a luminous performance of 8.0 lumen/W.
利用由znse - znese层组成的II-VI异质结构制备了工作在纯绿色光谱区域(508-514 nm)峰值波长的高亮度绿色发光二极管。最亮的器件产生792 μ W (10 mA, 4V)，峰值为510 nm。这相当于2%的外部效率和8.0流明/瓦的发光性能。
{"title":"High-brightness green light-emitting diodes","authors":"D. Eason, W. C. Hughes, J. Ren, K. Bowers, Z. Yu, J. Cook, J. Schetzina, G. Cantwell, W. Harsh","doi":"10.1109/DRC.1994.1009458","DOIUrl":"https://doi.org/10.1109/DRC.1994.1009458","url":null,"abstract":"II-VI heterostructures composed of ZnSe-ZnTeSe layers have been employed to develop high-brightness green light-emitting diodes operating at peak wavelengths in the pure green spectral region (508-514 nm). The brightest devices produce 792 mu W (10 mA, 4V) peaked at 510 nm. This corresponds to an external efficiency of 2% and a luminous performance of 8.0 lumen/W.","PeriodicalId":244069,"journal":{"name":"52nd Annual Device Research Conference","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114548247","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-06-20DOI: 10.1109/DRC.1994.1009417
K. Gotoh, H. Takauchi, A. Yoshida, H. Tamura, N. Yokoyama
{"title":"SrTiO3-channel thin-film transistor","authors":"K. Gotoh, H. Takauchi, A. Yoshida, H. Tamura, N. Yokoyama","doi":"10.1109/DRC.1994.1009417","DOIUrl":"https://doi.org/10.1109/DRC.1994.1009417","url":null,"abstract":"","PeriodicalId":244069,"journal":{"name":"52nd Annual Device Research Conference","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130218948","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-06-20DOI: 10.1109/DRC.1994.1009439
S. Lee, L.Y. Lin, K. Pister, M. Wu
We report the first fabrication of vertical three-dimensional micro-Fresnel lenses with polysilicon materials by surface micromachining technique. Micro-Fresnel lenses play a very important role in micro-optics because of their thin film structures and their ability to achieve very short focal lengths. Although micro-Fresnel lenses have been studied and well understood [ 11, the lens planes usually are restrained on the surface of the substrate. Therefore, their abilities of integration with other optoelectronic components in micro-optics are limited. In this paper, we present a vertical three-dimensional binary-phase micro-Fresnel lens which overcomes the disadvantage of conventional micro-fresnel lenses and is able to rotate out of the plane and stands perpendicular to the substrate. This lens and other similarly constructed micro-optical elements can shrink the whole free-space optical system to a single micro-chip. They have applications in free-space optical interconnect, packaging and optical storage. The fabrication of the vertical micro-Fresnel lens has been reported [2]. The lens plate is supported by micro-hinges and spring latches [3]. In this paper, we report the coupling experiments of semiconductor laser diodes and optical fibers using the vertical micro-Fresnel lens. The schematic structure of the micro-Fresnel lens is shown in Fig. 1. A 1.3pm laser diode or an optical fiber is placed at the focal point of the lens to collimate the optical beams. The collimated beam profile is shown in Fig. 2 and Fig. 3 for laser diode and optical fiber sources, respectively. The divergence angles of the laser diode 2Oox4O0, and the collimated beam shows an elliptical contour. A circular contour is observed for the collimated beam from optical fibers, which has a divergence angle of 7.0”. The collimated beam has a divergence angle of 0.43”. The threedimensional beam profile is also shown. The collecting efficiency of the lens is higher than 50%. Efficiency can be further improved by using transmissive binary lens rather than brighvdark Fresnel lens. Since the vertical micro-Fresnel lenses and other similarly fabricated threedimensional micro-optical components can be pre-aligned during the design stage of the layout, they can be integrated in a micro-chip with other active micro-optical elements such as semiconductor lasers and isolators. Therefore, we believe that they are very promising in the integrated micro-optics. In conclusion, a micromachined vertical three-dimensional micro-Fresnel is demonstrated, It is shown to be very successful in collimating beams fiom both an optical fiber tip and directly from a semiconductor laser. With the micro-Fresnel lens’ unique three-dimensional structure and with other similarly fabricated three-dimensional micro-optical components such as rotatable mirrors, beam-splitters and gratings, we can implement integrable free-space optics with this technique, These results &ow a promising hture in reducing the cost
{"title":"Micromachined vertical three-dimensional micro-fresnel lenses for free-space integrated micro-optics","authors":"S. Lee, L.Y. Lin, K. Pister, M. Wu","doi":"10.1109/DRC.1994.1009439","DOIUrl":"https://doi.org/10.1109/DRC.1994.1009439","url":null,"abstract":"We report the first fabrication of vertical three-dimensional micro-Fresnel lenses with polysilicon materials by surface micromachining technique. Micro-Fresnel lenses play a very important role in micro-optics because of their thin film structures and their ability to achieve very short focal lengths. Although micro-Fresnel lenses have been studied and well understood [ 11, the lens planes usually are restrained on the surface of the substrate. Therefore, their abilities of integration with other optoelectronic components in micro-optics are limited. In this paper, we present a vertical three-dimensional binary-phase micro-Fresnel lens which overcomes the disadvantage of conventional micro-fresnel lenses and is able to rotate out of the plane and stands perpendicular to the substrate. This lens and other similarly constructed micro-optical elements can shrink the whole free-space optical system to a single micro-chip. They have applications in free-space optical interconnect, packaging and optical storage. The fabrication of the vertical micro-Fresnel lens has been reported [2]. The lens plate is supported by micro-hinges and spring latches [3]. In this paper, we report the coupling experiments of semiconductor laser diodes and optical fibers using the vertical micro-Fresnel lens. The schematic structure of the micro-Fresnel lens is shown in Fig. 1. A 1.3pm laser diode or an optical fiber is placed at the focal point of the lens to collimate the optical beams. The collimated beam profile is shown in Fig. 2 and Fig. 3 for laser diode and optical fiber sources, respectively. The divergence angles of the laser diode 2Oox4O0, and the collimated beam shows an elliptical contour. A circular contour is observed for the collimated beam from optical fibers, which has a divergence angle of 7.0”. The collimated beam has a divergence angle of 0.43”. The threedimensional beam profile is also shown. The collecting efficiency of the lens is higher than 50%. Efficiency can be further improved by using transmissive binary lens rather than brighvdark Fresnel lens. Since the vertical micro-Fresnel lenses and other similarly fabricated threedimensional micro-optical components can be pre-aligned during the design stage of the layout, they can be integrated in a micro-chip with other active micro-optical elements such as semiconductor lasers and isolators. Therefore, we believe that they are very promising in the integrated micro-optics. In conclusion, a micromachined vertical three-dimensional micro-Fresnel is demonstrated, It is shown to be very successful in collimating beams fiom both an optical fiber tip and directly from a semiconductor laser. With the micro-Fresnel lens’ unique three-dimensional structure and with other similarly fabricated three-dimensional micro-optical components such as rotatable mirrors, beam-splitters and gratings, we can implement integrable free-space optics with this technique, These results &ow a promising hture in reducing the cost","PeriodicalId":244069,"journal":{"name":"52nd Annual Device Research Conference","volume":"53 92 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126074869","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-06-20DOI: 10.1109/DRC.1994.1009449
S. Wada, M. Tokushima, M. Fukaishi, N. Matsuno, H. Yano, H. Hida
{"title":"\"A sub-0.25/spl mu/m symmetric super self-aligned gate hjfet witn reduced gate fringing capacitance fabricated using electroless au plating and collimated sputtering\"","authors":"S. Wada, M. Tokushima, M. Fukaishi, N. Matsuno, H. Yano, H. Hida","doi":"10.1109/DRC.1994.1009449","DOIUrl":"https://doi.org/10.1109/DRC.1994.1009449","url":null,"abstract":"","PeriodicalId":244069,"journal":{"name":"52nd Annual Device Research Conference","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128124997","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-06-20DOI: 10.1109/DRC.1994.1009403
J. Ajit, D. Kinzer
The Double-Diffused power MOSFET (DMOSFET) and IGBT [ I ] are extensively used in power switching applications. The DMOSFET has fast switching characteristics but has high on-state drop for high voltage applications. The IGBT utilizes bipolar current conduction to achieve a low on-state drop but has slow switching characteristics. When the switching speed of the IGBT is improved by minority-carrier lifetime reduction, its forward drop increases. Consequently, IGBTs with turn-off time less than 250ns are not used in applications. The current conduction capability of other MOS-controlled bipolar transistor structures reported [2-4] is limited by the high on-resistance of the integrated high-voltage driver DMOSFET. This paper describes a new three-terminal device structure called Bipolar-Injection Coupled MOSFET (BIFET) which has a lower on-state drop compared to the DMOSFET while still retaining the fast switching characteristics and high avalanche capability of the DMOSFET.
{"title":"A novel bipolar injection coupled power mosfet (bifet)","authors":"J. Ajit, D. Kinzer","doi":"10.1109/DRC.1994.1009403","DOIUrl":"https://doi.org/10.1109/DRC.1994.1009403","url":null,"abstract":"The Double-Diffused power MOSFET (DMOSFET) and IGBT [ I ] are extensively used in power switching applications. The DMOSFET has fast switching characteristics but has high on-state drop for high voltage applications. The IGBT utilizes bipolar current conduction to achieve a low on-state drop but has slow switching characteristics. When the switching speed of the IGBT is improved by minority-carrier lifetime reduction, its forward drop increases. Consequently, IGBTs with turn-off time less than 250ns are not used in applications. The current conduction capability of other MOS-controlled bipolar transistor structures reported [2-4] is limited by the high on-resistance of the integrated high-voltage driver DMOSFET. This paper describes a new three-terminal device structure called Bipolar-Injection Coupled MOSFET (BIFET) which has a lower on-state drop compared to the DMOSFET while still retaining the fast switching characteristics and high avalanche capability of the DMOSFET.","PeriodicalId":244069,"journal":{"name":"52nd Annual Device Research Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129333755","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-06-20DOI: 10.1109/DRC.1994.1009394
A. Dodabalapur, L.J. Rothbergi, T. M. Miller
{"title":"Resonant-cavity light emitting diodes with organic semiconductors","authors":"A. Dodabalapur, L.J. Rothbergi, T. M. Miller","doi":"10.1109/DRC.1994.1009394","DOIUrl":"https://doi.org/10.1109/DRC.1994.1009394","url":null,"abstract":"","PeriodicalId":244069,"journal":{"name":"52nd Annual Device Research Conference","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114953082","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-06-20DOI: 10.1109/DRC.1994.1009423
S. Tiwari, H. Hanafi, A. Hartstein, E. Crabbé, A. R. Powell, S. Iyer, E. Tierney
{"title":"Novel capacitor-less high density low power vertical memory","authors":"S. Tiwari, H. Hanafi, A. Hartstein, E. Crabbé, A. R. Powell, S. Iyer, E. Tierney","doi":"10.1109/DRC.1994.1009423","DOIUrl":"https://doi.org/10.1109/DRC.1994.1009423","url":null,"abstract":"","PeriodicalId":244069,"journal":{"name":"52nd Annual Device Research Conference","volume":"92 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124432224","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-06-20DOI: 10.1109/DRC.1994.1009418
T. Uemura, T. Baba
Tunneling devices have attracted much interest because of their increased functionality due to NDR characteristics and inherently high-speed switching characteristics. Various tunnel transistors based on resonant tunneling have been studied up to now. Recently, we proposed a new tunnel device, the surface tunnel transistor (STT)'-'), in which an interband tunneling current between a degenerate n+-channel and p'-drain is controlled by a gate voltage. In order to implement the STT, we have developed a new fabrication process 'utilizing MBE regrowth techniques and observed the direct modulation of NDR characteristics by the gate in the new structure. Moreover, utilizing these NDR characteristics of the STT, a bistable circuit consisting of only two components (one STT and one load resistor) was realized and its operation was successfully confirmed. An STT with a VMOS-like structure was fabricated using a GaAdAlGaAs heterostructure. A 500-nm n+-GaAs source (n=lxlO" cm-'), a 200-nm i-GaAs layer, and a 150-nm p+-GaAs drain (p=1x1020 ~ m ~ ) were successively grown by MBE at 520 "C. In this device, it is important that the drain region should be highly degenerate and have a sharp doping interface with the i region. After making a sloped mesa structure by wet-chemical etching down to the source layer, the surface was cleaned at 410 "C using hydrogen radicals generated by cracking with a W-filament to regrow a channel and a gate layer, Since the residual oxygen at the regrown interface causes an increase of the valley current which weakens the NDR characteristics, it is important that the residual oxygen concentration be made as low as possible. Next, a 12-nm n+-GaAs channel (n=lxlO" cm"), a 40-nm i-Ab,Ga,7As gate insulator and a 10-nm p+-GaAs gate electrode (p=7x1Ol9 ~ m ~ ) were regrown by MBE at 520 "C. An interband tunneling junction is formed between the n+-channel and the p+-drain. After delimiting the gate region, the source, gate and drain electrodes were formed using lift-off techniques. The drain current of the fabricated STT exhibits clear NDR characteristics at room temperature under forward drain-bias condition. When the gate voltage changes from -0.8 V to 0.8 V, the peak-to-valley current ratio (PVR) increases from 1.25 to 4.80 and the peak current increases from 0.029 to 0.32 pA/pm. This increase of both PVR and peak current density with increasing the gate voltage reflects the direct modulation of the tunneling junction by the gate. In order to demonstrate the functionality of the STT, a bistable circuit was implemented consisting of only one STT and a 21-WZ load resistor connected to the drain in series. Bistable operation with output drain voltages of V,=0.25 V and Vp0.35 V was obtained at VG=0.4 V. Since the NDR characteristics can be controlled by the gate voltage, switching between these output levels can be performed by applying a voltage pulse to the gate, When the positive (negative) pulse of 0.2 V is applied to the gate, the drain
{"title":"Direct gate-controlled NDR characteristics in surface tunnel transistor","authors":"T. Uemura, T. Baba","doi":"10.1109/DRC.1994.1009418","DOIUrl":"https://doi.org/10.1109/DRC.1994.1009418","url":null,"abstract":"Tunneling devices have attracted much interest because of their increased functionality due to NDR characteristics and inherently high-speed switching characteristics. Various tunnel transistors based on resonant tunneling have been studied up to now. Recently, we proposed a new tunnel device, the surface tunnel transistor (STT)'-'), in which an interband tunneling current between a degenerate n+-channel and p'-drain is controlled by a gate voltage. In order to implement the STT, we have developed a new fabrication process 'utilizing MBE regrowth techniques and observed the direct modulation of NDR characteristics by the gate in the new structure. Moreover, utilizing these NDR characteristics of the STT, a bistable circuit consisting of only two components (one STT and one load resistor) was realized and its operation was successfully confirmed. An STT with a VMOS-like structure was fabricated using a GaAdAlGaAs heterostructure. A 500-nm n+-GaAs source (n=lxlO\" cm-'), a 200-nm i-GaAs layer, and a 150-nm p+-GaAs drain (p=1x1020 ~ m ~ ) were successively grown by MBE at 520 \"C. In this device, it is important that the drain region should be highly degenerate and have a sharp doping interface with the i region. After making a sloped mesa structure by wet-chemical etching down to the source layer, the surface was cleaned at 410 \"C using hydrogen radicals generated by cracking with a W-filament to regrow a channel and a gate layer, Since the residual oxygen at the regrown interface causes an increase of the valley current which weakens the NDR characteristics, it is important that the residual oxygen concentration be made as low as possible. Next, a 12-nm n+-GaAs channel (n=lxlO\" cm\"), a 40-nm i-Ab,Ga,7As gate insulator and a 10-nm p+-GaAs gate electrode (p=7x1Ol9 ~ m ~ ) were regrown by MBE at 520 \"C. An interband tunneling junction is formed between the n+-channel and the p+-drain. After delimiting the gate region, the source, gate and drain electrodes were formed using lift-off techniques. The drain current of the fabricated STT exhibits clear NDR characteristics at room temperature under forward drain-bias condition. When the gate voltage changes from -0.8 V to 0.8 V, the peak-to-valley current ratio (PVR) increases from 1.25 to 4.80 and the peak current increases from 0.029 to 0.32 pA/pm. This increase of both PVR and peak current density with increasing the gate voltage reflects the direct modulation of the tunneling junction by the gate. In order to demonstrate the functionality of the STT, a bistable circuit was implemented consisting of only one STT and a 21-WZ load resistor connected to the drain in series. Bistable operation with output drain voltages of V,=0.25 V and Vp0.35 V was obtained at VG=0.4 V. Since the NDR characteristics can be controlled by the gate voltage, switching between these output levels can be performed by applying a voltage pulse to the gate, When the positive (negative) pulse of 0.2 V is applied to the gate, the drain","PeriodicalId":244069,"journal":{"name":"52nd Annual Device Research Conference","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125376664","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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