Pub Date : 1994-06-20DOI: 10.1109/DRC.1994.1009399
W. Xie, J. Cooper, M. Melloch
N-channel MOSFETs are fabricatedin p-type epilayers grown on a p+ (Si-face) 6H-Sic substrate. The epilayers are doped with A1 to 2x1016 cm-3, and are 3 pm thick. Substrates with epilayers were obtained from Cree Research, Durham, NC. Registration marks are produced by R E using an aluminum etch mask. Source and drain regions are then formed by selective-area ion implantation of N to a concentration of lx1019 cm-3. A second implant introduces A1 at a concentration of 1x1018 cm-3 into regions outside the active devices to serve as a chanstop. Both implantations are masked with Ti and are conducted with the sample at an elevated temperature. The implants are then activated at the same time by a high temperature anneal in Ar. A 500 8, thick gate oxide is grown by wet thermal oxidation at 1150 OC, followed by a 30 min. in-situ anneal in Ar. Source and drain ohmic contacts are formed by E-beam evaporated Ni, which is pattemed by liftoff. p-type ohmic contacts are also formed to the chanstop region by evaporation of Al, which is also pattemed by liftoff. Both ohmic contacts are then annealed at high temperature in Ar. Finally, gate and interconnect metal is formed by evaporated AI, forming non-selfaligned metal-gate MOSFETs.
{"title":"NMOS digital integrated circuits in 6h silicon carbide","authors":"W. Xie, J. Cooper, M. Melloch","doi":"10.1109/DRC.1994.1009399","DOIUrl":"https://doi.org/10.1109/DRC.1994.1009399","url":null,"abstract":"N-channel MOSFETs are fabricatedin p-type epilayers grown on a p+ (Si-face) 6H-Sic substrate. The epilayers are doped with A1 to 2x1016 cm-3, and are 3 pm thick. Substrates with epilayers were obtained from Cree Research, Durham, NC. Registration marks are produced by R E using an aluminum etch mask. Source and drain regions are then formed by selective-area ion implantation of N to a concentration of lx1019 cm-3. A second implant introduces A1 at a concentration of 1x1018 cm-3 into regions outside the active devices to serve as a chanstop. Both implantations are masked with Ti and are conducted with the sample at an elevated temperature. The implants are then activated at the same time by a high temperature anneal in Ar. A 500 8, thick gate oxide is grown by wet thermal oxidation at 1150 OC, followed by a 30 min. in-situ anneal in Ar. Source and drain ohmic contacts are formed by E-beam evaporated Ni, which is pattemed by liftoff. p-type ohmic contacts are also formed to the chanstop region by evaporation of Al, which is also pattemed by liftoff. Both ohmic contacts are then annealed at high temperature in Ar. Finally, gate and interconnect metal is formed by evaporated AI, forming non-selfaligned metal-gate MOSFETs.","PeriodicalId":244069,"journal":{"name":"52nd Annual Device Research Conference","volume":"105 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134563993","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-06-20DOI: 10.1109/DRC.1994.1009411
S. Talwar, M. Cao, K. Kramer, G. Verma, K. Saraswat, T. Sigmon
Plasma hydrogenation has long been used to passivate grain boundary states in poly-Si TFTs . I Device performance improves significantly with the incorporation of hydrogen. However, long term stability has been shown to suffer.2 We report a technique for low temperature TFT fabrication suitable for display driver circuit applications on glass, providing excellent device characteristics without the need for intentional hydrogenation. A pulsed XeCl excimer laser was used to recrystallize pre-patterned a-silicon. High mobility, low leakage currents, and sharp subthreshold slopes have been achieved. The enhanced device performance over previous reported results is attributed to pre-patterning before laser annealing leading to enhanced lateral grain growth.
{"title":"High performance poly-si thin film transistors (TFTs) fabricated by xecl excimer laser annealing without post-hydrogenation","authors":"S. Talwar, M. Cao, K. Kramer, G. Verma, K. Saraswat, T. Sigmon","doi":"10.1109/DRC.1994.1009411","DOIUrl":"https://doi.org/10.1109/DRC.1994.1009411","url":null,"abstract":"Plasma hydrogenation has long been used to passivate grain boundary states in poly-Si TFTs . I Device performance improves significantly with the incorporation of hydrogen. However, long term stability has been shown to suffer.2 We report a technique for low temperature TFT fabrication suitable for display driver circuit applications on glass, providing excellent device characteristics without the need for intentional hydrogenation. A pulsed XeCl excimer laser was used to recrystallize pre-patterned a-silicon. High mobility, low leakage currents, and sharp subthreshold slopes have been achieved. The enhanced device performance over previous reported results is attributed to pre-patterning before laser annealing leading to enhanced lateral grain growth.","PeriodicalId":244069,"journal":{"name":"52nd Annual Device Research Conference","volume":"63 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132408460","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-06-20DOI: 10.1109/DRC.1994.1009455
S.C. Wang, M. Kao, S. Liu, P. Ho, K. Duh
A double heterojunction pseudomorphic structure was grown by MBE on Fe-doped semiinsulating InP substrate. The layers consisted of a thin InAlAs buffer, a pseudomorphic IQ 67G% 33As channel with InAlAs spacer and Si planar doping on both sides of the channel. On topof the'channel is the undoped InAlAs gate layer and the n+ InGaAs cap layer. The 77K sheet charge density and mobility were determined by Hall measurement to be 2.9~1012 cm-2 and 29,000 cmZNs, respectively.
{"title":"High performance w-band pseudomorphic InAlAs/InGaAs/InP power HEMTs","authors":"S.C. Wang, M. Kao, S. Liu, P. Ho, K. Duh","doi":"10.1109/DRC.1994.1009455","DOIUrl":"https://doi.org/10.1109/DRC.1994.1009455","url":null,"abstract":"A double heterojunction pseudomorphic structure was grown by MBE on Fe-doped semiinsulating InP substrate. The layers consisted of a thin InAlAs buffer, a pseudomorphic IQ 67G% 33As channel with InAlAs spacer and Si planar doping on both sides of the channel. On topof the'channel is the undoped InAlAs gate layer and the n+ InGaAs cap layer. The 77K sheet charge density and mobility were determined by Hall measurement to be 2.9~1012 cm-2 and 29,000 cmZNs, respectively.","PeriodicalId":244069,"journal":{"name":"52nd Annual Device Research Conference","volume":"71 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133859864","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-06-20DOI: 10.1109/DRC.1994.1009452
G. Berthold, A. Neviani, E. Zanoni, M. Manfredi, M. Pavesi, C. Canali, J. D. del Alamo, S. Bahl
Increasing the I d s mole fraction in InGaAs-base heterostructure FET's W E T ' S) leads to improved device performance due to the superior carrier transport properties of these materials. At the same time, however, the use of narrow band-gap semiconductors results in enhanced impact-ionization, with severe detrimental effects like excessive shot noise in ID and large gate current IG even at regular bias points. Detailed physical understanding of impact-ionization and of the behaviour of the copious amount of holes that are generated in InGaAs channels is crucial to developing guidelines for designing high-performance devices. Gate current measurements 'and electroluminescence spectra have been widely adopted to evaluate hot-electron effects and impact-ionization in GaAs-based MESFET's and HEMT's, but no agreement has been found as of the origin of the different spectral components of the emitted radiation. In any case, no work has been presented, up to now, in InGaAs-based WET'S. In this paper we cam' out a detailed study of gate current and its correlation w i t h the various spectral components of light emitted in InAlAs/InGaAs HFET's at regular bias points. Our work reveals that light emitted in the visible portion of the spectrum is a good signature of impact-ionization in the channel as impact-ionized holes recombine with channel electrons. On the other hand. light emitted in the infrared portion of the spectrum is found to originate in conduction band-to-conduction band transitions of the hot electrons in the channel. These findings establish electroluminescence in the appropriate spectral range as an ideal tool to characterize hot carrier phenomena in InP-based HFET's, and allowed us for the first time to quuntitavely separate the gate current into its electron and hole components. The devices characterized in ths work are n-channel normally-on L = 1 pm InAIAs/lnGaAs HFET's, with an 100 A n+-In0 ;jGaO 47As Si-doped channel (Nsi = 8 x lo1* ~ m-~) , a 300 In0.41Alo. j9As strained insulator'and a '50 A In0 j3Ga0.47As cap layer. When these devices are biased at high Vds (23 V), sigmficant impact-ionizkon takes place in the channel. A detailed study of the gate current reveals that, for negative Vgs, IG is dominated by collection of impact-ionized holes, while for positive Vgs, IG is dominated by electron real-space-transfer at low V h , and by hole collection at high Vds. Light emission both in the infrared and visible region takes place at high Vds. The …
{"title":"Electroluminescence and gate current components of InAlAs/InGaAs HEFT's","authors":"G. Berthold, A. Neviani, E. Zanoni, M. Manfredi, M. Pavesi, C. Canali, J. D. del Alamo, S. Bahl","doi":"10.1109/DRC.1994.1009452","DOIUrl":"https://doi.org/10.1109/DRC.1994.1009452","url":null,"abstract":"Increasing the I d s mole fraction in InGaAs-base heterostructure FET's W E T ' S) leads to improved device performance due to the superior carrier transport properties of these materials. At the same time, however, the use of narrow band-gap semiconductors results in enhanced impact-ionization, with severe detrimental effects like excessive shot noise in ID and large gate current IG even at regular bias points. Detailed physical understanding of impact-ionization and of the behaviour of the copious amount of holes that are generated in InGaAs channels is crucial to developing guidelines for designing high-performance devices. Gate current measurements 'and electroluminescence spectra have been widely adopted to evaluate hot-electron effects and impact-ionization in GaAs-based MESFET's and HEMT's, but no agreement has been found as of the origin of the different spectral components of the emitted radiation. In any case, no work has been presented, up to now, in InGaAs-based WET'S. In this paper we cam' out a detailed study of gate current and its correlation w i t h the various spectral components of light emitted in InAlAs/InGaAs HFET's at regular bias points. Our work reveals that light emitted in the visible portion of the spectrum is a good signature of impact-ionization in the channel as impact-ionized holes recombine with channel electrons. On the other hand. light emitted in the infrared portion of the spectrum is found to originate in conduction band-to-conduction band transitions of the hot electrons in the channel. These findings establish electroluminescence in the appropriate spectral range as an ideal tool to characterize hot carrier phenomena in InP-based HFET's, and allowed us for the first time to quuntitavely separate the gate current into its electron and hole components. The devices characterized in ths work are n-channel normally-on L = 1 pm InAIAs/lnGaAs HFET's, with an 100 A n+-In0 ;jGaO 47As Si-doped channel (Nsi = 8 x lo1* ~ m-~) , a 300 In0.41Alo. j9As strained insulator'and a '50 A In0 j3Ga0.47As cap layer. When these devices are biased at high Vds (23 V), sigmficant impact-ionizkon takes place in the channel. A detailed study of the gate current reveals that, for negative Vgs, IG is dominated by collection of impact-ionized holes, while for positive Vgs, IG is dominated by electron real-space-transfer at low V h , and by hole collection at high Vds. Light emission both in the infrared and visible region takes place at high Vds. The …","PeriodicalId":244069,"journal":{"name":"52nd Annual Device Research Conference","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132849148","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-06-20DOI: 10.1109/DRC.1994.1009460
N. Moll, D. Mars, A. Fischer-Colbrie
While early work on such devices focussed on low-temperature operation, because of small gain and small collector base barriers' ', advances in material technology have lead to successful operation of hot-electron transistors at room temperature, with materials lattice matched to GaSb3, or to InP4. These devices achieve respectable current gain by the use of a significant offset between the emitter injection energy and the collector barrier to allow for energy loss by hot carriers as they traverse the base, and to reduce quantum mechanical reflection at the collector.
{"title":"Heteroelectronic injection transistors for room-temterature operation","authors":"N. Moll, D. Mars, A. Fischer-Colbrie","doi":"10.1109/DRC.1994.1009460","DOIUrl":"https://doi.org/10.1109/DRC.1994.1009460","url":null,"abstract":"While early work on such devices focussed on low-temperature operation, because of small gain and small collector base barriers' ', advances in material technology have lead to successful operation of hot-electron transistors at room temperature, with materials lattice matched to GaSb3, or to InP4. These devices achieve respectable current gain by the use of a significant offset between the emitter injection energy and the collector barrier to allow for energy loss by hot carriers as they traverse the base, and to reduce quantum mechanical reflection at the collector.","PeriodicalId":244069,"journal":{"name":"52nd Annual Device Research Conference","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126250140","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-06-20DOI: 10.1109/DRC.1994.1009402
A. Bhalla, T. Chow
In this paper we present a 600V Emitter Switched Thyristor with a Divener (ESTD, Fig. 2), wlth a novel stnpe design, that incorporates a p-channel diverter adjacent to the floating emitter. The Emitter Switched Thyristor (EST, Fig. 1)[1,2] is a MOS-controlled thyristor that has been demonstrated to have the unique feature of gate controlled current saturation after the thyristor latches on. This current saturation feature is retained in the ESTD. which improves the maximum controllable current of the EST with a small penalty in the forward drop. During turn-off, a negative gate voltage is applied to activate the diverter, creating a p-channel that draws away part of the hole current from the p-well. The hole current flowing under the n+ source is thereby reduced, and latching of the parasitic thyristor is suppressed to higher total current levels, increasing the maximum controllable current. Since the hole current has two alternate paths, i.e. into the cathode contact and out via the diverter MOSFET (Fig. 4), the plasma is squeezed rather like in a GTO. For a linear stripe design, there is a factor of 4 maximum theoretical improvement in controllable current density for the situation of negligible p-channel resistance. The turn-on region and the diverter MOSFET occupy the same region in the device. This leads to an increased JFET resistance in series with the lateral MOSFETs, making it harder to turn the device on. Although the thyristor latching current is relatively unchanged if the floating emitter length is the same as the EST, there is a larger knee in the forward characteristic. (This problem can be alleviated by using a heavier JFET implant.) However, once the thyristor is latched, the difference in the forward drops is small. T h e simulated forward characteristics (Fig. 3) of an EST and ESTD for ~,,,=3p, .tP=0.3ps, show the knee in the ESTD characteristic, and the small increase in forward drop with respect to the EST. (These lifetime values were estimated from the measured IGBT turn-off current waveform on the same wafer, which gave a high level lifetime rn0+ T of 3.3 p.) Snubberless resistive turn-off simulations (1OOV) showed that the EST successfully turned off 200A/cm2, Pp faling at 300A/cm2 while the ESTD failed just above 700A/cm2. In these simulations, a uniform ndrift layer doping of l O " b K 3 , thickness 50p-1, p-well surface concentration of 1017cm-3, junction depth 3 p , p-base surface concentration 3 X 1017cm-3, junction depth of 3.6pm, n+ surface concentration of 1020cm-3, junction depth l p , and a oxide thickness of lOOnm was assumed. Both ESTs and ESDTs were fabricated on wafers with a 0.02Q-cm, Sopm nepi, 3R-cm n buffer on a p+ substrate. In this study, single-cell devices (300pm long stripes) were compared. These devices were fabricated with six closely spaced floating field rings leading to the main termination designed for a 600V breakdown voltage. This eliminated the need for large p+ areas under the pads connect
{"title":"ESTD: an emitter switched thyristor with a diverter","authors":"A. Bhalla, T. Chow","doi":"10.1109/DRC.1994.1009402","DOIUrl":"https://doi.org/10.1109/DRC.1994.1009402","url":null,"abstract":"In this paper we present a 600V Emitter Switched Thyristor with a Divener (ESTD, Fig. 2), wlth a novel stnpe design, that incorporates a p-channel diverter adjacent to the floating emitter. The Emitter Switched Thyristor (EST, Fig. 1)[1,2] is a MOS-controlled thyristor that has been demonstrated to have the unique feature of gate controlled current saturation after the thyristor latches on. This current saturation feature is retained in the ESTD. which improves the maximum controllable current of the EST with a small penalty in the forward drop. During turn-off, a negative gate voltage is applied to activate the diverter, creating a p-channel that draws away part of the hole current from the p-well. The hole current flowing under the n+ source is thereby reduced, and latching of the parasitic thyristor is suppressed to higher total current levels, increasing the maximum controllable current. Since the hole current has two alternate paths, i.e. into the cathode contact and out via the diverter MOSFET (Fig. 4), the plasma is squeezed rather like in a GTO. For a linear stripe design, there is a factor of 4 maximum theoretical improvement in controllable current density for the situation of negligible p-channel resistance. The turn-on region and the diverter MOSFET occupy the same region in the device. This leads to an increased JFET resistance in series with the lateral MOSFETs, making it harder to turn the device on. Although the thyristor latching current is relatively unchanged if the floating emitter length is the same as the EST, there is a larger knee in the forward characteristic. (This problem can be alleviated by using a heavier JFET implant.) However, once the thyristor is latched, the difference in the forward drops is small. T h e simulated forward characteristics (Fig. 3) of an EST and ESTD for ~,,,=3p, .tP=0.3ps, show the knee in the ESTD characteristic, and the small increase in forward drop with respect to the EST. (These lifetime values were estimated from the measured IGBT turn-off current waveform on the same wafer, which gave a high level lifetime rn0+ T of 3.3 p.) Snubberless resistive turn-off simulations (1OOV) showed that the EST successfully turned off 200A/cm2, Pp faling at 300A/cm2 while the ESTD failed just above 700A/cm2. In these simulations, a uniform ndrift layer doping of l O \" b K 3 , thickness 50p-1, p-well surface concentration of 1017cm-3, junction depth 3 p , p-base surface concentration 3 X 1017cm-3, junction depth of 3.6pm, n+ surface concentration of 1020cm-3, junction depth l p , and a oxide thickness of lOOnm was assumed. Both ESTs and ESDTs were fabricated on wafers with a 0.02Q-cm, Sopm nepi, 3R-cm n buffer on a p+ substrate. In this study, single-cell devices (300pm long stripes) were compared. These devices were fabricated with six closely spaced floating field rings leading to the main termination designed for a 600V breakdown voltage. This eliminated the need for large p+ areas under the pads connect","PeriodicalId":244069,"journal":{"name":"52nd Annual Device Research Conference","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126775886","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-06-20DOI: 10.1109/DRC.1994.1009413
H. Ogihara, M. Yoshimaru, S. Takase, H. Kurogi, H. Tamura, A. Kita, M. Ino
The main issue of the high density DRAM cell is to obtain the sufficient cell capacitance in a small area. Many kinds of capacitor structures, for example, cylindrical(1) or crown(2) type stacked cells have been proposed to solve this problem. However, the storage node height of these cells is so high that the following patterning processes become very difficult. Furthermore, their process steps are essentially complex. In this paper, we propose the double-sided rugged poly Si FIN STC technology, having low aspect storage node without any complex processes. This technology is proved to be applicable to 256Mb DRAMs and beyond. The key technology of this cell is to control the shapes of the rugged poly Si by ion implantation. These shapes are changed by ion implantation with arsenic dose more than 5E15 cm-2. Neighboring grains connected each other. These rugged poly Si shapes don't change during the following ion activation annealing. Using this film as the storage node, the FIN structure with the rugged shape on both the upper and the lower surface are achieved. By the TEM observation, there is no sharp edge of the storage node rugged poly Si surface and no thinning of the ONO dielectric film. In this experiment, these capacitors with 2FINs were fabricated in 1.2x0.6 um2 area (cell size for the 256Mb DRAMs ). The total storage node height has become 300nm. The increase ratio of the effective surface area is calculated from C-V measurement for the rugged FIN STC, the conventional FIN STC and the conventional STC. The effective surface area of the rugged FIN STC is 1.8 times as large as that of the conventional FIN STC, and 3.6 times as large as that of the conventional STC. The calculated cell capacitance of the 256Mb DRAM can reach to 25 fJ?/bit with 4 . 5 ~ 1 thickness ONO film. From the cell capacitance dependence on the frequency, there is no degradation in the high frequency region up to 1MHz. It shows that the sheet resistance of this rugged poly Si film is enough low because each grain is connected to the neighboring grains. There is no degradation in I-V characteristics compared with the conventional FIN STC. In conclusion, 25fFbit cell capacitance can be obtained in STC with 2FINs by using this technology. The total storage node height (300nm) is low enough, and there is no degradation in the C-V or I-V characteristic. We demonstrated this rugged FIN STC is one of the most suitable cell structures for the 256Mb DRAMs and beyond because it doesn't need no complex process steps. The separated-grain poly Si is deposited by LPCVD.
{"title":"Double-sided rugged poly Si FIN STC (stacked capacitor cell) technology for high density DRAMs","authors":"H. Ogihara, M. Yoshimaru, S. Takase, H. Kurogi, H. Tamura, A. Kita, M. Ino","doi":"10.1109/DRC.1994.1009413","DOIUrl":"https://doi.org/10.1109/DRC.1994.1009413","url":null,"abstract":"The main issue of the high density DRAM cell is to obtain the sufficient cell capacitance in a small area. Many kinds of capacitor structures, for example, cylindrical(1) or crown(2) type stacked cells have been proposed to solve this problem. However, the storage node height of these cells is so high that the following patterning processes become very difficult. Furthermore, their process steps are essentially complex. In this paper, we propose the double-sided rugged poly Si FIN STC technology, having low aspect storage node without any complex processes. This technology is proved to be applicable to 256Mb DRAMs and beyond. The key technology of this cell is to control the shapes of the rugged poly Si by ion implantation. These shapes are changed by ion implantation with arsenic dose more than 5E15 cm-2. Neighboring grains connected each other. These rugged poly Si shapes don't change during the following ion activation annealing. Using this film as the storage node, the FIN structure with the rugged shape on both the upper and the lower surface are achieved. By the TEM observation, there is no sharp edge of the storage node rugged poly Si surface and no thinning of the ONO dielectric film. In this experiment, these capacitors with 2FINs were fabricated in 1.2x0.6 um2 area (cell size for the 256Mb DRAMs ). The total storage node height has become 300nm. The increase ratio of the effective surface area is calculated from C-V measurement for the rugged FIN STC, the conventional FIN STC and the conventional STC. The effective surface area of the rugged FIN STC is 1.8 times as large as that of the conventional FIN STC, and 3.6 times as large as that of the conventional STC. The calculated cell capacitance of the 256Mb DRAM can reach to 25 fJ?/bit with 4 . 5 ~ 1 thickness ONO film. From the cell capacitance dependence on the frequency, there is no degradation in the high frequency region up to 1MHz. It shows that the sheet resistance of this rugged poly Si film is enough low because each grain is connected to the neighboring grains. There is no degradation in I-V characteristics compared with the conventional FIN STC. In conclusion, 25fFbit cell capacitance can be obtained in STC with 2FINs by using this technology. The total storage node height (300nm) is low enough, and there is no degradation in the C-V or I-V characteristic. We demonstrated this rugged FIN STC is one of the most suitable cell structures for the 256Mb DRAMs and beyond because it doesn't need no complex process steps. The separated-grain poly Si is deposited by LPCVD.","PeriodicalId":244069,"journal":{"name":"52nd Annual Device Research Conference","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129244686","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/DRC.1994.1009430
V. Arbet-Engels, W. Chang, E. Yablonovitch, G. Sullivan, M. Szwed, M. Chang
The IC industry lias rcaclicd tlic tlircsliold wlicrc tlic device pcrformance is limitcd by traditional packaging concepts. For instance, tlie trend toward higher frequcncy operation of GaAs/AlGaAs Iieterqjunction bipolar transistors (HBT) lias manifested itself in the ever increasing nced for ncw packaging systems in ordcr to lower tlie thermal resistance ’I?. In particular. devices grown on semi-insulating GaAs substrates suffer to ii grcalcr cstcnt due to the poor thermal conductivity of 111-V compounds. In Silicon IC technology, liowevcr. llicse limitations are not as severe. due to the approsinlately 2.7 tiines larger thermal conductivity of Si respect to GaAs. Nevertheless, recent developments in thin film handling and processing technology have created new vistas for inovative packaging solutions. For esamplc, using tlie epitasial liftoff (ELO) technique ’. active layers of clcctronic circuitry can be isolated from their substrates on which they were synthesized and hrtl ier mounted onto diffcrcnt substratcs with suitable thermal properties.
集成电路行业的传统封装理念限制了IC器件的性能。例如，GaAs/AlGaAs双极晶体管(HBT)的高频工作趋势体现在为了降低热阻' I '而对新型封装系统的需求不断增加。在特定的。在半绝缘GaAs衬底上生长的器件由于111-V化合物的导热性差而遭受ii calcst。然而，在硅集成电路技术中。许可证限制没有那么严格。由于硅的导热系数比砷化镓高约2.7倍。然而，薄膜处理和加工技术的最新发展为创新包装解决方案创造了新的前景。例如，采用薄膜外延升空(ELO)技术。电子电路的有源层可以与它们合成的基板隔离，并安装在具有合适热性能的不同基板上。
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Pub Date : 1900-01-01DOI: 10.1109/DRC.1994.1009397
Hao Dong, A. Gopinath
Optical switch matrices are one of the fundamental devices in all optical communications systems. The branch switches perform the splitting of optical signals, while the crossbar switches route the optical signals and can be reconfigured. High-speed optical switches may be used for time-division multiplexing to utilize the high bandwidth of common single mode fibers, and as external modulators for signal encoding. Semi-insulating substrates are favorable for monolithic integration. Most current optical switches are passive, suffering from long coupling length(typical1y 0.5-1 .O cm), and losses. Active optical switches, however, can overcome these problems. They can be zero loss or even provide gain at lengths of only a few hundred micrometers. From a practical standpoint the high frequency response and simple structure of an active optical switch are its most attractive features. In this paper, we will present the 1x1, 1x2, and 2x2 active optical switch matrices as modulators, branch switches, and photonic crossbars respectively. All of these switches are lossless, 500 micrometer in length and fabricated on a semiinsulating substrate. The switches basically are ridge waveguide semiconductor optical amplifiers. The semiconductor amplifiers are composed of separate confinement multiple-quantum wells sandwiched within a heterostructure for high differential gain, narrow linewidth, low chirp, and high modulation frequency 1. The quantum wells are heavily doped p-type to improve the frequency response*-4. The ridge waveguide structure in our devices has been designed to support only the fundamental TE and TM modes which are degenerate. The 1x1 switch/modulator has been tested for a switch with about 30 dB extinguish ratio and for a modulator with a 19 GHz 3dB bandwidth small signal response. Equal power splitting/routing or signal gain will be shown in the 1x2 switch. Simultaneous routing of two optical signals will be shown in the 2x2 crossbar with signal gain. With properly biasing condition, the signal gain or attenuation can be enhanced. Efficient heat sink will improve the performance of the switches. All of these switch matrices are integrable with other electronic or optoelectronic devices.
{"title":"AlGaAs/GaAs active optical switch matrices","authors":"Hao Dong, A. Gopinath","doi":"10.1109/DRC.1994.1009397","DOIUrl":"https://doi.org/10.1109/DRC.1994.1009397","url":null,"abstract":"Optical switch matrices are one of the fundamental devices in all optical communications systems. The branch switches perform the splitting of optical signals, while the crossbar switches route the optical signals and can be reconfigured. High-speed optical switches may be used for time-division multiplexing to utilize the high bandwidth of common single mode fibers, and as external modulators for signal encoding. Semi-insulating substrates are favorable for monolithic integration. Most current optical switches are passive, suffering from long coupling length(typical1y 0.5-1 .O cm), and losses. Active optical switches, however, can overcome these problems. They can be zero loss or even provide gain at lengths of only a few hundred micrometers. From a practical standpoint the high frequency response and simple structure of an active optical switch are its most attractive features. In this paper, we will present the 1x1, 1x2, and 2x2 active optical switch matrices as modulators, branch switches, and photonic crossbars respectively. All of these switches are lossless, 500 micrometer in length and fabricated on a semiinsulating substrate. The switches basically are ridge waveguide semiconductor optical amplifiers. The semiconductor amplifiers are composed of separate confinement multiple-quantum wells sandwiched within a heterostructure for high differential gain, narrow linewidth, low chirp, and high modulation frequency 1. The quantum wells are heavily doped p-type to improve the frequency response*-4. The ridge waveguide structure in our devices has been designed to support only the fundamental TE and TM modes which are degenerate. The 1x1 switch/modulator has been tested for a switch with about 30 dB extinguish ratio and for a modulator with a 19 GHz 3dB bandwidth small signal response. Equal power splitting/routing or signal gain will be shown in the 1x2 switch. Simultaneous routing of two optical signals will be shown in the 2x2 crossbar with signal gain. With properly biasing condition, the signal gain or attenuation can be enhanced. Efficient heat sink will improve the performance of the switches. All of these switch matrices are integrable with other electronic or optoelectronic devices.","PeriodicalId":244069,"journal":{"name":"52nd Annual Device Research Conference","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121241357","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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