Pub Date : 1994-06-20DOI: 10.1109/DRC.1994.1009395
M. Grupen, Jin Wang, K. Hess
Applications such as optical interconnects have made the modulation response of semiconductor laser diodes of great interest. Details of the modulation response have been attributed to different carrier transport mechanisms. Two imporlaxit features of the modulation response are the resonant frequency and the amount of gain saturation, often referred to as the low frequency roll-off. There has been some disagreement conceriiing which carrier transport mechanisms are most important in determining these features, particularly the gain saturation. One view of gain saturation concentrates on the ca,pture of carriers in the bound states of the quantum well.' Althougli carrier ca.pture is a relatively fast process, Kan et. al. feel it may be slow enough to cause some accumulation of carriers in tlie continuum states above the quantum well. This accumulation could then form a diffusive barrier to the transport of free caxriers to the active region. Since electrons usually have a slower capture rate lhan holes, it was concluded that the slow difk'usion of electrons to tlie quantum well may be to blame €or gain saturation. An alteriiative view is that the capture rneclianism is too fast to limit the modulation response.2 Instead, the holes, with their low mobilities, are slow in moving to the quantum well, and, therefore, are the cause of poor modulation. To test this idea, Nagarajan el. el. measured the modulation responses of different strained InGaAs quantum well lasers. The devices differed in the width of the separate confinement region (SCIt) and the location of the quantum well within this region. They showed that a SCR that is wide on both the n and p sides has significant gain saturation. Furthermore, they showed that when the n side of the SCR is narrow but the p side is still wide, the amount of gain saturation is comparable to the case in which both sides are wide. Thus, it was concluded thak it is hole transport, and not electron tra#nsport, that causes a poor modulation response. We present an irivestigation into this issue that was conducted with the Minilase laser sirnulator. The simulation includes all of the principal read space transport mechanisms, including driftdiffusion in bulk regions, thermionic emission at heterojunctions, and carrier capture into bound quantum states. The simulation was used to calculate modulation responses for GaAsIAZGaAs lasers similar ixi geometry to tliose measured by Nagarajan et. al. These responses are shown in figure 1, and the results show lhe same trends observed in the experimental measurements. We will present similar calculations on strained InGaAs/AlGaAs lasers together with computer experinients that manipulate carrier mobilities, thermionic emission rates, and capture times. Our results show tliat it is neither the transport of electrons or holes tu the quantum well that results in gain saturation. Ilalher, low frequency roll-off is primarily due to electrons that fail to get captured by the qua
{"title":"The roles of carrier transport in determining the modulation of semiconductor quantum well lasers","authors":"M. Grupen, Jin Wang, K. Hess","doi":"10.1109/DRC.1994.1009395","DOIUrl":"https://doi.org/10.1109/DRC.1994.1009395","url":null,"abstract":"Applications such as optical interconnects have made the modulation response of semiconductor laser diodes of great interest. Details of the modulation response have been attributed to different carrier transport mechanisms. Two imporlaxit features of the modulation response are the resonant frequency and the amount of gain saturation, often referred to as the low frequency roll-off. There has been some disagreement conceriiing which carrier transport mechanisms are most important in determining these features, particularly the gain saturation. One view of gain saturation concentrates on the ca,pture of carriers in the bound states of the quantum well.' Althougli carrier ca.pture is a relatively fast process, Kan et. al. feel it may be slow enough to cause some accumulation of carriers in tlie continuum states above the quantum well. This accumulation could then form a diffusive barrier to the transport of free caxriers to the active region. Since electrons usually have a slower capture rate lhan holes, it was concluded that the slow difk'usion of electrons to tlie quantum well may be to blame €or gain saturation. An alteriiative view is that the capture rneclianism is too fast to limit the modulation response.2 Instead, the holes, with their low mobilities, are slow in moving to the quantum well, and, therefore, are the cause of poor modulation. To test this idea, Nagarajan el. el. measured the modulation responses of different strained InGaAs quantum well lasers. The devices differed in the width of the separate confinement region (SCIt) and the location of the quantum well within this region. They showed that a SCR that is wide on both the n and p sides has significant gain saturation. Furthermore, they showed that when the n side of the SCR is narrow but the p side is still wide, the amount of gain saturation is comparable to the case in which both sides are wide. Thus, it was concluded thak it is hole transport, and not electron tra#nsport, that causes a poor modulation response. We present an irivestigation into this issue that was conducted with the Minilase laser sirnulator. The simulation includes all of the principal read space transport mechanisms, including driftdiffusion in bulk regions, thermionic emission at heterojunctions, and carrier capture into bound quantum states. The simulation was used to calculate modulation responses for GaAsIAZGaAs lasers similar ixi geometry to tliose measured by Nagarajan et. al. These responses are shown in figure 1, and the results show lhe same trends observed in the experimental measurements. We will present similar calculations on strained InGaAs/AlGaAs lasers together with computer experinients that manipulate carrier mobilities, thermionic emission rates, and capture times. Our results show tliat it is neither the transport of electrons or holes tu the quantum well that results in gain saturation. Ilalher, low frequency roll-off is primarily due to electrons that fail to get captured by the qua","PeriodicalId":244069,"journal":{"name":"52nd Annual Device Research Conference","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115890132","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-06-20DOI: 10.1109/DRC.1994.1009420
Y. Nara, H. Kurata, T. Yamazaki, T. Sugii
The saturation drain current (drain voltage: 2V) at fixed gate overdrive (Vg-Vth=lV or 1.5V) was higher in higher S/D extension concentration devices at gate length of less than 0.3pm for nMOS. The extracted effective channel length (using the method proposed by ref.l) of high S/D extension concentration (dose: 6~10'~cm-~) device has shorter by about 45nm than lower SD extension concentration (dose: 2~10'~cm-~) device at Vg-Vth of 1V. This difference increases to about 72nm at Vg-Vth of 1.5V. Higher saturation drain current with higher S/D extension concentration is, therefore, attributed to the suppressed effective channel length modulation. This effect is remarkable in short channel devices because the modulation of effective channel length is less sensitive in longer channel devices. The SP extrinsic resistance in higher S/D extension concentration device has higher value and smaller gate voltage dependence. However, the reduction of effective channel length has major effect on the saturation drain current than the increase of S/D extrinsic resistance. For PMOS, saturation drain current with high S/D extension concentration (dose: 6x 1014cm-2) increased by more than 10% for 0.15pm device than that with low S/D extension concentration (dose: 4~10'~cm-~). This increase is attributed to shorter effective channel length in high S/D extension concentration device. The modulation of effective channel length is smaller in PMOS than in nMOS because the carrier concentration at the extension region may be increased by the impurity diffusion from S/D regions. Propagation delay time (Tpd) of the 0.15pm CMOS inverters was calculated using extracted SPICE parameters. The load capacitance dependence of Tpd was 0.488ps/fF and 0.416pslfF for low (dose: 4~1O'~cm-~) and high (dose: 6x10 14cm-2) S/D extension concentration, respectively, showing that about 15% higher load drivability is obtained in high SD extension concentration device. Hot-carrier reliability We examined the degradation of drain current (AId/Ido) in nMOS under DC stress. The stress gate voltage was chosen for substrate current to be maximum for each stress drain voltage. We defined the hot-carrier life time as the stress time for 10% drain current degradation. We found that the life time was longer with higher S/D extension concentration and that the allowable drain voltage to 10 years DC life time was 1.9Y If we adjust the stress condition as same substrate current (same impact ionization rate), the surface state generation estimated from the increase in charge pumping current is almost the same for high and low S/D extension concentration devices. However, AWdo is lower with higher SD extension concentration. We speculate that the increase in S/D extension resistance caused by the surface state generation is relaxed by screening effect of increased carrier concentration in higher S/D extension concentration device. Summary We have demonstrated that higher-concentration SD extension devices h
{"title":"Impact of highly-doped s/d extension on the current drivability and reliability in 0.15/spl mu/m CMOS","authors":"Y. Nara, H. Kurata, T. Yamazaki, T. Sugii","doi":"10.1109/DRC.1994.1009420","DOIUrl":"https://doi.org/10.1109/DRC.1994.1009420","url":null,"abstract":"The saturation drain current (drain voltage: 2V) at fixed gate overdrive (Vg-Vth=lV or 1.5V) was higher in higher S/D extension concentration devices at gate length of less than 0.3pm for nMOS. The extracted effective channel length (using the method proposed by ref.l) of high S/D extension concentration (dose: 6~10'~cm-~) device has shorter by about 45nm than lower SD extension concentration (dose: 2~10'~cm-~) device at Vg-Vth of 1V. This difference increases to about 72nm at Vg-Vth of 1.5V. Higher saturation drain current with higher S/D extension concentration is, therefore, attributed to the suppressed effective channel length modulation. This effect is remarkable in short channel devices because the modulation of effective channel length is less sensitive in longer channel devices. The SP extrinsic resistance in higher S/D extension concentration device has higher value and smaller gate voltage dependence. However, the reduction of effective channel length has major effect on the saturation drain current than the increase of S/D extrinsic resistance. For PMOS, saturation drain current with high S/D extension concentration (dose: 6x 1014cm-2) increased by more than 10% for 0.15pm device than that with low S/D extension concentration (dose: 4~10'~cm-~). This increase is attributed to shorter effective channel length in high S/D extension concentration device. The modulation of effective channel length is smaller in PMOS than in nMOS because the carrier concentration at the extension region may be increased by the impurity diffusion from S/D regions. Propagation delay time (Tpd) of the 0.15pm CMOS inverters was calculated using extracted SPICE parameters. The load capacitance dependence of Tpd was 0.488ps/fF and 0.416pslfF for low (dose: 4~1O'~cm-~) and high (dose: 6x10 14cm-2) S/D extension concentration, respectively, showing that about 15% higher load drivability is obtained in high SD extension concentration device. Hot-carrier reliability We examined the degradation of drain current (AId/Ido) in nMOS under DC stress. The stress gate voltage was chosen for substrate current to be maximum for each stress drain voltage. We defined the hot-carrier life time as the stress time for 10% drain current degradation. We found that the life time was longer with higher S/D extension concentration and that the allowable drain voltage to 10 years DC life time was 1.9Y If we adjust the stress condition as same substrate current (same impact ionization rate), the surface state generation estimated from the increase in charge pumping current is almost the same for high and low S/D extension concentration devices. However, AWdo is lower with higher SD extension concentration. We speculate that the increase in S/D extension resistance caused by the surface state generation is relaxed by screening effect of increased carrier concentration in higher S/D extension concentration device. Summary We have demonstrated that higher-concentration SD extension devices h","PeriodicalId":244069,"journal":{"name":"52nd Annual Device Research Conference","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115926013","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-06-20DOI: 10.1109/DRC.1994.1009407
A. Schuppen, A. Gruhle, U. Erben, H. Kibbel, U. Konig
{"title":"90 GHz f max SiGe-HBTs","authors":"A. Schuppen, A. Gruhle, U. Erben, H. Kibbel, U. Konig","doi":"10.1109/DRC.1994.1009407","DOIUrl":"https://doi.org/10.1109/DRC.1994.1009407","url":null,"abstract":"","PeriodicalId":244069,"journal":{"name":"52nd Annual Device Research Conference","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122714785","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-06-20DOI: 10.1109/DRC.1994.1009453
J. Shealy, M. Mondry, M. Heimbuch, M. Thompson, S. Denbaars
Recently, we demonstrated improved breakdown characteristics in 1 -pm gate length AlInAdGaInAs HEMT utilizing (1) ajunction to modulate the 2-DEG and (2) regrowth of the ohmic contact regions by MOCVD[1]. The remaining challenge has been to demonstrate a high frequency device with improved breakdown characteristics. We present a 0.2pm junction modulated HEMT (JHEMT) with both high frequency performance as well as high breakdown characteristics.
{"title":"0.2/spl mu/m gatelength, non-alloyed AlInAs/GaInAs JHEMTs with extrinsic ft=62 GHz","authors":"J. Shealy, M. Mondry, M. Heimbuch, M. Thompson, S. Denbaars","doi":"10.1109/DRC.1994.1009453","DOIUrl":"https://doi.org/10.1109/DRC.1994.1009453","url":null,"abstract":"Recently, we demonstrated improved breakdown characteristics in 1 -pm gate length AlInAdGaInAs HEMT utilizing (1) ajunction to modulate the 2-DEG and (2) regrowth of the ohmic contact regions by MOCVD[1]. The remaining challenge has been to demonstrate a high frequency device with improved breakdown characteristics. We present a 0.2pm junction modulated HEMT (JHEMT) with both high frequency performance as well as high breakdown characteristics.","PeriodicalId":244069,"journal":{"name":"52nd Annual Device Research Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129938877","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-06-20DOI: 10.1109/DRC.1994.1009445
K. Stevens, M. Kinniburgh, A. Ohtani, M. Hovinen, R. Beresford
The wide bandgap semiconductor AlxGal-p is desired for applications as a solar-blind ultraviolet photodetector for endoatmospheric sensing of jet or rocket plumes and exoatmospheric sensing of solar uv rays reflected from orbiting craft. Recent success in producing epitaxial AlN and GaN on Si [ 11 leads to the present work, which demonstrates at a proof-of-concept level the cointegration of nitride-based photodetectors and Si microelectronics. Development of this concept can lead to unique "solar-blind / solar-sighted'' uv / visible imaging arrays. The materials synthesis is based on an N2 beam excited in an electron cyclotron resonance plasma in a molecular beam epitaxy process. The Si (1 1 1) face provides a commensurate though highly mismatched growth substrate. Microstructure of the AlN and GaN layers is analyzed by x-ray diffractometty and electron microscopy. Two demonstrations are offered to establish the feasibility of the device concepts. In the fist, a GaN photoconductive sensor is produced on a thin A1N buffer layer on Si (1 11). A similar demonstration has previously been made for GaN on sapphire [2]. In the present case, however, the use of Si as the substrate opens up an opportunity to enhance the detector functionality and combine the optoelectronic components with Si-based signal conditioning and read-out circuitry. To integrate nitride- based photodetector architectures with Si electronics, MISFET structures using AN as the gate insulator are demonstrated. Electronic-grade AlN/Si interfaces appear to be a realistic goal.
{"title":"Wide bandgap nitride components for silicon-based integrated ultraviolet photodetection","authors":"K. Stevens, M. Kinniburgh, A. Ohtani, M. Hovinen, R. Beresford","doi":"10.1109/DRC.1994.1009445","DOIUrl":"https://doi.org/10.1109/DRC.1994.1009445","url":null,"abstract":"The wide bandgap semiconductor AlxGal-p is desired for applications as a solar-blind ultraviolet photodetector for endoatmospheric sensing of jet or rocket plumes and exoatmospheric sensing of solar uv rays reflected from orbiting craft. Recent success in producing epitaxial AlN and GaN on Si [ 11 leads to the present work, which demonstrates at a proof-of-concept level the cointegration of nitride-based photodetectors and Si microelectronics. Development of this concept can lead to unique \"solar-blind / solar-sighted'' uv / visible imaging arrays. The materials synthesis is based on an N2 beam excited in an electron cyclotron resonance plasma in a molecular beam epitaxy process. The Si (1 1 1) face provides a commensurate though highly mismatched growth substrate. Microstructure of the AlN and GaN layers is analyzed by x-ray diffractometty and electron microscopy. Two demonstrations are offered to establish the feasibility of the device concepts. In the fist, a GaN photoconductive sensor is produced on a thin A1N buffer layer on Si (1 11). A similar demonstration has previously been made for GaN on sapphire [2]. In the present case, however, the use of Si as the substrate opens up an opportunity to enhance the detector functionality and combine the optoelectronic components with Si-based signal conditioning and read-out circuitry. To integrate nitride- based photodetector architectures with Si electronics, MISFET structures using AN as the gate insulator are demonstrated. Electronic-grade AlN/Si interfaces appear to be a realistic goal.","PeriodicalId":244069,"journal":{"name":"52nd Annual Device Research Conference","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128521143","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-06-20DOI: 10.1109/DRC.1994.1009409
D. Quon, G. Sonek, G. Li
In this paper, we report the study of base current (ib) transport in polyemitter bipolar transistors (PETS) using low frequency noise analysis and suggest that the distribution of the specific carrier transport mechanisms limiting ib can be quantified by acquiring the exponential dependence of fbndamental base current noise (SiEB) on base bias current, This result is important to the resolution of base current mismatching in these devices, which is undesirable for high precision analog circuits. For this investigation, the two carrier transport mechanisms of carrier tunneling through the emitter polysilicon /silicon interface and carrier diffision through the bulk polysilicon [ 11 are considered. To hlly utilize the information contained in the device noise, we have adopted a formulation [2] that makes use of the effects of series resistances and internal emitter feedback to estimate the weighting of the internal noise sources in the device terminal noise SVB. Since rx, and p are critical parameters to this formulation, the device gummel curve was used to extract them and their bias dependence. While the influence of these small signal parameters on SvB dominates at lower biases (Vh<0.7V), the dependence of SiEB on ib can heavily affect SVB at moderate bias (0.7V
{"title":"Characterization of base current transport in polyemitter transistors using low frequency noise analysis","authors":"D. Quon, G. Sonek, G. Li","doi":"10.1109/DRC.1994.1009409","DOIUrl":"https://doi.org/10.1109/DRC.1994.1009409","url":null,"abstract":"In this paper, we report the study of base current (ib) transport in polyemitter bipolar transistors (PETS) using low frequency noise analysis and suggest that the distribution of the specific carrier transport mechanisms limiting ib can be quantified by acquiring the exponential dependence of fbndamental base current noise (SiEB) on base bias current, This result is important to the resolution of base current mismatching in these devices, which is undesirable for high precision analog circuits. For this investigation, the two carrier transport mechanisms of carrier tunneling through the emitter polysilicon /silicon interface and carrier diffision through the bulk polysilicon [ 11 are considered. To hlly utilize the information contained in the device noise, we have adopted a formulation [2] that makes use of the effects of series resistances and internal emitter feedback to estimate the weighting of the internal noise sources in the device terminal noise SVB. Since rx, and p are critical parameters to this formulation, the device gummel curve was used to extract them and their bias dependence. While the influence of these small signal parameters on SvB dominates at lower biases (Vh<0.7V), the dependence of SiEB on ib can heavily affect SVB at moderate bias (0.7V<Vk<O.8V), showing SVB either increasing, unchanging or decreasing with increasing collector bias current I,. It should be noted that the weighting of SiEB at the base terminal is much higher than for other noise sources, which allows for the acquisition of it by using the SiEB and thermal terms of the SvB formulation alone. The measured white noise portion of SV~, which is independent of the l/f noise, is found to correlate well with theoretically calculated values over more than two decades of current. For the l/f portion of S\"B, we assume here that the l/f component of SZB is characterized by only two parameters, Kf and af, which represent the magnitude and ib bias dependence of SEB, respectively. Based on theoretical l/f noise models, af values of 1 or 2 are indicative of the dominant diffision or tunneling current occurring at the polysilicodsilicon interface. We report that these values are confirmed also over more than two decades of current in transistors having either an epitaxially realigned interface or a continuous interfacial oxide, as indicated by their series emitter resistance re. However, assuming af values of 1 or 2 for arbitrary transistors can lead to large discrepancies between the actual and calculated noise. Transistors having ' ifitermediate values of rc exhibited lafa, implying that their ibs embody a more balanced formulation of diffision and tunneling [3]. A more detailed discussion of the measurement and physical interpretation of these noise characteristics will be presented at the conference.","PeriodicalId":244069,"journal":{"name":"52nd Annual Device Research Conference","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125000875","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-06-20DOI: 10.1109/DRC.1994.1009424
J. Ellis-Monaghan, R. Hulfachor, K.W. Kim, M. Littlejohn
The simulation model employed in this study consists of an advanced ensemble Monte Carlo method, that incorporates two conduction energy bands from pseudopotential calculations, coupled with an interface-state genemtion model. It has been demonstrated that this coupled treatment can calculate interface-state generation with accuracy and a good overall agreement has been achieved between the simulated results and measured data in longchannel (l-pm) devices [ I]. Using the same methodology, we explored the implications of power-supply voltages driven by two widely used device-scaling approaches: constant field scaling [2] 'and a more generalized scaling [3]. Throughout this study, the devices are stressed for 120 seconds at Vds=2Vgs. For constant field scaling, we found that the simulated electron injection rates decreased from 6.4x102'/cm2sec at the location of peak electron injection for a 0.33-pin device with Vd,=3.3 V, to 2.4x10"/cm2sec for a 0.12-pin device with Vd,=1.2 V. This corresponds to a predicted peak interface-state density of 7x10"/cm2eV and 4.3x10"/cm2eV for the 0.33-pm and 0.12-pm device, respectively. This decrease seems to be caused mainly by the reduced lateral field, (The "constant" lateral field methodology reduces the peak electric field from 170 kV/cm to 150 kV/cm for these short-channel devices.) On the other hand, the peak average electron energy is significantly reduced from 2.2 eV for the 0.33-pm device to 1.3 eV for the 0.12-pin device. When the generalized scaling scheme was applied, the simulated electron injection and interface-state generation rates increased considerably, from an interface-state generation density of 7x10"/cm2eV for the same 0.33-pm device with Vh=3.3 V, to 9.2x10"/cm2eV for a 0.12-pm device with Vd,=2.25 V. The corresponding peak electron injection rate for the 0.12-pm device was 1.1x1OZ2/cm2sec. For the generalized scaling scheme, the peak lateral field increased from 170 kV/cm to 240 kV/cm as the devices scaled down. The effect of power-supplyvoltage reduction was clearly seen in the average electron energy. The average energy at the location of pe'ak electron injection was significantly reduced, from 2.2 eV for the 0.33-pm device to 1.5 eV for the 0.12-pm device. Thus, the electron energy distribution appears to have strongly non-linear characteristics. While the average energy scales down with the power-supply voltage, the electrons in the high-energy tail of the distribution ciui bc enhanced (i.e., a longer tail) by the large peak electric field. These results for the two scaling approaches demonstrate the importance of hot electron degradation in deep-submicron MOSFETS operating below the 3 V power supply level.
{"title":"Scaling studies of hot electron injection and interface-state generation in deep-submicron silicon mosfets: a monte carlo analysis","authors":"J. Ellis-Monaghan, R. Hulfachor, K.W. Kim, M. Littlejohn","doi":"10.1109/DRC.1994.1009424","DOIUrl":"https://doi.org/10.1109/DRC.1994.1009424","url":null,"abstract":"The simulation model employed in this study consists of an advanced ensemble Monte Carlo method, that incorporates two conduction energy bands from pseudopotential calculations, coupled with an interface-state genemtion model. It has been demonstrated that this coupled treatment can calculate interface-state generation with accuracy and a good overall agreement has been achieved between the simulated results and measured data in longchannel (l-pm) devices [ I]. Using the same methodology, we explored the implications of power-supply voltages driven by two widely used device-scaling approaches: constant field scaling [2] 'and a more generalized scaling [3]. Throughout this study, the devices are stressed for 120 seconds at Vds=2Vgs. For constant field scaling, we found that the simulated electron injection rates decreased from 6.4x102'/cm2sec at the location of peak electron injection for a 0.33-pin device with Vd,=3.3 V, to 2.4x10\"/cm2sec for a 0.12-pin device with Vd,=1.2 V. This corresponds to a predicted peak interface-state density of 7x10\"/cm2eV and 4.3x10\"/cm2eV for the 0.33-pm and 0.12-pm device, respectively. This decrease seems to be caused mainly by the reduced lateral field, (The \"constant\" lateral field methodology reduces the peak electric field from 170 kV/cm to 150 kV/cm for these short-channel devices.) On the other hand, the peak average electron energy is significantly reduced from 2.2 eV for the 0.33-pm device to 1.3 eV for the 0.12-pin device. When the generalized scaling scheme was applied, the simulated electron injection and interface-state generation rates increased considerably, from an interface-state generation density of 7x10\"/cm2eV for the same 0.33-pm device with Vh=3.3 V, to 9.2x10\"/cm2eV for a 0.12-pm device with Vd,=2.25 V. The corresponding peak electron injection rate for the 0.12-pm device was 1.1x1OZ2/cm2sec. For the generalized scaling scheme, the peak lateral field increased from 170 kV/cm to 240 kV/cm as the devices scaled down. The effect of power-supplyvoltage reduction was clearly seen in the average electron energy. The average energy at the location of pe'ak electron injection was significantly reduced, from 2.2 eV for the 0.33-pm device to 1.5 eV for the 0.12-pm device. Thus, the electron energy distribution appears to have strongly non-linear characteristics. While the average energy scales down with the power-supply voltage, the electrons in the high-energy tail of the distribution ciui bc enhanced (i.e., a longer tail) by the large peak electric field. These results for the two scaling approaches demonstrate the importance of hot electron degradation in deep-submicron MOSFETS operating below the 3 V power supply level.","PeriodicalId":244069,"journal":{"name":"52nd Annual Device Research Conference","volume":"1 3","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120926851","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-06-20DOI: 10.1109/DRC.1994.1009425
S. Takagi, A. Toriumi
{"title":"The importance of inversion-layer capacitance in Si MOSFETs in the ultra-thin gate oxide regime","authors":"S. Takagi, A. Toriumi","doi":"10.1109/DRC.1994.1009425","DOIUrl":"https://doi.org/10.1109/DRC.1994.1009425","url":null,"abstract":"","PeriodicalId":244069,"journal":{"name":"52nd Annual Device Research Conference","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116552353","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-06-20DOI: 10.1109/DRC.1994.1009421
F. Cartier, D. J. DiMaria, D. Buchanan, J. Stathis, W. Abadeer, R. Vollertsen
I Jot-electrons in gate oxides can release process-induced hydrogenic species from the Si02 network and from its interfaces. Additional oxide/intcrface degradation will occur because of subsequent chemical reactions. Atomic hydrogen, IP, is known to cause such damage at device operation temperatures.' To quantify the I In chemistry and to study its erects on device reliability, we have measured the Si-orientation dcpcndcncc, the oxidc thickness dependence and the temperature dependence of ZP-induced degradation using an atomic hydrogen sourc'c2 Thcrmal SiO, films on Si Were exposed to I P and the resulting degradation was characterized by current/voltagc, by high/low-rrequency capacitance-voltage and by electron paramagnetic resonancc measurement T . +
{"title":"Degradation of thin SiO/sub 2/ gate oxides by atomic hydrogen","authors":"F. Cartier, D. J. DiMaria, D. Buchanan, J. Stathis, W. Abadeer, R. Vollertsen","doi":"10.1109/DRC.1994.1009421","DOIUrl":"https://doi.org/10.1109/DRC.1994.1009421","url":null,"abstract":"I Jot-electrons in gate oxides can release process-induced hydrogenic species from the Si02 network and from its interfaces. Additional oxide/intcrface degradation will occur because of subsequent chemical reactions. Atomic hydrogen, IP, is known to cause such damage at device operation temperatures.' To quantify the I In chemistry and to study its erects on device reliability, we have measured the Si-orientation dcpcndcncc, the oxidc thickness dependence and the temperature dependence of ZP-induced degradation using an atomic hydrogen sourc'c2 Thcrmal SiO, films on Si Were exposed to I P and the resulting degradation was characterized by current/voltagc, by high/low-rrequency capacitance-voltage and by electron paramagnetic resonancc measurement T . +","PeriodicalId":244069,"journal":{"name":"52nd Annual Device Research Conference","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132557447","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-06-20DOI: 10.1109/DRC.1994.1009448
T. Ohshima, N. Yamamoto, T. Ichioka, T. Kimura, Y. Sano
Then W-Al was anisotropically etched by the electron cyclotron resonance (ECR) plasma using the Al pattern as a mask, where the difference between the resist spacing and the gate length was less than 0.02pm. A standard deviation of 0.17pm W-AI gate pattern obtained was as small as 0.019pm (9.5%) over a 3-inch wafer. After the gate formation, ion implantations of Si and C were performed to form n+-region and buried p-region which were self-aligned to the gate. This structure successfilly suppressed the short channel effect without sacrificing its high speed performance, namely, without increasing the parasitic capacitance. Fabricated 0.17pm-gate GaAs MESFETs have shown the averaged maximum transconductance of 622mmS/mm with the standard deviation of lOmmS/mm (1.6%) at the drain voltage of 1V. The uniformity of the threshold voltage was also good, and the standard deviation was 28mV over a 3-inch wafer. The DCFL (Direct-Coupled FET Logic) inverter implemented by this device has shown a propagation delay of 10.4pdgate with a power dissipation of 2.34mW/gate at the supply voltage of 2V as averaged values over a 3-inch wafer. These standard deviations were 0.28ps/gate (2.7%) and 0.053mW/gate (2.3%), respectively. As the highest value, we have observed the propagation delay of 7.6pdgate at a supply voltage of 1OV. Using this device we have fabricated 8: 1 multiplexer and 1 :8 demultiplexer, and obtained a stable operation at lOGb/s at a power dissipation as low as 1.5W and 2.0W, respectively. The demultiplexer has operated even at 14Gb/s, which is one of the best results ever reported. A yield of these IC's was over 50%, which was due to the high uniformity in the characteristics of the MESFETs. Finally, we have confirmed that the fabrication process of 0.17pm-gate GaAs MESFET based on the phase-shifting mask technology is promising for the ultra high speed digital IC application. Next, Al was evaporated and lifted-off
{"title":"Application of phase-shifting mask technology to 0.17/spl mu/m-gate GaAs MESFET for ultra high speed IC's","authors":"T. Ohshima, N. Yamamoto, T. Ichioka, T. Kimura, Y. Sano","doi":"10.1109/DRC.1994.1009448","DOIUrl":"https://doi.org/10.1109/DRC.1994.1009448","url":null,"abstract":"Then W-Al was anisotropically etched by the electron cyclotron resonance (ECR) plasma using the Al pattern as a mask, where the difference between the resist spacing and the gate length was less than 0.02pm. A standard deviation of 0.17pm W-AI gate pattern obtained was as small as 0.019pm (9.5%) over a 3-inch wafer. After the gate formation, ion implantations of Si and C were performed to form n+-region and buried p-region which were self-aligned to the gate. This structure successfilly suppressed the short channel effect without sacrificing its high speed performance, namely, without increasing the parasitic capacitance. Fabricated 0.17pm-gate GaAs MESFETs have shown the averaged maximum transconductance of 622mmS/mm with the standard deviation of lOmmS/mm (1.6%) at the drain voltage of 1V. The uniformity of the threshold voltage was also good, and the standard deviation was 28mV over a 3-inch wafer. The DCFL (Direct-Coupled FET Logic) inverter implemented by this device has shown a propagation delay of 10.4pdgate with a power dissipation of 2.34mW/gate at the supply voltage of 2V as averaged values over a 3-inch wafer. These standard deviations were 0.28ps/gate (2.7%) and 0.053mW/gate (2.3%), respectively. As the highest value, we have observed the propagation delay of 7.6pdgate at a supply voltage of 1OV. Using this device we have fabricated 8: 1 multiplexer and 1 :8 demultiplexer, and obtained a stable operation at lOGb/s at a power dissipation as low as 1.5W and 2.0W, respectively. The demultiplexer has operated even at 14Gb/s, which is one of the best results ever reported. A yield of these IC's was over 50%, which was due to the high uniformity in the characteristics of the MESFETs. Finally, we have confirmed that the fabrication process of 0.17pm-gate GaAs MESFET based on the phase-shifting mask technology is promising for the ultra high speed digital IC application. Next, Al was evaporated and lifted-off","PeriodicalId":244069,"journal":{"name":"52nd Annual Device Research Conference","volume":"103 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132746047","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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