Pub Date : 2009-07-12DOI: 10.1109/RME.2009.5201364
O. Brousse, G. Sassatelli, F. Grize
This paper presents a unified design flow that aims at accelerating parallelizable data-intensive applications in the context of ubiquitous computing. This contribution relies on the JubiTool: a set of integrated tools (JubiSplitter, JubiCompiler), allowing respectively to extract and compile parallelizable parts of applications described in a Java extended language called Jubi. By appending hardware directives to a software agent description, the inherent flexibility of software is combined with the runtime performance of a hardware execution. In the case of typical Perplexus applications such as a biologically plausible neural network simulator, this contribution takes profit of the intrinsic property of the Perplexus Ubichip in terms of parallelism resulting in an expected speedup of one order of magnitude. Finally, we show that this original flow allowing HW acceleration can be modified to support other types of distributed platforms.
{"title":"The Jubi approach: a tool set for hardware acceleration in sensor network applications field","authors":"O. Brousse, G. Sassatelli, F. Grize","doi":"10.1109/RME.2009.5201364","DOIUrl":"https://doi.org/10.1109/RME.2009.5201364","url":null,"abstract":"This paper presents a unified design flow that aims at accelerating parallelizable data-intensive applications in the context of ubiquitous computing. This contribution relies on the JubiTool: a set of integrated tools (JubiSplitter, JubiCompiler), allowing respectively to extract and compile parallelizable parts of applications described in a Java extended language called Jubi. By appending hardware directives to a software agent description, the inherent flexibility of software is combined with the runtime performance of a hardware execution. In the case of typical Perplexus applications such as a biologically plausible neural network simulator, this contribution takes profit of the intrinsic property of the Perplexus Ubichip in terms of parallelism resulting in an expected speedup of one order of magnitude. Finally, we show that this original flow allowing HW acceleration can be modified to support other types of distributed platforms.","PeriodicalId":245992,"journal":{"name":"2009 Ph.D. Research in Microelectronics and Electronics","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130896373","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-12DOI: 10.1109/RME.2009.5201301
P. Balasubramanian, D. A. Edwards
A novel heterogeneously encoded dual-bit self-timed adder design is presented in this paper. Heterogeneous encoding refers to a combination of at least two different delay-insensitive encoding schemes, adopted for the inputs and outputs. The primary motivation being that higher order 1-of-n encoding protocols facilitate reduction in terms of the circuit switching power dissipation compared to the basic dual-rail (1-of-2, which is the simplest 1-of-n code) encoding scheme. Here, n specifies the number of physical lines. The number of transitions gets reduced by O(k) over a dual-rail code, with k being the number of primary inputs and equals log2n. The design of a dual-bit adder is considered to illustrate the advantage of the heterogeneous encoding scheme. The proposed adder design satisfies Seitz's weak-indication timing constraints. In comparison with dual-bit adders realized using other approaches, employing dual-rail encoding or heterogeneous encoding, the proposed design is found to be efficient in terms of delay, power consumption and area parameters.
{"title":"Heterogeneously encoded dual-bit self-timed adder","authors":"P. Balasubramanian, D. A. Edwards","doi":"10.1109/RME.2009.5201301","DOIUrl":"https://doi.org/10.1109/RME.2009.5201301","url":null,"abstract":"A novel heterogeneously encoded dual-bit self-timed adder design is presented in this paper. Heterogeneous encoding refers to a combination of at least two different delay-insensitive encoding schemes, adopted for the inputs and outputs. The primary motivation being that higher order 1-of-n encoding protocols facilitate reduction in terms of the circuit switching power dissipation compared to the basic dual-rail (1-of-2, which is the simplest 1-of-n code) encoding scheme. Here, n specifies the number of physical lines. The number of transitions gets reduced by O(k) over a dual-rail code, with k being the number of primary inputs and equals log2n. The design of a dual-bit adder is considered to illustrate the advantage of the heterogeneous encoding scheme. The proposed adder design satisfies Seitz's weak-indication timing constraints. In comparison with dual-bit adders realized using other approaches, employing dual-rail encoding or heterogeneous encoding, the proposed design is found to be efficient in terms of delay, power consumption and area parameters.","PeriodicalId":245992,"journal":{"name":"2009 Ph.D. Research in Microelectronics and Electronics","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121938480","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-12DOI: 10.1109/RME.2009.5201370
J. Vial, A. Virazel
With the technology entering the nano dimension, manufacturing processes are less and less reliable, thus drastically impacting the yield. To address this problem during SoC development, memory cores are built with hardware redundancies. On the other hand, logic cores embedded in SoC usually do not have such redundancy capabilities. Therefore, manufacturing defects affecting these cores decrease the yield of the entire SoC. Consequently, meaningful techniques for SoC yield improvement must also consider logic cores. In this paper, we propose and investigate the usage of TMR architectures for logic cores to increase the overall SoC yield. In order to analyze the TMR effectiveness, we resort to two defects distribution models, the Poisson and negative binomial distributions, that are also compared. Results obtained on SoC examples demonstrate the interest of using TMR architectures for SoC yield enhancement purpose.
{"title":"Yes, we can improve SoC yield","authors":"J. Vial, A. Virazel","doi":"10.1109/RME.2009.5201370","DOIUrl":"https://doi.org/10.1109/RME.2009.5201370","url":null,"abstract":"With the technology entering the nano dimension, manufacturing processes are less and less reliable, thus drastically impacting the yield. To address this problem during SoC development, memory cores are built with hardware redundancies. On the other hand, logic cores embedded in SoC usually do not have such redundancy capabilities. Therefore, manufacturing defects affecting these cores decrease the yield of the entire SoC. Consequently, meaningful techniques for SoC yield improvement must also consider logic cores. In this paper, we propose and investigate the usage of TMR architectures for logic cores to increase the overall SoC yield. In order to analyze the TMR effectiveness, we resort to two defects distribution models, the Poisson and negative binomial distributions, that are also compared. Results obtained on SoC examples demonstrate the interest of using TMR architectures for SoC yield enhancement purpose.","PeriodicalId":245992,"journal":{"name":"2009 Ph.D. Research in Microelectronics and Electronics","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116641067","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-12DOI: 10.1109/RME.2009.5201332
M. Kaniewska
In the paper the possibilities of using instantaneous complex frequency (ICF) for analyzing and modifying simple sounds are discussed. Before estimating ICF, a bifactorization of a signal is applied in order to obtain two factors: one fully characterized by its envelope and the other with positive instantaneous frequency.
{"title":"On the use of instantaneous complex frequency for analysis and modification of simple sounds","authors":"M. Kaniewska","doi":"10.1109/RME.2009.5201332","DOIUrl":"https://doi.org/10.1109/RME.2009.5201332","url":null,"abstract":"In the paper the possibilities of using instantaneous complex frequency (ICF) for analyzing and modifying simple sounds are discussed. Before estimating ICF, a bifactorization of a signal is applied in order to obtain two factors: one fully characterized by its envelope and the other with positive instantaneous frequency.","PeriodicalId":245992,"journal":{"name":"2009 Ph.D. Research in Microelectronics and Electronics","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131342166","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-12DOI: 10.1109/RME.2009.5201326
M. Dei, N. Nizza, G. M. Lazzerini, P. Bruschi, M. Piotto
An analog, Gilbert-like CMOS multiplier, based on a novel linear current divider, is described. The divider uses a cascade of two differential pairs to produce a linear dependence between the tail current and the two output currents. A numerical algorithm has been implemented to find the optimum sizing of the active devices in order to compensate for the deviation from the ideal MOSFET square law. The results of low frequency measurements performed on a prototype, designed with CMOS devices from the STMicroelectronic process BCD6s, are shown.
{"title":"A four quadrant analog multiplier based on a novel CMOS linear current divider","authors":"M. Dei, N. Nizza, G. M. Lazzerini, P. Bruschi, M. Piotto","doi":"10.1109/RME.2009.5201326","DOIUrl":"https://doi.org/10.1109/RME.2009.5201326","url":null,"abstract":"An analog, Gilbert-like CMOS multiplier, based on a novel linear current divider, is described. The divider uses a cascade of two differential pairs to produce a linear dependence between the tail current and the two output currents. A numerical algorithm has been implemented to find the optimum sizing of the active devices in order to compensate for the deviation from the ideal MOSFET square law. The results of low frequency measurements performed on a prototype, designed with CMOS devices from the STMicroelectronic process BCD6s, are shown.","PeriodicalId":245992,"journal":{"name":"2009 Ph.D. Research in Microelectronics and Electronics","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128172496","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-12DOI: 10.1109/RME.2009.5201340
M. Marx, R. Kokozinski, H. Muller
ACCURATE localization Systems, based on the measurement of the time of flight of a signal between radio devices, also known as Real Time Location Systems (RTLS) are becoming increasingly important especially in indoor applications. Due to severe multi path conditions, the largest problem for those RTLS systems is to detect the time of arrival of signals traveling over the direct line of sight path. We present issues of a new High Resolution Delay Locked Loop (HRDLL) architecture- that allows an efficient hardware implementation of a high resolution method for multi path mitigation, and demonstrate first results.
{"title":"High Resolution Delay Locked Loop for time synchronization with multi path mitigation","authors":"M. Marx, R. Kokozinski, H. Muller","doi":"10.1109/RME.2009.5201340","DOIUrl":"https://doi.org/10.1109/RME.2009.5201340","url":null,"abstract":"ACCURATE localization Systems, based on the measurement of the time of flight of a signal between radio devices, also known as Real Time Location Systems (RTLS) are becoming increasingly important especially in indoor applications. Due to severe multi path conditions, the largest problem for those RTLS systems is to detect the time of arrival of signals traveling over the direct line of sight path. We present issues of a new High Resolution Delay Locked Loop (HRDLL) architecture- that allows an efficient hardware implementation of a high resolution method for multi path mitigation, and demonstrate first results.","PeriodicalId":245992,"journal":{"name":"2009 Ph.D. Research in Microelectronics and Electronics","volume":"74 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132086155","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-12DOI: 10.1109/RME.2009.5201344
M. Meola, S. Carrato, G. Bernacchia, E. Bodano
In this paper a new large-signal discrete time model for dc-dc converters is derived. The model is meant to overcome the lack of large-signal dc-dc converter models which, firstly, are able to accurately predict converter behavior in different operating modes and, secondly, can be implemented both in Matlab/SIMULINK and HDL language. The model is well suited to perform system level simulation of digitally controlled SMPS using synthesis tools targeted to FPGA and ASIC implementation and, therefore, avoiding time consuming mixedsignal simulations from the first stages of the design.
{"title":"Discrete time large-signal model of dc-dc converters for system level simulation of digitally controlled SMPS","authors":"M. Meola, S. Carrato, G. Bernacchia, E. Bodano","doi":"10.1109/RME.2009.5201344","DOIUrl":"https://doi.org/10.1109/RME.2009.5201344","url":null,"abstract":"In this paper a new large-signal discrete time model for dc-dc converters is derived. The model is meant to overcome the lack of large-signal dc-dc converter models which, firstly, are able to accurately predict converter behavior in different operating modes and, secondly, can be implemented both in Matlab/SIMULINK and HDL language. The model is well suited to perform system level simulation of digitally controlled SMPS using synthesis tools targeted to FPGA and ASIC implementation and, therefore, avoiding time consuming mixedsignal simulations from the first stages of the design.","PeriodicalId":245992,"journal":{"name":"2009 Ph.D. Research in Microelectronics and Electronics","volume":"188 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133380095","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-12DOI: 10.1109/RME.2009.5201358
E. Volpi, L. Fanucci
The design and laboratory tests of a high voltage driver with programmable output current are presented. The proposed solution is designed to work in the range of low frequencies (PWM output current up to 100 KHz) and with output currents between 50 mA and 130 mA. The presented topology exploits a feedback loop that allows fixing the output current to the desired value with high precision not easy to achieve with high voltage devices. Measurements performed on a prototype, designed and fabricated in a 0.35 μm Bipolar-CMOS-DMOS technology prove the effectiveness of the proposed solution.
{"title":"Design of a high voltage high side driver with programmable output current","authors":"E. Volpi, L. Fanucci","doi":"10.1109/RME.2009.5201358","DOIUrl":"https://doi.org/10.1109/RME.2009.5201358","url":null,"abstract":"The design and laboratory tests of a high voltage driver with programmable output current are presented. The proposed solution is designed to work in the range of low frequencies (PWM output current up to 100 KHz) and with output currents between 50 mA and 130 mA. The presented topology exploits a feedback loop that allows fixing the output current to the desired value with high precision not easy to achieve with high voltage devices. Measurements performed on a prototype, designed and fabricated in a 0.35 μm Bipolar-CMOS-DMOS technology prove the effectiveness of the proposed solution.","PeriodicalId":245992,"journal":{"name":"2009 Ph.D. Research in Microelectronics and Electronics","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117326050","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-12DOI: 10.1109/RME.2009.5201292
F. Amoroso, A. Pugliese, G. Cappuccino
The large-signal performances of switched-capacitor (SC) circuits employing two-stage operational amplifiers (opamps) with current-buffer Miller compensation are analyzed. Well-defined rules to fix carefully the bias currents of the two op-amp stages are proposed in order to optimize the amplifier settling behavior. Simulation results related to op-amps designed in a commercial 0.35 µm CMOS technology show the usefulness of the proposed design guidelines.
{"title":"Large-signal settling optimization of SC circuits using two-stage amplifiers with current-buffer miller compensation","authors":"F. Amoroso, A. Pugliese, G. Cappuccino","doi":"10.1109/RME.2009.5201292","DOIUrl":"https://doi.org/10.1109/RME.2009.5201292","url":null,"abstract":"The large-signal performances of switched-capacitor (SC) circuits employing two-stage operational amplifiers (opamps) with current-buffer Miller compensation are analyzed. Well-defined rules to fix carefully the bias currents of the two op-amp stages are proposed in order to optimize the amplifier settling behavior. Simulation results related to op-amps designed in a commercial 0.35 µm CMOS technology show the usefulness of the proposed design guidelines.","PeriodicalId":245992,"journal":{"name":"2009 Ph.D. Research in Microelectronics and Electronics","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115780512","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-12DOI: 10.1109/RME.2009.5201319
A. Rodríguez-Pérez, M. Delgado-Restituto, F. Medeiro
This paper presents a 12-bit low-voltage low-power Analog-to-Digital Converter (ADC). The design employs Switched Capacitor (SC) techniques and implements a Successive Approximation (SA) algorithm. The ADC is highly reconfigurable, with digitally selectable resolution and input signal amplitude, and achieves 11.4-bit of effective resolution at 500kHz clock frequency, with a power consumption below 3µW from a 1V voltage supply.
{"title":"A low-voltage low-power successive approximation reconfigurable ADC based on SC techniques","authors":"A. Rodríguez-Pérez, M. Delgado-Restituto, F. Medeiro","doi":"10.1109/RME.2009.5201319","DOIUrl":"https://doi.org/10.1109/RME.2009.5201319","url":null,"abstract":"This paper presents a 12-bit low-voltage low-power Analog-to-Digital Converter (ADC). The design employs Switched Capacitor (SC) techniques and implements a Successive Approximation (SA) algorithm. The ADC is highly reconfigurable, with digitally selectable resolution and input signal amplitude, and achieves 11.4-bit of effective resolution at 500kHz clock frequency, with a power consumption below 3µW from a 1V voltage supply.","PeriodicalId":245992,"journal":{"name":"2009 Ph.D. Research in Microelectronics and Electronics","volume":"65 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124237359","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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