Pub Date : 2009-07-12DOI: 10.1109/RME.2009.5201342
Meththa Samaranayake, Helen Ji, J. Ainscough
This paper presents the idea of using a combination of force-directed graph drawing algorithms for the basis of a module placement tool. Even with the increase of usage of modules within designs, the industry holds a gap for module placement tools. Direct experimentation has shown that comparable placement topologies were achieved by the forcedirected algorithms to that of current academic placement tools.
{"title":"Development of a force directed module placement tool","authors":"Meththa Samaranayake, Helen Ji, J. Ainscough","doi":"10.1109/RME.2009.5201342","DOIUrl":"https://doi.org/10.1109/RME.2009.5201342","url":null,"abstract":"This paper presents the idea of using a combination of force-directed graph drawing algorithms for the basis of a module placement tool. Even with the increase of usage of modules within designs, the industry holds a gap for module placement tools. Direct experimentation has shown that comparable placement topologies were achieved by the forcedirected algorithms to that of current academic placement tools.","PeriodicalId":245992,"journal":{"name":"2009 Ph.D. Research in Microelectronics and Electronics","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128953592","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-12DOI: 10.1109/RME.2009.5201327
M. Barragán, D. Vázquez, A. Rueda
This paper presents practical implementations of test cores for analog and mixed-signal BIST. A sinewave generator for test stimulus generation, and a periodical signal characterization system for response evaluation are discussed. Integrated prototypes and experimental results are provided, and a prototype of a network/spectrum analyzer featuring both test cores has been developed and tested in the lab.
{"title":"Practical test cores for the on-chip generation and evaluation of analog test signals: Application to a network/spectrum analyzer for analog BIST","authors":"M. Barragán, D. Vázquez, A. Rueda","doi":"10.1109/RME.2009.5201327","DOIUrl":"https://doi.org/10.1109/RME.2009.5201327","url":null,"abstract":"This paper presents practical implementations of test cores for analog and mixed-signal BIST. A sinewave generator for test stimulus generation, and a periodical signal characterization system for response evaluation are discussed. Integrated prototypes and experimental results are provided, and a prototype of a network/spectrum analyzer featuring both test cores has been developed and tested in the lab.","PeriodicalId":245992,"journal":{"name":"2009 Ph.D. Research in Microelectronics and Electronics","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129105743","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-12DOI: 10.1109/RME.2009.5201376
S. Braga, A. Cabrini, G. Torelli
Phase change memories (PCMs) are promising candidates for multilevel storage, thanks to the wide programming window. The multilevel approach requires good control of the programmed cell resistance. For any multilevel programming strategy, the RESET operation plays a key role for the accuracy of the intermediate programmed resistance levels. In this paper, we analyze the impact of the applied RESET pulse amplitude and the fabrication process spreads on the resistance distribution obtained after the RESET operation. To this end, we propose a model to estimate the impact of device parameter spreads on the amorphous cap thickness and, hence, on the cell resistance obtained after a RESET operation. The proposed model is verified by means of experimental characterization on a PCM cells array.
{"title":"Experimental analysis of RESET resistance distribution in phase change memories","authors":"S. Braga, A. Cabrini, G. Torelli","doi":"10.1109/RME.2009.5201376","DOIUrl":"https://doi.org/10.1109/RME.2009.5201376","url":null,"abstract":"Phase change memories (PCMs) are promising candidates for multilevel storage, thanks to the wide programming window. The multilevel approach requires good control of the programmed cell resistance. For any multilevel programming strategy, the RESET operation plays a key role for the accuracy of the intermediate programmed resistance levels. In this paper, we analyze the impact of the applied RESET pulse amplitude and the fabrication process spreads on the resistance distribution obtained after the RESET operation. To this end, we propose a model to estimate the impact of device parameter spreads on the amorphous cap thickness and, hence, on the cell resistance obtained after a RESET operation. The proposed model is verified by means of experimental characterization on a PCM cells array.","PeriodicalId":245992,"journal":{"name":"2009 Ph.D. Research in Microelectronics and Electronics","volume":"46 4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127991903","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-12DOI: 10.1109/RME.2009.5201354
Liang Zheng, H. Qin, S. Daniels
This paper present a preparative technique for spiral thin-film transformer with ferrite magnetic core. RF magnetron sputtering is used to prepare ferrite thin film on SiO2 layer. Compatible problems of thin film with IC technology are observed by SEM. The problems are resolved through sputtering parameters modification and heating treatment addition. S-parameters are measured at 10MHz-20GHz. The result shows that The experience result shows, magnetic core thin-film transformer with 15:15 ratio-turn can obtain the maximal transmission efficiency 80.9% at 10MHz- 20GHz, and the air core transformer can obtain the maximal transmission efficiency 55.4% at same frequency range. Ferrite thin film can improve the transmission efficiency evidently.
{"title":"A preparative technique for spiral thin-film transformer at GHz frequency band","authors":"Liang Zheng, H. Qin, S. Daniels","doi":"10.1109/RME.2009.5201354","DOIUrl":"https://doi.org/10.1109/RME.2009.5201354","url":null,"abstract":"This paper present a preparative technique for spiral thin-film transformer with ferrite magnetic core. RF magnetron sputtering is used to prepare ferrite thin film on SiO2 layer. Compatible problems of thin film with IC technology are observed by SEM. The problems are resolved through sputtering parameters modification and heating treatment addition. S-parameters are measured at 10MHz-20GHz. The result shows that The experience result shows, magnetic core thin-film transformer with 15:15 ratio-turn can obtain the maximal transmission efficiency 80.9% at 10MHz- 20GHz, and the air core transformer can obtain the maximal transmission efficiency 55.4% at same frequency range. Ferrite thin film can improve the transmission efficiency evidently.","PeriodicalId":245992,"journal":{"name":"2009 Ph.D. Research in Microelectronics and Electronics","volume":"80 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126862374","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-12DOI: 10.1109/RME.2009.5201357
M. Riccio, A. Irace, G. Breglio
In this paper we show how the Lock-In Thermography (LIT) technique is a valid choice to obtain information on the pre-breakdown leakage current distribution on power diodes. To do this we describe the LIT principle and our in house made experimental set-up. We finally show interesting experimental results on power Schottky diodes.
{"title":"Lock-in thermography for the localization of prebreakdown leakage current on power diodes","authors":"M. Riccio, A. Irace, G. Breglio","doi":"10.1109/RME.2009.5201357","DOIUrl":"https://doi.org/10.1109/RME.2009.5201357","url":null,"abstract":"In this paper we show how the Lock-In Thermography (LIT) technique is a valid choice to obtain information on the pre-breakdown leakage current distribution on power diodes. To do this we describe the LIT principle and our in house made experimental set-up. We finally show interesting experimental results on power Schottky diodes.","PeriodicalId":245992,"journal":{"name":"2009 Ph.D. Research in Microelectronics and Electronics","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121661437","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-12DOI: 10.1109/RME.2009.5201318
N. B. Hassine, D. Mercier, P. Renaux
This work deals with BAW SMR reliability at high power levels. Experimental methods easy to set up in common RF laboratories are presented and validated. Experimental results concerning frequency shifts versus the dissipated power and the harmonics generation are reported. The main origins of these effects are discussed physically and conclusions in light of the obtained results about the characterization method and the device reliability are drawn.
{"title":"Solidly mounted resonators under high power study for reliability assessment","authors":"N. B. Hassine, D. Mercier, P. Renaux","doi":"10.1109/RME.2009.5201318","DOIUrl":"https://doi.org/10.1109/RME.2009.5201318","url":null,"abstract":"This work deals with BAW SMR reliability at high power levels. Experimental methods easy to set up in common RF laboratories are presented and validated. Experimental results concerning frequency shifts versus the dissipated power and the harmonics generation are reported. The main origins of these effects are discussed physically and conclusions in light of the obtained results about the characterization method and the device reliability are drawn.","PeriodicalId":245992,"journal":{"name":"2009 Ph.D. Research in Microelectronics and Electronics","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123886565","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-12DOI: 10.1109/RME.2009.5201294
A. Neyer, B. Thiel, S. Heinen
A stereo FM-radio transmitter with Radio Data System (RDS) support based on an all-digital PLL is presented. It has been designed as a fully integrated single-chip transmitter in a 90-nm CMOS technology to be compatible with digital deepsubmicrometer processes. Target application of the proposed system is the cointegration with baseband processors and transmitters for mobile communication systems. Nowadays mobile phones have a lot of multimedia capabilities e. g. an integrated MP3 player. The proposed transmitter enables a mobile device to stream audio data to a FM receiver which is popular and existing in most households world wide. RDS support allows to send additional information e. g. title and artist of a song. As mobile applications are the main target for the transmitter great attention has been attached to saving power and area. Therefore, the presented transmitter works on a 1V supply voltage and is aimed for using a 32.768 kHz reference crystal oscillator instead of the commonly used 26MHz reference oscillator while still providing wideband frequency modulation capability.
{"title":"A FM-radio transmitter concept based on an all-digital PLL","authors":"A. Neyer, B. Thiel, S. Heinen","doi":"10.1109/RME.2009.5201294","DOIUrl":"https://doi.org/10.1109/RME.2009.5201294","url":null,"abstract":"A stereo FM-radio transmitter with Radio Data System (RDS) support based on an all-digital PLL is presented. It has been designed as a fully integrated single-chip transmitter in a 90-nm CMOS technology to be compatible with digital deepsubmicrometer processes. Target application of the proposed system is the cointegration with baseband processors and transmitters for mobile communication systems. Nowadays mobile phones have a lot of multimedia capabilities e. g. an integrated MP3 player. The proposed transmitter enables a mobile device to stream audio data to a FM receiver which is popular and existing in most households world wide. RDS support allows to send additional information e. g. title and artist of a song. As mobile applications are the main target for the transmitter great attention has been attached to saving power and area. Therefore, the presented transmitter works on a 1V supply voltage and is aimed for using a 32.768 kHz reference crystal oscillator instead of the commonly used 26MHz reference oscillator while still providing wideband frequency modulation capability.","PeriodicalId":245992,"journal":{"name":"2009 Ph.D. Research in Microelectronics and Electronics","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133916138","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-12DOI: 10.1109/RME.2009.5201331
A. Danchiv, M. Bodea
This paper presents a modification of the standard autozero (AZ) amplifier topology that requires less chip area for achieving high offset performances. To improve the charge injection effects on the residual offset voltage a high gain ratio between the signal path and offset compensation loop is implemented. The novelty of this design consists in the different two input pair topologies used.
{"title":"An area efficient low offset autozero amplifier design","authors":"A. Danchiv, M. Bodea","doi":"10.1109/RME.2009.5201331","DOIUrl":"https://doi.org/10.1109/RME.2009.5201331","url":null,"abstract":"This paper presents a modification of the standard autozero (AZ) amplifier topology that requires less chip area for achieving high offset performances. To improve the charge injection effects on the residual offset voltage a high gain ratio between the signal path and offset compensation loop is implemented. The novelty of this design consists in the different two input pair topologies used.","PeriodicalId":245992,"journal":{"name":"2009 Ph.D. Research in Microelectronics and Electronics","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123062834","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-12DOI: 10.1109/RME.2009.5201340
M. Marx, R. Kokozinski, H. Muller
ACCURATE localization Systems, based on the measurement of the time of flight of a signal between radio devices, also known as Real Time Location Systems (RTLS) are becoming increasingly important especially in indoor applications. Due to severe multi path conditions, the largest problem for those RTLS systems is to detect the time of arrival of signals traveling over the direct line of sight path. We present issues of a new High Resolution Delay Locked Loop (HRDLL) architecture- that allows an efficient hardware implementation of a high resolution method for multi path mitigation, and demonstrate first results.
{"title":"High Resolution Delay Locked Loop for time synchronization with multi path mitigation","authors":"M. Marx, R. Kokozinski, H. Muller","doi":"10.1109/RME.2009.5201340","DOIUrl":"https://doi.org/10.1109/RME.2009.5201340","url":null,"abstract":"ACCURATE localization Systems, based on the measurement of the time of flight of a signal between radio devices, also known as Real Time Location Systems (RTLS) are becoming increasingly important especially in indoor applications. Due to severe multi path conditions, the largest problem for those RTLS systems is to detect the time of arrival of signals traveling over the direct line of sight path. We present issues of a new High Resolution Delay Locked Loop (HRDLL) architecture- that allows an efficient hardware implementation of a high resolution method for multi path mitigation, and demonstrate first results.","PeriodicalId":245992,"journal":{"name":"2009 Ph.D. Research in Microelectronics and Electronics","volume":"74 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132086155","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-12DOI: 10.1109/RME.2009.5201344
M. Meola, S. Carrato, G. Bernacchia, E. Bodano
In this paper a new large-signal discrete time model for dc-dc converters is derived. The model is meant to overcome the lack of large-signal dc-dc converter models which, firstly, are able to accurately predict converter behavior in different operating modes and, secondly, can be implemented both in Matlab/SIMULINK and HDL language. The model is well suited to perform system level simulation of digitally controlled SMPS using synthesis tools targeted to FPGA and ASIC implementation and, therefore, avoiding time consuming mixedsignal simulations from the first stages of the design.
{"title":"Discrete time large-signal model of dc-dc converters for system level simulation of digitally controlled SMPS","authors":"M. Meola, S. Carrato, G. Bernacchia, E. Bodano","doi":"10.1109/RME.2009.5201344","DOIUrl":"https://doi.org/10.1109/RME.2009.5201344","url":null,"abstract":"In this paper a new large-signal discrete time model for dc-dc converters is derived. The model is meant to overcome the lack of large-signal dc-dc converter models which, firstly, are able to accurately predict converter behavior in different operating modes and, secondly, can be implemented both in Matlab/SIMULINK and HDL language. The model is well suited to perform system level simulation of digitally controlled SMPS using synthesis tools targeted to FPGA and ASIC implementation and, therefore, avoiding time consuming mixedsignal simulations from the first stages of the design.","PeriodicalId":245992,"journal":{"name":"2009 Ph.D. Research in Microelectronics and Electronics","volume":"188 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133380095","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：