Pub Date : 2009-07-12DOI: 10.1109/RME.2009.5201371
Roberto Airoldi, F. Garzia, J. Nurmi
This paper describes the implementation of a 64-point FFT on a Multi-Processor System-on-Chip (MPSoC) composed of 9 homogeneous clusters. Each cluster is built around a RISC processor. The implementation technique adopted for the mapping of the FFT produces a speed-up of 6x which is close to the theoretical limit. This is due to a reduced overhead of intra-clusters communication.
{"title":"Implementation of a 64-point FFT on a Multi-Processor System-on-Chip","authors":"Roberto Airoldi, F. Garzia, J. Nurmi","doi":"10.1109/RME.2009.5201371","DOIUrl":"https://doi.org/10.1109/RME.2009.5201371","url":null,"abstract":"This paper describes the implementation of a 64-point FFT on a Multi-Processor System-on-Chip (MPSoC) composed of 9 homogeneous clusters. Each cluster is built around a RISC processor. The implementation technique adopted for the mapping of the FFT produces a speed-up of 6x which is close to the theoretical limit. This is due to a reduced overhead of intra-clusters communication.","PeriodicalId":245992,"journal":{"name":"2009 Ph.D. Research in Microelectronics and Electronics","volume":"89 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121178543","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-12DOI: 10.1109/RME.2009.5201303
T. Feldengut, R. Kokozinski, S. Kolnsberg
The operating range of passive UHF transponder systems is largely determined by the tag current consumption and the rectifier efficiency. Reading ranges of several meters have recently been reported for many state of the art RFID (Radio frequency IDentification) tags [1]. At this distance, the main issue for the rectifier design is the low amplitude of the high frequency antenna signal. Schottky diodes are often used for their low forward voltage drop and high switching speed. As an alternative to Schottky diodes, different circuit techniques for compensating the threshold voltage of standard transistor diodes have been utilized [4]. The transistor gates are biased near the threshold voltage, so that the devices effectively act as diodes with very low forward voltage drop. In the presented rectifier, a secondary diode charge pump is used to generate the DC bias for the threshold voltage compensation. The circuit is implemented in a standard CMOS technology and operates at a minimum available power of −11.3 dBm for an output DC power of 7.5 µW.
{"title":"A UHF voltage multiplier circuit using a threshold-voltage cancellation technique","authors":"T. Feldengut, R. Kokozinski, S. Kolnsberg","doi":"10.1109/RME.2009.5201303","DOIUrl":"https://doi.org/10.1109/RME.2009.5201303","url":null,"abstract":"The operating range of passive UHF transponder systems is largely determined by the tag current consumption and the rectifier efficiency. Reading ranges of several meters have recently been reported for many state of the art RFID (Radio frequency IDentification) tags [1]. At this distance, the main issue for the rectifier design is the low amplitude of the high frequency antenna signal. Schottky diodes are often used for their low forward voltage drop and high switching speed. As an alternative to Schottky diodes, different circuit techniques for compensating the threshold voltage of standard transistor diodes have been utilized [4]. The transistor gates are biased near the threshold voltage, so that the devices effectively act as diodes with very low forward voltage drop. In the presented rectifier, a secondary diode charge pump is used to generate the DC bias for the threshold voltage compensation. The circuit is implemented in a standard CMOS technology and operates at a minimum available power of −11.3 dBm for an output DC power of 7.5 µW.","PeriodicalId":245992,"journal":{"name":"2009 Ph.D. Research in Microelectronics and Electronics","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122700739","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-12DOI: 10.1109/RME.2009.5201367
Q. D. Hossain, G. Betta, L. Pancheri, D. Stoppa
CMOS image sensors integrate the image processing circuitry on the same chip as the light sensitive elements. Recently, lots of effort has been concentrated to create a standard CMOS photonic demodulator. A CMOS based current assisted photonic mixing demodulator is described in this paper. As a test vehicle, 10×10 pixel arrays in two different geometries have been fabricated with a 0.18μm CMOS technology. Remarkably small pixel size of 10×10 μm2 has been achieved. Preliminary experimental results demonstrate a good DC charge separation efficiency close to 100% and good demodulation capabilities up to 35MHz. The measurement results are compared to the performance of two different device array structures. These test devices represent the first step towards integrating a high resolution TOF based 3D CMOS image sensor.
{"title":"Current assisted photonic mixing demodulator implemented in 0.18μm standard CMOS technology","authors":"Q. D. Hossain, G. Betta, L. Pancheri, D. Stoppa","doi":"10.1109/RME.2009.5201367","DOIUrl":"https://doi.org/10.1109/RME.2009.5201367","url":null,"abstract":"CMOS image sensors integrate the image processing circuitry on the same chip as the light sensitive elements. Recently, lots of effort has been concentrated to create a standard CMOS photonic demodulator. A CMOS based current assisted photonic mixing demodulator is described in this paper. As a test vehicle, 10×10 pixel arrays in two different geometries have been fabricated with a 0.18μm CMOS technology. Remarkably small pixel size of 10×10 μm2 has been achieved. Preliminary experimental results demonstrate a good DC charge separation efficiency close to 100% and good demodulation capabilities up to 35MHz. The measurement results are compared to the performance of two different device array structures. These test devices represent the first step towards integrating a high resolution TOF based 3D CMOS image sensor.","PeriodicalId":245992,"journal":{"name":"2009 Ph.D. Research in Microelectronics and Electronics","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115529728","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-12DOI: 10.1109/RME.2009.5201368
S. Srivastava, C. Spagnol, E. Popovici
In multi-hop wireless sensor networks (WSN), the data transmitted from sensor nodes is highly susceptible to error corruption introduced by noisy channels. It is important to use some error correction schemes in order to control the errors introduced and to reduce the number of automatic requests for retransmission. The sensor nodes are typically wireless nodes with limited storage and computational power. Thus the error control schemes should be energy efficient at sensor nodes level. Most of the reported works assume that both encoding and decoding are performed at every node. The idea of this paper is to perform encoding only at the first node and decoding will be done at the base station. We assume that the base station has enough power to run complex decoding algorithms. This paper provides a model for energy consumed and the probability of receiving a correct word for multi-hop WSN at base station when considering a number of coding schemes and hops. The emphasis is on using powerful codes with low complexity encoding. Several powerful codes like Reed-Solomon (RS), list decoded RS codes, multivariate interpolation decoded RS codes (MIDRS) and Hermitian codes are investigated for this scheme. All these codes have very simple encoding based on RS type encoders and we will show that this scheme consumes less power than reported schemes while maintaining a low probability of error.
{"title":"Analysis of a set of error correcting schemes in multi-hop wireless sensor networks","authors":"S. Srivastava, C. Spagnol, E. Popovici","doi":"10.1109/RME.2009.5201368","DOIUrl":"https://doi.org/10.1109/RME.2009.5201368","url":null,"abstract":"In multi-hop wireless sensor networks (WSN), the data transmitted from sensor nodes is highly susceptible to error corruption introduced by noisy channels. It is important to use some error correction schemes in order to control the errors introduced and to reduce the number of automatic requests for retransmission. The sensor nodes are typically wireless nodes with limited storage and computational power. Thus the error control schemes should be energy efficient at sensor nodes level. Most of the reported works assume that both encoding and decoding are performed at every node. The idea of this paper is to perform encoding only at the first node and decoding will be done at the base station. We assume that the base station has enough power to run complex decoding algorithms. This paper provides a model for energy consumed and the probability of receiving a correct word for multi-hop WSN at base station when considering a number of coding schemes and hops. The emphasis is on using powerful codes with low complexity encoding. Several powerful codes like Reed-Solomon (RS), list decoded RS codes, multivariate interpolation decoded RS codes (MIDRS) and Hermitian codes are investigated for this scheme. All these codes have very simple encoding based on RS type encoders and we will show that this scheme consumes less power than reported schemes while maintaining a low probability of error.","PeriodicalId":245992,"journal":{"name":"2009 Ph.D. Research in Microelectronics and Electronics","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115303151","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-12DOI: 10.1109/RME.2009.5201348
Tüze Kuyucu, M. Trefzer, J. Miller, A. Tyrrell
The design of electronic circuits with model-free heuristics like evolutionary algorithms is an attractive concept and field of research. Although successful to a point, evolution of circuits that are bigger than a 3-bit multiplier is hindered by the scalability problem. Modelling the biological development as an artificial genotype-phenotype mapping mechanism has been shown to improve scalability on some simple circuit problems and pattern formations. As a candidate solution to the scalability issue, an artificial developmental system is presented.
{"title":"A scalable solution to n-bit parity via artificial development","authors":"Tüze Kuyucu, M. Trefzer, J. Miller, A. Tyrrell","doi":"10.1109/RME.2009.5201348","DOIUrl":"https://doi.org/10.1109/RME.2009.5201348","url":null,"abstract":"The design of electronic circuits with model-free heuristics like evolutionary algorithms is an attractive concept and field of research. Although successful to a point, evolution of circuits that are bigger than a 3-bit multiplier is hindered by the scalability problem. Modelling the biological development as an artificial genotype-phenotype mapping mechanism has been shown to improve scalability on some simple circuit problems and pattern formations. As a candidate solution to the scalability issue, an artificial developmental system is presented.","PeriodicalId":245992,"journal":{"name":"2009 Ph.D. Research in Microelectronics and Electronics","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126502076","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-12DOI: 10.1109/RME.2009.5201311
B. Thiel, A. Neyer, S. Heinen
The design of a multi-GHz digitally controlled oscillator (DCO) achieving low noise and power consumption is presented. The DCO is part of an all-digital phase lock loop (ADPLL) for an FM-radio transmitter prototype chip designed in a 90nm CMOS process. For this application the oscillator frequency of 3.05–3.45GHz is divided by 32 or 36 to cover the frequency span of 87.5–108.0MHz. A wide tuning range combined with a precise frequency tuning is achieved by different digitally controlled variable capacitors grouped as banks. Different approaches of these variable capacitors and oscillator topologies are simulated and compared. The design is chosen considering low phase noise combined with low power consumption. The power consumption of the designed DCO core is below 1.7mW at 1V supply voltage. This setup shows a phase noise below −154 dBc Hz at 20MHz offset. The chip area utilised by one DCO is 260 × 500 µm. Simulations show the performance of this DCO is state-of-the-art.
{"title":"Design of a low noise, low power 3.05–3.45 GHz digitally controlled oscillator in 90 nm CMOS","authors":"B. Thiel, A. Neyer, S. Heinen","doi":"10.1109/RME.2009.5201311","DOIUrl":"https://doi.org/10.1109/RME.2009.5201311","url":null,"abstract":"The design of a multi-GHz digitally controlled oscillator (DCO) achieving low noise and power consumption is presented. The DCO is part of an all-digital phase lock loop (ADPLL) for an FM-radio transmitter prototype chip designed in a 90nm CMOS process. For this application the oscillator frequency of 3.05–3.45GHz is divided by 32 or 36 to cover the frequency span of 87.5–108.0MHz. A wide tuning range combined with a precise frequency tuning is achieved by different digitally controlled variable capacitors grouped as banks. Different approaches of these variable capacitors and oscillator topologies are simulated and compared. The design is chosen considering low phase noise combined with low power consumption. The power consumption of the designed DCO core is below 1.7mW at 1V supply voltage. This setup shows a phase noise below −154 dBc Hz at 20MHz offset. The chip area utilised by one DCO is 260 × 500 µm. Simulations show the performance of this DCO is state-of-the-art.","PeriodicalId":245992,"journal":{"name":"2009 Ph.D. Research in Microelectronics and Electronics","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115825457","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-12DOI: 10.1109/RME.2009.5201300
A. Surano, E. Bonizzoni, F. Maloberti
This paper presents a novel signal frequency multiplier for very high speed applications. The proposed circuit is based on a simple but effective folding cell and it is able to generate an output at four times the frequency of the differential sine wave input. The circuit has been designed and optimized for a 40-nm CMOS technology and it has been fully simulated at the transistor level. Possible fabrication and timing mismatches are corrected with foreground calibration. Simulation results shows that the multiplier can provide an output signal at 40 GHz starting from a 10-GHz input signal consuming about 5 mW.
{"title":"On-chip sine wave frequency multiplier for 40-GHz signal generator","authors":"A. Surano, E. Bonizzoni, F. Maloberti","doi":"10.1109/RME.2009.5201300","DOIUrl":"https://doi.org/10.1109/RME.2009.5201300","url":null,"abstract":"This paper presents a novel signal frequency multiplier for very high speed applications. The proposed circuit is based on a simple but effective folding cell and it is able to generate an output at four times the frequency of the differential sine wave input. The circuit has been designed and optimized for a 40-nm CMOS technology and it has been fully simulated at the transistor level. Possible fabrication and timing mismatches are corrected with foreground calibration. Simulation results shows that the multiplier can provide an output signal at 40 GHz starting from a 10-GHz input signal consuming about 5 mW.","PeriodicalId":245992,"journal":{"name":"2009 Ph.D. Research in Microelectronics and Electronics","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126257570","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-12DOI: 10.1109/RME.2009.5201360
M. Carminati, G. Ferrari, F. Gozzini, M. Sampietro
Sub-attoFarad capacitance resolution is experimentally reached, demonstrating the suitability of the proposed instrumentation for the development of impedimetric molecular biosensors. The modular design of the system is illustrated along with novel analog solutions (providing high sensitivity over a DC-1MHz bandwidth), digital lock-in elaboration techniques and their impact on the final instrument resolution.
{"title":"Instrumentation with attoFarad resolution for electrochemical impedance measurements on molecular biosensors","authors":"M. Carminati, G. Ferrari, F. Gozzini, M. Sampietro","doi":"10.1109/RME.2009.5201360","DOIUrl":"https://doi.org/10.1109/RME.2009.5201360","url":null,"abstract":"Sub-attoFarad capacitance resolution is experimentally reached, demonstrating the suitability of the proposed instrumentation for the development of impedimetric molecular biosensors. The modular design of the system is illustrated along with novel analog solutions (providing high sensitivity over a DC-1MHz bandwidth), digital lock-in elaboration techniques and their impact on the final instrument resolution.","PeriodicalId":245992,"journal":{"name":"2009 Ph.D. Research in Microelectronics and Electronics","volume":"69 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114469622","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-12DOI: 10.1109/RME.2009.5201313
M. Dielacher, Martin Flatscher, W. Pribyl
This paper presents a 2.45 GHz low noise amplifier (LNA), built in a 0.13 µm CMOS process. It has an on-chip matching network and contains integrated bulk acoustic wave (BAW) resonators for narrow-band filtering at RF. The voltage gain of LNA and matching network is 31.5 dB with 4.7 dB noise figure (NF) at a current consumption of 2 mA.
{"title":"A low noise amplifier with on-chip matching network and integrated bulk Acoustic Wave resonators for high image rejection","authors":"M. Dielacher, Martin Flatscher, W. Pribyl","doi":"10.1109/RME.2009.5201313","DOIUrl":"https://doi.org/10.1109/RME.2009.5201313","url":null,"abstract":"This paper presents a 2.45 GHz low noise amplifier (LNA), built in a 0.13 µm CMOS process. It has an on-chip matching network and contains integrated bulk acoustic wave (BAW) resonators for narrow-band filtering at RF. The voltage gain of LNA and matching network is 31.5 dB with 4.7 dB noise figure (NF) at a current consumption of 2 mA.","PeriodicalId":245992,"journal":{"name":"2009 Ph.D. Research in Microelectronics and Electronics","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121596838","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-12DOI: 10.1109/RME.2009.5201361
B. Alandry, F. Mailly, L. Latorre, P. Nouet
This paper introduces an original MEMS multi-sensor platform for consumer applications. The whole set of sensors have been designed. manufactured and tested showing interesting performances for various type of applications. A demonstrator of a 3D orientation determination system has also been programmed on the platform proving the interest of such device.
{"title":"A MEMS-based multi-sensor platform for consumer applications","authors":"B. Alandry, F. Mailly, L. Latorre, P. Nouet","doi":"10.1109/RME.2009.5201361","DOIUrl":"https://doi.org/10.1109/RME.2009.5201361","url":null,"abstract":"This paper introduces an original MEMS multi-sensor platform for consumer applications. The whole set of sensors have been designed. manufactured and tested showing interesting performances for various type of applications. A demonstrator of a 3D orientation determination system has also been programmed on the platform proving the interest of such device.","PeriodicalId":245992,"journal":{"name":"2009 Ph.D. Research in Microelectronics and Electronics","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115728216","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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