Pub Date : 2009-07-12DOI: 10.1109/RME.2009.5201334
Song-Bok Kim, Yifan Wang, S. Heinen
In this paper, the jitter-induced noise is estimated in continuous-time quadrature bandpass sigma-delta modulator. The closedform formulas for the output spectrum of noise caused by clock jitter are derived. The correctness of the obtained analytical results is proved, based on model simulation. The noise introduced by clock jitter increases the in-band noise power, and therefore decreases the signal-to-noises ratio (SNR). The jitter-induced noise power depends on the noise shaping transfer function and the input signal level. The former's optimization gives improvement in the SNR. The dependence on the latter introduces the non-linearity of the modulator.
{"title":"Analysis of clock jitter in continuous-time quadrature bandpass sigma-delta modulators with NRZ pulses","authors":"Song-Bok Kim, Yifan Wang, S. Heinen","doi":"10.1109/RME.2009.5201334","DOIUrl":"https://doi.org/10.1109/RME.2009.5201334","url":null,"abstract":"In this paper, the jitter-induced noise is estimated in continuous-time quadrature bandpass sigma-delta modulator. The closedform formulas for the output spectrum of noise caused by clock jitter are derived. The correctness of the obtained analytical results is proved, based on model simulation. The noise introduced by clock jitter increases the in-band noise power, and therefore decreases the signal-to-noises ratio (SNR). The jitter-induced noise power depends on the noise shaping transfer function and the input signal level. The former's optimization gives improvement in the SNR. The dependence on the latter introduces the non-linearity of the modulator.","PeriodicalId":245992,"journal":{"name":"2009 Ph.D. Research in Microelectronics and Electronics","volume":"63 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131904627","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-12DOI: 10.1109/RME.2009.5201352
J. Zidek, O. Subrt, P. Martínek
Environment for testing analog-to-digital converters is presented in this article. It is a novel concept of powerful engine suitable for design and verification of generic type ADCs in Mentor Graphics IC Studio software. Source code of each block of the design is written in Verilog-A which offers relatively effortless portability on different design systems (e.g. Cadence). This approach brings to IC design engineers easy to use supportive tool. The core of our proposal is based on Servo- Loop with improved search algorithm [1]. The simulation outputs are curves of static INL and DNL. A part of article deals with the example of simple Flash ADC testing.
本文介绍了一种测试模数转换器的环境。它是一种新颖的功能强大的引擎，适用于Mentor Graphics IC Studio软件中通用型adc的设计和验证。设计的每个模块的源代码都是用Verilog-A编写的，它在不同的设计系统(例如Cadence)上提供了相对轻松的可移植性。这种方法为IC设计工程师带来了易于使用的辅助工具。我们的方案的核心是基于伺服环和改进的搜索算法[1]。仿真输出为静态INL和DNL曲线。本文的一部分讨论了一个简单的Flash ADC测试示例。
{"title":"Novel design evaluation engine for A/D converters","authors":"J. Zidek, O. Subrt, P. Martínek","doi":"10.1109/RME.2009.5201352","DOIUrl":"https://doi.org/10.1109/RME.2009.5201352","url":null,"abstract":"Environment for testing analog-to-digital converters is presented in this article. It is a novel concept of powerful engine suitable for design and verification of generic type ADCs in Mentor Graphics IC Studio software. Source code of each block of the design is written in Verilog-A which offers relatively effortless portability on different design systems (e.g. Cadence). This approach brings to IC design engineers easy to use supportive tool. The core of our proposal is based on Servo- Loop with improved search algorithm [1]. The simulation outputs are curves of static INL and DNL. A part of article deals with the example of simple Flash ADC testing.","PeriodicalId":245992,"journal":{"name":"2009 Ph.D. Research in Microelectronics and Electronics","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122043217","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-12DOI: 10.1109/RME.2009.5201359
Andreas Spickermann, B. Hosticka, A. Grabmaier
Photogate based active pixel sensors (PG APS) are often used in CMOS imaging. In advanced applications (e.g. high-speed imaging or time-of-flight distance measurements) the pixel performance requirements are high, especially as far as the optical sensitivity of the PG and the transfer and readout speed of photogenerated charge carriers are concerned. In this contribution we investigate the electrical and optical performances of different PG based pixel configurations fabricated in the 0.35μm CMOS process available at the Fraunhofer IMS. Finally, we propose a high resistivity polysilicon gate based pixel structure to be applied in 3-D time-offlight (ToF) measurements, that yields an enhanced charge transfer speed.
{"title":"Performance considerations for photogate based active pixel sensors","authors":"Andreas Spickermann, B. Hosticka, A. Grabmaier","doi":"10.1109/RME.2009.5201359","DOIUrl":"https://doi.org/10.1109/RME.2009.5201359","url":null,"abstract":"Photogate based active pixel sensors (PG APS) are often used in CMOS imaging. In advanced applications (e.g. high-speed imaging or time-of-flight distance measurements) the pixel performance requirements are high, especially as far as the optical sensitivity of the PG and the transfer and readout speed of photogenerated charge carriers are concerned. In this contribution we investigate the electrical and optical performances of different PG based pixel configurations fabricated in the 0.35μm CMOS process available at the Fraunhofer IMS. Finally, we propose a high resistivity polysilicon gate based pixel structure to be applied in 3-D time-offlight (ToF) measurements, that yields an enhanced charge transfer speed.","PeriodicalId":245992,"journal":{"name":"2009 Ph.D. Research in Microelectronics and Electronics","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131792765","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-12DOI: 10.1109/RME.2009.5201375
D. Halupka, A. Sheikholeslami
Sub-22nm processes necessitate the use of larger SRAM cells in order to counter the effects of increasing silicon variation. However, storage density is reduced when the SRAM cell grows in size. This paper proposes the use of a cross-coupled bit line (BL) biasing scheme that retains SRAM's fast access speed while reducing the read-access failures in the presence of V variation, without excessively increasing the SRAM cell size. We have shown, by extensive Monte-Carlo simulations using 22-nm predictive CMOS models, that the proposed scheme reduces the cell area by 6.5% compared to the conventional BL biasing schemes also analyzed in this paper.
{"title":"Cross-coupled bit-line biasing for 22-nm SRAM","authors":"D. Halupka, A. Sheikholeslami","doi":"10.1109/RME.2009.5201375","DOIUrl":"https://doi.org/10.1109/RME.2009.5201375","url":null,"abstract":"Sub-22nm processes necessitate the use of larger SRAM cells in order to counter the effects of increasing silicon variation. However, storage density is reduced when the SRAM cell grows in size. This paper proposes the use of a cross-coupled bit line (BL) biasing scheme that retains SRAM's fast access speed while reducing the read-access failures in the presence of V variation, without excessively increasing the SRAM cell size. We have shown, by extensive Monte-Carlo simulations using 22-nm predictive CMOS models, that the proposed scheme reduces the cell area by 6.5% compared to the conventional BL biasing schemes also analyzed in this paper.","PeriodicalId":245992,"journal":{"name":"2009 Ph.D. Research in Microelectronics and Electronics","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127655521","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-12DOI: 10.1109/RME.2009.5201321
H. Erkens, Ye Zhang, R. Wunderlich
A phase shifter with polar output has been implemented with techniques commonly used for quadrature phase shifters. The hybrid approach employs dual-path programmable gain amplifiers and polyphase filters as cascaded quadrature phase shifter stages. Each stage is implemented using active components as well as differential RC filters which consume less area than the typical LC low-pass/high-pass approach. 5-bit phase resolution has been implemented. A 4-bit linear PGA follows the phase shifter chain for antenna tapering. The RFIC employing LNA and balancing devices has been been designed in a 0.25 µm SiGe BiCMOS technology which guarantees a low cost solution for medium scale integration such as in phased arrays. According to simulation results, a very homogeneous distribution of phase/gain states can be expected over a wide bandwidth. Achieved gain and noise figure in the band of interest (2.9 GHz ... 3.1 GHz) exhibit 25.9 dB and 11.6 dB, respectively, with a power consumption of 114mW.
用正交移相器常用的技术实现了具有极性输出的移相器。混合方法采用双路可编程增益放大器和多相滤波器作为级联的正交移相器级。每个级都使用有源元件以及差分RC滤波器实现，其消耗的面积小于典型的LC低通/高通方法。实现了5位相位分辨率。4位线性PGA遵循移相器链，用于天线变细。采用LNA和平衡器件的RFIC采用0.25 μ m SiGe BiCMOS技术设计，保证了相控阵等中等规模集成的低成本解决方案。根据仿真结果，在较宽的带宽范围内，相位/增益状态的分布非常均匀。在目标频带(2.9 GHz…3.1 GHz)分别为25.9 dB和11.6 dB，功耗为114mW。
{"title":"Building a circle with squares: A polar phase shifter based on cartesian methods","authors":"H. Erkens, Ye Zhang, R. Wunderlich","doi":"10.1109/RME.2009.5201321","DOIUrl":"https://doi.org/10.1109/RME.2009.5201321","url":null,"abstract":"A phase shifter with polar output has been implemented with techniques commonly used for quadrature phase shifters. The hybrid approach employs dual-path programmable gain amplifiers and polyphase filters as cascaded quadrature phase shifter stages. Each stage is implemented using active components as well as differential RC filters which consume less area than the typical LC low-pass/high-pass approach. 5-bit phase resolution has been implemented. A 4-bit linear PGA follows the phase shifter chain for antenna tapering. The RFIC employing LNA and balancing devices has been been designed in a 0.25 µm SiGe BiCMOS technology which guarantees a low cost solution for medium scale integration such as in phased arrays. According to simulation results, a very homogeneous distribution of phase/gain states can be expected over a wide bandwidth. Achieved gain and noise figure in the band of interest (2.9 GHz ... 3.1 GHz) exhibit 25.9 dB and 11.6 dB, respectively, with a power consumption of 114mW.","PeriodicalId":245992,"journal":{"name":"2009 Ph.D. Research in Microelectronics and Electronics","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129379191","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-12DOI: 10.1109/RME.2009.5201299
Mabrouki Aya, T. Thierry, Deval Yann, B. Jean-Baptiste
In this paper, a variable gain CMOS low noise amplifier (LNA) suitable for WiMAX (Worldwide Interoperability for Microwave Access) applications, 2.4 GHz, is reported. The design concept is based on the novel idea of body biasing. In high mode gain the cascode LNA, implemented in a 0.13µm CMOS standard process and supplied under 1.1V, exhibits a power gain of 15.44 dB, a 2.87 dB noise figure (NF), and −4.62 dBm of third order intercept point (IIP3) for a 4.64 mA current consumption and a bulk to source Voltage, VBS, of 0.3V. Tuning VBS to −0.55V, the LNA operates in the low gain mode, achieving 8.23 dB of power gain, 5 dB NF and 6.63 dBm IIP3 under a constrained power consumption of 1.1 mW.
{"title":"A variable gain 2.4-GHz CMOS low noise amplifier employing body biasing","authors":"Mabrouki Aya, T. Thierry, Deval Yann, B. Jean-Baptiste","doi":"10.1109/RME.2009.5201299","DOIUrl":"https://doi.org/10.1109/RME.2009.5201299","url":null,"abstract":"In this paper, a variable gain CMOS low noise amplifier (LNA) suitable for WiMAX (Worldwide Interoperability for Microwave Access) applications, 2.4 GHz, is reported. The design concept is based on the novel idea of body biasing. In high mode gain the cascode LNA, implemented in a 0.13µm CMOS standard process and supplied under 1.1V, exhibits a power gain of 15.44 dB, a 2.87 dB noise figure (NF), and −4.62 dBm of third order intercept point (IIP3) for a 4.64 mA current consumption and a bulk to source Voltage, VBS, of 0.3V. Tuning VBS to −0.55V, the LNA operates in the low gain mode, achieving 8.23 dB of power gain, 5 dB NF and 6.63 dBm IIP3 under a constrained power consumption of 1.1 mW.","PeriodicalId":245992,"journal":{"name":"2009 Ph.D. Research in Microelectronics and Electronics","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131976849","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-12DOI: 10.1109/RME.2009.5201307
A. Amaricai, M. Vladutiu, O. Boncalo
In this paper, hardware units for interval addition, multiplication and divide-add fused are presented. Regarding interval addition, a new architecture of double path adder, is presented. This architecture exploits the parallel structure of double path adder. Regarding multiplication, the proposed architecture is based on a dual result multiplier (floating point multiplication unit with two differently rounded results for the same pair of operands) and two floating point comparators. The goal of the divide-add fused unit is to increase the performance of the interval Newton's method. Algorithm and architecture for this operation, inspired by the ones used for multiply-add fused, are proposed.
{"title":"Design of floating point units for interval arithmetic","authors":"A. Amaricai, M. Vladutiu, O. Boncalo","doi":"10.1109/RME.2009.5201307","DOIUrl":"https://doi.org/10.1109/RME.2009.5201307","url":null,"abstract":"In this paper, hardware units for interval addition, multiplication and divide-add fused are presented. Regarding interval addition, a new architecture of double path adder, is presented. This architecture exploits the parallel structure of double path adder. Regarding multiplication, the proposed architecture is based on a dual result multiplier (floating point multiplication unit with two differently rounded results for the same pair of operands) and two floating point comparators. The goal of the divide-add fused unit is to increase the performance of the interval Newton's method. Algorithm and architecture for this operation, inspired by the ones used for multiply-add fused, are proposed.","PeriodicalId":245992,"journal":{"name":"2009 Ph.D. Research in Microelectronics and Electronics","volume":"13 3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132385052","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-12DOI: 10.1109/RME.2009.5201365
Hyuntae Kim, B. Bakkaloglu
A fully integrated 8-channel gas readout analog front-end IC is presented. The IC enables detection and identification of harmful environmental pollutants in exhaust gas fumes for extended periods, which in turn helps with correlating different pollutants with several illnesses. The system can read out an array of eight conductometric and amperometric electrochemical sensors while multiplexing analog-front-end circuitry to reduce die size. The IC consists of a low noise front-end and low DC offset, multiplexed ADC. The conductometric sensor uses a novel current steering approach for extracting impedance of the sensor. To reduce 1/f noise and DC offset voltage, a nested-chopper stabilized ADC is used. The detection analog front-end achieves 67.2 dB SNR at 1.57 mW quiescent power consumption per channel, enabling a chemical detection sensitivity of 1ppm in volume.
{"title":"An 0.18μm CMOS electrochemical sensor readout IC for exhaust gas monitoring","authors":"Hyuntae Kim, B. Bakkaloglu","doi":"10.1109/RME.2009.5201365","DOIUrl":"https://doi.org/10.1109/RME.2009.5201365","url":null,"abstract":"A fully integrated 8-channel gas readout analog front-end IC is presented. The IC enables detection and identification of harmful environmental pollutants in exhaust gas fumes for extended periods, which in turn helps with correlating different pollutants with several illnesses. The system can read out an array of eight conductometric and amperometric electrochemical sensors while multiplexing analog-front-end circuitry to reduce die size. The IC consists of a low noise front-end and low DC offset, multiplexed ADC. The conductometric sensor uses a novel current steering approach for extracting impedance of the sensor. To reduce 1/f noise and DC offset voltage, a nested-chopper stabilized ADC is used. The detection analog front-end achieves 67.2 dB SNR at 1.57 mW quiescent power consumption per channel, enabling a chemical detection sensitivity of 1ppm in volume.","PeriodicalId":245992,"journal":{"name":"2009 Ph.D. Research in Microelectronics and Electronics","volume":"9 2","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120840866","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-12DOI: 10.1109/RME.2009.5201377
S. Veeramachaneni, M. Srinivas
Sub-threshold design of CMOS logic circuits is important for ultra low-power operation. With continuous scaling of MOS devices to nanometer sizes however, conventional CMOS logic style may not function properly at 65nm and below due to a variety of leakage currents flowing. Thus alternative logic styles, such as, transmission-gate, have been proposed for sub-threshold operation in nanometer regime. In this work, a new CMOS logic style, that results in reduced leakage currents both in active and idle modes of operation leading to a better static and dynamic performance, is proposed. Simulations have been carried out in Cadence Spectre to verify the functionality of the gates using standard 65nm technology. Results indicate that static power reduction of up to 25% has been achieved. The utility of the new logic style is demonstrated with a 1-bit full-adder circuit.
{"title":"Redefining CMOS logic style for subthreshold operation","authors":"S. Veeramachaneni, M. Srinivas","doi":"10.1109/RME.2009.5201377","DOIUrl":"https://doi.org/10.1109/RME.2009.5201377","url":null,"abstract":"Sub-threshold design of CMOS logic circuits is important for ultra low-power operation. With continuous scaling of MOS devices to nanometer sizes however, conventional CMOS logic style may not function properly at 65nm and below due to a variety of leakage currents flowing. Thus alternative logic styles, such as, transmission-gate, have been proposed for sub-threshold operation in nanometer regime. In this work, a new CMOS logic style, that results in reduced leakage currents both in active and idle modes of operation leading to a better static and dynamic performance, is proposed. Simulations have been carried out in Cadence Spectre to verify the functionality of the gates using standard 65nm technology. Results indicate that static power reduction of up to 25% has been achieved. The utility of the new logic style is demonstrated with a 1-bit full-adder circuit.","PeriodicalId":245992,"journal":{"name":"2009 Ph.D. Research in Microelectronics and Electronics","volume":"80 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126265665","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-12DOI: 10.1109/RME.2009.5201329
Eduard Garcia, R. E. Bosch
In this paper we propose an alternative IIR filter architecture for tail cancellation of a TPC detector in the ALICE experiment. The proposed filter architecture allows a reduction in the width of the data-path minimizing the circuit complexity and thus its power consumption. There is no additional signal processing penalty. The choice of the multiplier architecture in the IIR filter allows operation at a reduced supply voltage to 0.8 V, while maintaining fast operation, reducing the power consumption in the digital circuit to 45 % of what would be obtained if the nominal supply voltage 1.2 V was used.
{"title":"Low power optimization of an IIR for tail cancellation in High Energy Physics applications","authors":"Eduard Garcia, R. E. Bosch","doi":"10.1109/RME.2009.5201329","DOIUrl":"https://doi.org/10.1109/RME.2009.5201329","url":null,"abstract":"In this paper we propose an alternative IIR filter architecture for tail cancellation of a TPC detector in the ALICE experiment. The proposed filter architecture allows a reduction in the width of the data-path minimizing the circuit complexity and thus its power consumption. There is no additional signal processing penalty. The choice of the multiplier architecture in the IIR filter allows operation at a reduced supply voltage to 0.8 V, while maintaining fast operation, reducing the power consumption in the digital circuit to 45 % of what would be obtained if the nominal supply voltage 1.2 V was used.","PeriodicalId":245992,"journal":{"name":"2009 Ph.D. Research in Microelectronics and Electronics","volume":"119 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114931186","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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