Pub Date : 2009-07-12DOI: 10.1109/RME.2009.5201312
Ping Zhao, T. Hollstein, M. Glesner
This paper presents the necessity and potential of using tunable matching network in UHF RFID transponders. A compact I/V model for diode-connected MOSFET in strong inversion and sub-threshold regions, which is based on the UMC 0.13-µm technology, is utilized to analyze the influence of the dynamic load to the performance of the power harvesting circuit. A direct dependence of the voltage sensitivity on the varying load current has been found and formulated. The dependence suggests the necessity of optimizing dynamically the impedance matching network between the antenna and the rectifier according to the transponder operation status. A concept of the operationcontrolled tunable matching network is finally proposed.
{"title":"Analysis on power harvesting circuits with tunable matching network for improved efficiency","authors":"Ping Zhao, T. Hollstein, M. Glesner","doi":"10.1109/RME.2009.5201312","DOIUrl":"https://doi.org/10.1109/RME.2009.5201312","url":null,"abstract":"This paper presents the necessity and potential of using tunable matching network in UHF RFID transponders. A compact I/V model for diode-connected MOSFET in strong inversion and sub-threshold regions, which is based on the UMC 0.13-µm technology, is utilized to analyze the influence of the dynamic load to the performance of the power harvesting circuit. A direct dependence of the voltage sensitivity on the varying load current has been found and formulated. The dependence suggests the necessity of optimizing dynamically the impedance matching network between the antenna and the rectifier according to the transponder operation status. A concept of the operationcontrolled tunable matching network is finally proposed.","PeriodicalId":245992,"journal":{"name":"2009 Ph.D. Research in Microelectronics and Electronics","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129180427","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-12DOI: 10.1109/RME.2009.5201316
D. Das, S. Collins
The digital imager sensors integrated into most current systems have a linear response and a dynamic range of 60dB or less. This is not a large enough dynamic range for some applications. Although suitable for most applications there are some emerging applications, such as automotive safety, that require a dynamic range of 120dB. In this paper a pixel circuit for a 0.35-µm CMOS technology is described that integrates the photocurrent in the pixel for time that depends upon the photocurrent to create a wide dynamic range response. Similar pixels have been described previously, however for this process the critical user defined reference voltage has been modified to compensate for capacitive coupling between nodes within the pixel. More importantly, a MOSFET functioning as a charge spill gate has been included in the pixel to improve the pixel's low light sensitivity.
{"title":"A wide dynamic range integrating pixel with controllable logarithmic photoresponse","authors":"D. Das, S. Collins","doi":"10.1109/RME.2009.5201316","DOIUrl":"https://doi.org/10.1109/RME.2009.5201316","url":null,"abstract":"The digital imager sensors integrated into most current systems have a linear response and a dynamic range of 60dB or less. This is not a large enough dynamic range for some applications. Although suitable for most applications there are some emerging applications, such as automotive safety, that require a dynamic range of 120dB. In this paper a pixel circuit for a 0.35-µm CMOS technology is described that integrates the photocurrent in the pixel for time that depends upon the photocurrent to create a wide dynamic range response. Similar pixels have been described previously, however for this process the critical user defined reference voltage has been modified to compensate for capacitive coupling between nodes within the pixel. More importantly, a MOSFET functioning as a charge spill gate has been included in the pixel to improve the pixel's low light sensitivity.","PeriodicalId":245992,"journal":{"name":"2009 Ph.D. Research in Microelectronics and Electronics","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126000650","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-12DOI: 10.1109/RME.2009.5201349
Alienor Richard, C. Hernalsteens, F. Robert
The paper presents Nessie [1], an original multicriteria exploration tool able to decide on functional and nonfunctional aspects of SoC's based on the application and platform descriptions and the costs (energy, execution time, area, ...). Indeed, the different performance prediction tools we can find in the literature, aiming at helping designers to take decisions and find efficient solutions, have some limitations that we wanted to overcome. To validate our tool, we have chosen real case study. In particular, we present here an example based on a 3MF MPSoC platform executing a real time AVC/H.264 video decoding extended to 3D-stacked architectures. Results given by Nessie, based on the average wire power consumption, have reinforced us in the utility of such a tool to help designers to take decision, especially in huge design spaces like embedded SoC ones.
{"title":"Development and validation of Nessie: a multi-criteria performance estimation tool for SoC","authors":"Alienor Richard, C. Hernalsteens, F. Robert","doi":"10.1109/RME.2009.5201349","DOIUrl":"https://doi.org/10.1109/RME.2009.5201349","url":null,"abstract":"The paper presents Nessie [1], an original multicriteria exploration tool able to decide on functional and nonfunctional aspects of SoC's based on the application and platform descriptions and the costs (energy, execution time, area, ...). Indeed, the different performance prediction tools we can find in the literature, aiming at helping designers to take decisions and find efficient solutions, have some limitations that we wanted to overcome. To validate our tool, we have chosen real case study. In particular, we present here an example based on a 3MF MPSoC platform executing a real time AVC/H.264 video decoding extended to 3D-stacked architectures. Results given by Nessie, based on the average wire power consumption, have reinforced us in the utility of such a tool to help designers to take decision, especially in huge design spaces like embedded SoC ones.","PeriodicalId":245992,"journal":{"name":"2009 Ph.D. Research in Microelectronics and Electronics","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130847754","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-12DOI: 10.1109/RME.2009.5201322
T. O'Dwyer, M. Kennedy
Matched pairs or arrays of resistive elements are an important aspect of many analog and mixed signal semiconductor circuit designs. Such structures are often implemented using the polysilicon layers in a typical CMOS process. In many processes, there are two or more such layers at the disposal of the designer. These typically have differing resistivity characteristics and matching performance. This paper examines the resistance matching characteristics of the polysilicon layers on a commercial CMOS process. The study encompasses both wafer-to-wafer and die-to-die variations, and presents models to describe the behavior. Using these models, conclusions are drawn regarding the appropriate layer to use to minimize the silicon area for target values of resistance and matching.
{"title":"Comparison of resistor matching performance of polysilicon films in a CMOS process","authors":"T. O'Dwyer, M. Kennedy","doi":"10.1109/RME.2009.5201322","DOIUrl":"https://doi.org/10.1109/RME.2009.5201322","url":null,"abstract":"Matched pairs or arrays of resistive elements are an important aspect of many analog and mixed signal semiconductor circuit designs. Such structures are often implemented using the polysilicon layers in a typical CMOS process. In many processes, there are two or more such layers at the disposal of the designer. These typically have differing resistivity characteristics and matching performance. This paper examines the resistance matching characteristics of the polysilicon layers on a commercial CMOS process. The study encompasses both wafer-to-wafer and die-to-die variations, and presents models to describe the behavior. Using these models, conclusions are drawn regarding the appropriate layer to use to minimize the silicon area for target values of resistance and matching.","PeriodicalId":245992,"journal":{"name":"2009 Ph.D. Research in Microelectronics and Electronics","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131485709","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-12DOI: 10.1109/RME.2009.5201374
M. Ichihashi
This paper discusses the design requirement of on-chip dc-dc converter for block-level Dynamic Voltage Scaling (DVS). The target application is low-power SoC where DVS can be applied to all the implemented logic blocks. The proposed converter occupies only five bonding pads and the simulation demonstrates that the leakage current is only 84 nA in the standby mode. As shown by a set of equations based on a first order model, the proposed converter does not need any pulse frequency modulator (PFM).
{"title":"Design requirement of on-chip DC-DC converter for block-level Dynamic Voltage Scaling","authors":"M. Ichihashi","doi":"10.1109/RME.2009.5201374","DOIUrl":"https://doi.org/10.1109/RME.2009.5201374","url":null,"abstract":"This paper discusses the design requirement of on-chip dc-dc converter for block-level Dynamic Voltage Scaling (DVS). The target application is low-power SoC where DVS can be applied to all the implemented logic blocks. The proposed converter occupies only five bonding pads and the simulation demonstrates that the leakage current is only 84 nA in the standby mode. As shown by a set of equations based on a first order model, the proposed converter does not need any pulse frequency modulator (PFM).","PeriodicalId":245992,"journal":{"name":"2009 Ph.D. Research in Microelectronics and Electronics","volume":"118 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134543201","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-12DOI: 10.1109/RME.2009.5201317
O. Novák, Wei Wu, C. Charles
The potential of wireless ultra-wide-band (UWB) technology for data links in biomedical implants is discussed. Most current technologies have been proven unsuitable for use in future high complexity applications. Emerging systems such as vision prosthesis will require significantly higher data rates and power efficiency. UWB offers unique properties that make it an attractive candidate to meet the increased demand. Furthermore, initial results of an UWB transceiver design are reported. A pulse generator and a wide-band LNA have been designed and fabricated in a 65nm CMOS technology. Test results are also presented.
{"title":"Wireless ultra-wide-band data link for biomedical implants","authors":"O. Novák, Wei Wu, C. Charles","doi":"10.1109/RME.2009.5201317","DOIUrl":"https://doi.org/10.1109/RME.2009.5201317","url":null,"abstract":"The potential of wireless ultra-wide-band (UWB) technology for data links in biomedical implants is discussed. Most current technologies have been proven unsuitable for use in future high complexity applications. Emerging systems such as vision prosthesis will require significantly higher data rates and power efficiency. UWB offers unique properties that make it an attractive candidate to meet the increased demand. Furthermore, initial results of an UWB transceiver design are reported. A pulse generator and a wide-band LNA have been designed and fabricated in a 65nm CMOS technology. Test results are also presented.","PeriodicalId":245992,"journal":{"name":"2009 Ph.D. Research in Microelectronics and Electronics","volume":"105 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122982789","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-12DOI: 10.1109/RME.2009.5201302
M. Mincica, D. Pepe, Agnese Giordano1, D. Zito
A correlator-based receiver of an UWB radar for cardio-pulmonary monitoring is presented. It consists of Low Noise Amplifier, analog Multiplier and Integrator. The UWB LNA shows a measured −3 dB band close to 5 GHz, from 3.56 and 8.46 GHz, a transducer gain of 22.7 dB at 5.2 GHz, an input reflection coefficient lower than −10.5 dB in −3 dB band, and a input-referred 1-dB compression point of −19.7 dBm, in excellent agreement with the post-layout simulation results. The Multiplier shows a direct conversion gain (GC) equal to 4.3 at 5 GHz, and implements the analog multiplication with a good linearity. The Integrator (i.e. OTA) shows a −3 dB band of 40 Hz, a voltage gain of 32 dB and a phase margin of 90 degree with an input linear range of 100 mV. In the linear range the OTA is characterized by a THD of about −38 dB.
{"title":"CMOS correlation receiver for UWB pulse radar","authors":"M. Mincica, D. Pepe, Agnese Giordano1, D. Zito","doi":"10.1109/RME.2009.5201302","DOIUrl":"https://doi.org/10.1109/RME.2009.5201302","url":null,"abstract":"A correlator-based receiver of an UWB radar for cardio-pulmonary monitoring is presented. It consists of Low Noise Amplifier, analog Multiplier and Integrator. The UWB LNA shows a measured −3 dB band close to 5 GHz, from 3.56 and 8.46 GHz, a transducer gain of 22.7 dB at 5.2 GHz, an input reflection coefficient lower than −10.5 dB in −3 dB band, and a input-referred 1-dB compression point of −19.7 dBm, in excellent agreement with the post-layout simulation results. The Multiplier shows a direct conversion gain (GC) equal to 4.3 at 5 GHz, and implements the analog multiplication with a good linearity. The Integrator (i.e. OTA) shows a −3 dB band of 40 Hz, a voltage gain of 32 dB and a phase margin of 90 degree with an input linear range of 100 mV. In the linear range the OTA is characterized by a THD of about −38 dB.","PeriodicalId":245992,"journal":{"name":"2009 Ph.D. Research in Microelectronics and Electronics","volume":"91 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116974089","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-12DOI: 10.1109/RME.2009.5201289
D. Gruner, G. Boeck
A fully integrated 5.6-6.4 GHz power amplifier is implemented in a 0.25 um SiGe-HBT technology using an onchip transformer combining structure. The novel combiner topology combines the output power of two push pull pairs and leads to a reduced transistor size compared to a conventional combiner while enhancing the efficiency and maintaining the maximum output power. Electromagnetic modeling of the whole chip layout has been carried out to optimize the performance of the presented circuit. At 6 GHz and a supply voltage of 1.2/1.8 V the single-stage power amplifier achieves a measured output power of 18/21 dBm at 1 dB power compression and 21/24 dBm in saturation region. The maximum power added efficiency is 24.7%. A small signal gain of 12 dB was observed at the center frequency of 6 GHz.
{"title":"Fully integrated 5.6–6.4 GHz power amplifier using transformer combining","authors":"D. Gruner, G. Boeck","doi":"10.1109/RME.2009.5201289","DOIUrl":"https://doi.org/10.1109/RME.2009.5201289","url":null,"abstract":"A fully integrated 5.6-6.4 GHz power amplifier is implemented in a 0.25 um SiGe-HBT technology using an onchip transformer combining structure. The novel combiner topology combines the output power of two push pull pairs and leads to a reduced transistor size compared to a conventional combiner while enhancing the efficiency and maintaining the maximum output power. Electromagnetic modeling of the whole chip layout has been carried out to optimize the performance of the presented circuit. At 6 GHz and a supply voltage of 1.2/1.8 V the single-stage power amplifier achieves a measured output power of 18/21 dBm at 1 dB power compression and 21/24 dBm in saturation region. The maximum power added efficiency is 24.7%. A small signal gain of 12 dB was observed at the center frequency of 6 GHz.","PeriodicalId":245992,"journal":{"name":"2009 Ph.D. Research in Microelectronics and Electronics","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124048687","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-12DOI: 10.1109/RME.2009.5201347
Umer Farooq, H. Parvez, Z. Marrakchi, H. Mehrez
In this paper, we present a new multilevel hierarchical (Tree-based) coarse-grained FPGA architecture. This architecture comprises two unidirectional interconnects, a downward interconnect and an upward interconnect. The proposed architecture can support various kinds of coarse-grained blocks. These coarse-grained blocks are defined using an architecture description file. A new software flow has been developed to evaluate the proposed architecture. New tools are developed to support this software flow and they have resulted in the successful placement and routing of different DSP benchmarks on the proposed architecture. A comparison of coarse-grained Treebased and fine-grained Tree-based architectures is performed. This comparison reveals an average area gain of 41% for coarsegrained Tree-based architecture over fine-grained Tree-based architecture. Similarly a comparison of Tree-based and Meshbased coarse-grained architectures shows an average area saving of 60% for Tree-based coarse-grained architectures over Meshbased coarse-grained architectures.
{"title":"A new Tree-based coarse-grained FPGA architecture","authors":"Umer Farooq, H. Parvez, Z. Marrakchi, H. Mehrez","doi":"10.1109/RME.2009.5201347","DOIUrl":"https://doi.org/10.1109/RME.2009.5201347","url":null,"abstract":"In this paper, we present a new multilevel hierarchical (Tree-based) coarse-grained FPGA architecture. This architecture comprises two unidirectional interconnects, a downward interconnect and an upward interconnect. The proposed architecture can support various kinds of coarse-grained blocks. These coarse-grained blocks are defined using an architecture description file. A new software flow has been developed to evaluate the proposed architecture. New tools are developed to support this software flow and they have resulted in the successful placement and routing of different DSP benchmarks on the proposed architecture. A comparison of coarse-grained Treebased and fine-grained Tree-based architectures is performed. This comparison reveals an average area gain of 41% for coarsegrained Tree-based architecture over fine-grained Tree-based architecture. Similarly a comparison of Tree-based and Meshbased coarse-grained architectures shows an average area saving of 60% for Tree-based coarse-grained architectures over Meshbased coarse-grained architectures.","PeriodicalId":245992,"journal":{"name":"2009 Ph.D. Research in Microelectronics and Electronics","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126954834","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-12DOI: 10.1109/RME.2009.5201335
Adem Coskun, I. Kale
This paper proposes a multi-dimensional matched filtering technique for spatial diversity receivers. The coefficients of the multi-dimensional matched filter are identified by making use of an adaptive filter, the update of which doesn't require the transmission of any training symbols within the transmitted data stream. Therefore the use of the proposed technique improves the data rate efficiency. Furthermore, it is well known that implementing multi-dimensional matched filtering is essential for equalization purposes to obtain the optimum error rate performance from spatial diversity receivers. For that reason the technique is designed not only to identify the unknown matched filter but also to simultaneously lead to the equalization of the channel too. In order to update the adaptive filter, the Constant Modulus Algorithm (CMA) is utilized, which is an implementation convenient algorithm. Therefore the proposed technique is not computationally complex in comparison to those identification algorithms proposed for spatial diversity receivers. Simulations are provided to present the equalization performance of the novel technique.
{"title":"Multi-dimensional matched filter identification technique for channel equalization deployed in spatial diversity receivers","authors":"Adem Coskun, I. Kale","doi":"10.1109/RME.2009.5201335","DOIUrl":"https://doi.org/10.1109/RME.2009.5201335","url":null,"abstract":"This paper proposes a multi-dimensional matched filtering technique for spatial diversity receivers. The coefficients of the multi-dimensional matched filter are identified by making use of an adaptive filter, the update of which doesn't require the transmission of any training symbols within the transmitted data stream. Therefore the use of the proposed technique improves the data rate efficiency. Furthermore, it is well known that implementing multi-dimensional matched filtering is essential for equalization purposes to obtain the optimum error rate performance from spatial diversity receivers. For that reason the technique is designed not only to identify the unknown matched filter but also to simultaneously lead to the equalization of the channel too. In order to update the adaptive filter, the Constant Modulus Algorithm (CMA) is utilized, which is an implementation convenient algorithm. Therefore the proposed technique is not computationally complex in comparison to those identification algorithms proposed for spatial diversity receivers. Simulations are provided to present the equalization performance of the novel technique.","PeriodicalId":245992,"journal":{"name":"2009 Ph.D. Research in Microelectronics and Electronics","volume":"94 7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127985713","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：