Pub Date : 2009-07-12DOI: 10.1109/RME.2009.5201373
Y. Benabboud, A. Bosio1, O. Riew
This paper presents a diagnosis method targeting System-On-Chip (SoC). We first show the complexity and the issues related to the diagnosis of SoC. Then we propose a diagnosis approach based on fault simulation performed in two phases, (i) a fault localization phase and (ii) a fault model allocation phase. The fault localization phase peovides a set of suspected lines able to explain the observed errors. The fault model allocation phase associates a set of fault models on each suspected line. The main advantages of this approach are that the fault localization phase is fault model independent, and that the fault model allocation phase is able to deal with several fault models at a time (static and dynamic). Experimental results show the diagnosis accuracy, in terms of absolute number of suspects, of the proposed approach. Moreover, a comparison with an industrial reference tool highlights the reliability of our approach.
本文介绍了一种针对片上系统（SoC）的诊断方法。我们首先说明了 SoC 诊断的复杂性和相关问题。然后，我们提出了一种基于故障模拟的诊断方法，分两个阶段进行：(i) 故障定位阶段和 (ii) 故障模型分配阶段。故障定位阶段提供一组能够解释观察到的错误的可疑线路。故障模型分配阶段为每条可疑线路关联一组故障模型。这种方法的主要优点是故障定位阶段与故障模型无关，而且故障模型分配阶段能够同时处理多个故障模型（静态和动态）。实验结果表明，从疑点的绝对数量来看，所提出的方法诊断准确。此外，与工业参考工具的比较也凸显了我们方法的可靠性。
{"title":"A diagnosis method for System-On-Chip","authors":"Y. Benabboud, A. Bosio1, O. Riew","doi":"10.1109/RME.2009.5201373","DOIUrl":"https://doi.org/10.1109/RME.2009.5201373","url":null,"abstract":"This paper presents a diagnosis method targeting System-On-Chip (SoC). We first show the complexity and the issues related to the diagnosis of SoC. Then we propose a diagnosis approach based on fault simulation performed in two phases, (i) a fault localization phase and (ii) a fault model allocation phase. The fault localization phase peovides a set of suspected lines able to explain the observed errors. The fault model allocation phase associates a set of fault models on each suspected line. The main advantages of this approach are that the fault localization phase is fault model independent, and that the fault model allocation phase is able to deal with several fault models at a time (static and dynamic). Experimental results show the diagnosis accuracy, in terms of absolute number of suspects, of the proposed approach. Moreover, a comparison with an industrial reference tool highlights the reliability of our approach.","PeriodicalId":245992,"journal":{"name":"2009 Ph.D. Research in Microelectronics and Electronics","volume":"84 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130161213","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-12DOI: 10.1109/RME.2009.5201328
C. Patauner, W. Pribyl, A. Marchioro
This paper presents a data compression algorithm to be used for data coming from the digitization of signals from particle physics detectors. Modern detectors in high energy physics experiments produce a huge amount of information. Therefore, efficient data reduction methods right at the front end are required to reduce the amount of data to be transmitted and stored. The data compression algorithm proposed in this paper is based on a combination of vector quantization and Huffman coding and is a lossless compression method. This compression algorithm is designed to be implemented in a new front end ASIC for amplification and digitization of signals in TPC detectors. The performance of the described compression method is presented by using a set of measured data from the ALICE TPC recording cosmic rays at CERN. The compression method is compared with the simpler arithmetic coding and Huffman coding. The obtained results show that a compression factor of 2 can be obtained on relevant data. The compression method results in a reduction better than what predicted by the simple entropy of the used data set. An implementation proposal is given and the required memory requirements for an ASIC are estimated.
{"title":"A lossless data compression method for an application in high energy physics","authors":"C. Patauner, W. Pribyl, A. Marchioro","doi":"10.1109/RME.2009.5201328","DOIUrl":"https://doi.org/10.1109/RME.2009.5201328","url":null,"abstract":"This paper presents a data compression algorithm to be used for data coming from the digitization of signals from particle physics detectors. Modern detectors in high energy physics experiments produce a huge amount of information. Therefore, efficient data reduction methods right at the front end are required to reduce the amount of data to be transmitted and stored. The data compression algorithm proposed in this paper is based on a combination of vector quantization and Huffman coding and is a lossless compression method. This compression algorithm is designed to be implemented in a new front end ASIC for amplification and digitization of signals in TPC detectors. The performance of the described compression method is presented by using a set of measured data from the ALICE TPC recording cosmic rays at CERN. The compression method is compared with the simpler arithmetic coding and Huffman coding. The obtained results show that a compression factor of 2 can be obtained on relevant data. The compression method results in a reduction better than what predicted by the simple entropy of the used data set. An implementation proposal is given and the required memory requirements for an ASIC are estimated.","PeriodicalId":245992,"journal":{"name":"2009 Ph.D. Research in Microelectronics and Electronics","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130267161","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-12DOI: 10.1109/RME.2009.5201353
G. M. Lazzerini, S. Surdo, G. Barillaro
In this work an original approach for the fabrication of the mechanical part of the Millipede, a MEMS-based scanning-probe data storage system, is reported. It allows the integration of both mechanical and electronic parts on the same wafer, by using CMOS-compatible processes. The proposed approach is based on the selective etching of p-type silicon, used as a sacrificial layer, with respect to n-type silicon, which is exploited as structural material (selective p-to-n electropolishing). Experimental results on chips fabricated by using the BCD6 process of STMicroelectronics demonstrate the feasibility of using this approach for the fabrication of freestanding n-type silicon cantilevers by selective etching of the ptype substrates.
{"title":"A new approach for CMOS-compatible fabrication of cantilever/tip systems for probe-storage applications","authors":"G. M. Lazzerini, S. Surdo, G. Barillaro","doi":"10.1109/RME.2009.5201353","DOIUrl":"https://doi.org/10.1109/RME.2009.5201353","url":null,"abstract":"In this work an original approach for the fabrication of the mechanical part of the Millipede, a MEMS-based scanning-probe data storage system, is reported. It allows the integration of both mechanical and electronic parts on the same wafer, by using CMOS-compatible processes. The proposed approach is based on the selective etching of p-type silicon, used as a sacrificial layer, with respect to n-type silicon, which is exploited as structural material (selective p-to-n electropolishing). Experimental results on chips fabricated by using the BCD6 process of STMicroelectronics demonstrate the feasibility of using this approach for the fabrication of freestanding n-type silicon cantilevers by selective etching of the ptype substrates.","PeriodicalId":245992,"journal":{"name":"2009 Ph.D. Research in Microelectronics and Electronics","volume":"2015 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133194322","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-12DOI: 10.1109/RME.2009.5201356
T. D. Werth, Lei Liao, R. Wunderlich
In the design process of integrated DC/DC converters it is desirable to assess as many critical design parameters and parasitic effects by simulation as possible as the control loop is hard to tune after fabrication. In this work, switch conduction loss of an integrated, synchronous buck converter is identified to have significant influence on control loop dynamics. Thus, an equivalent small-signal model for the open loop frequency response accounting for switch conduction loss is developed. Finally, the model is validated against the frequency response obtained by periodic stability analysis which can account for parasitic effects and loading. Very good agreement between the extended model and the results obtained from periodic stability analysis is obtained. The method and model presented in this work help to compensate DC/DC converters more effectively.
{"title":"An accurate model for PWM mode buck converter stability analysis comprising switch conduction loss","authors":"T. D. Werth, Lei Liao, R. Wunderlich","doi":"10.1109/RME.2009.5201356","DOIUrl":"https://doi.org/10.1109/RME.2009.5201356","url":null,"abstract":"In the design process of integrated DC/DC converters it is desirable to assess as many critical design parameters and parasitic effects by simulation as possible as the control loop is hard to tune after fabrication. In this work, switch conduction loss of an integrated, synchronous buck converter is identified to have significant influence on control loop dynamics. Thus, an equivalent small-signal model for the open loop frequency response accounting for switch conduction loss is developed. Finally, the model is validated against the frequency response obtained by periodic stability analysis which can account for parasitic effects and loading. Very good agreement between the extended model and the results obtained from periodic stability analysis is obtained. The method and model presented in this work help to compensate DC/DC converters more effectively.","PeriodicalId":245992,"journal":{"name":"2009 Ph.D. Research in Microelectronics and Electronics","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132237032","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-12DOI: 10.1109/RME.2009.5201336
F. Stefani, A. Pennatini, A. Cefalo
This paper deals with an AC series voltage regulator for permanent magnet generators. This project is internationally patented with the publication number WO/2009/004466. Possible application contexts of the system include electrical regulation for battery-free motorbikes or small wind energy generators. The comparison with the stateof- the-art parallel architecture is discussed together with energy efficiency simulations, specific advantages and disadvantages for both the solutions. The operation principles of the proposed regulation system is explained with the help of block diagrams and two practical implementations are discussed: the first one realized entirely with analog electronics, the second one with a microcontroller. Finally several experimental measurements made on the analog prototype of the device are presented.
{"title":"AC voltage series regulator for permanent magnet generators","authors":"F. Stefani, A. Pennatini, A. Cefalo","doi":"10.1109/RME.2009.5201336","DOIUrl":"https://doi.org/10.1109/RME.2009.5201336","url":null,"abstract":"This paper deals with an AC series voltage regulator for permanent magnet generators. This project is internationally patented with the publication number WO/2009/004466. Possible application contexts of the system include electrical regulation for battery-free motorbikes or small wind energy generators. The comparison with the stateof- the-art parallel architecture is discussed together with energy efficiency simulations, specific advantages and disadvantages for both the solutions. The operation principles of the proposed regulation system is explained with the help of block diagrams and two practical implementations are discussed: the first one realized entirely with analog electronics, the second one with a microcontroller. Finally several experimental measurements made on the analog prototype of the device are presented.","PeriodicalId":245992,"journal":{"name":"2009 Ph.D. Research in Microelectronics and Electronics","volume":"63 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126218483","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-12DOI: 10.1109/RME.2009.5201337
T. Krupski, E. Hermanowicz
This paper presents novel designs of multi-output sinusoidal oscillators derived from recursive digital filter structures. Two methods to design a complex digital oscillator were developed. In the first approach we obtain the output signals as a result of using in the oscillator algorithm the desired rotation matrix elements, while in the second approach the recipe is opposite: based on the desired amplitudes and phases of sinusoidal signals we obtain the rotation matrix elements. The common feature of these two strategies is the rotation matrix ability to unify various complex oscillator structures. Detailed analysis of the complex oscillators yielded to design multi-output sinusoidal oscillators with waveforms of specified amplitudes and phases. The three-phase oscillator proposed here can be implemented with the aid of four multipliers having two different coefficient values, three adders, and three delay elements.
{"title":"Novel designs of recursive discrete-time sinusoidal oscillators","authors":"T. Krupski, E. Hermanowicz","doi":"10.1109/RME.2009.5201337","DOIUrl":"https://doi.org/10.1109/RME.2009.5201337","url":null,"abstract":"This paper presents novel designs of multi-output sinusoidal oscillators derived from recursive digital filter structures. Two methods to design a complex digital oscillator were developed. In the first approach we obtain the output signals as a result of using in the oscillator algorithm the desired rotation matrix elements, while in the second approach the recipe is opposite: based on the desired amplitudes and phases of sinusoidal signals we obtain the rotation matrix elements. The common feature of these two strategies is the rotation matrix ability to unify various complex oscillator structures. Detailed analysis of the complex oscillators yielded to design multi-output sinusoidal oscillators with waveforms of specified amplitudes and phases. The three-phase oscillator proposed here can be implemented with the aid of four multipliers having two different coefficient values, three adders, and three delay elements.","PeriodicalId":245992,"journal":{"name":"2009 Ph.D. Research in Microelectronics and Electronics","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114635445","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-12DOI: 10.1109/RME.2009.5201339
Nadia El Mrabet, G. Di Natale, M. Flottes
Pairings permit several protocol simplifications and original scheme creation, for example Identity Based Cryptography protocols. Initially, the use of pairings did not involve any secret entry, consequently, side channel attacks were not a threat for pairing based cryptography. On the contrary, in an Identity Based Cryptographic protocol, one of the two entries to the pairing is secret. Side Channel Attacks can be therefore applied to find this secret. We realize a Differential Power Analysis(DPA) against the Miller algorithm, the central step to compute theWeil, Tate and Ate pairing. We show that the countermeasure which consist in setting the secret during a pairing computation at the first parameter is not sufficient to prevent a DPA attack.
{"title":"A practical Differential Power Analysis attack against the Miller algorithm","authors":"Nadia El Mrabet, G. Di Natale, M. Flottes","doi":"10.1109/RME.2009.5201339","DOIUrl":"https://doi.org/10.1109/RME.2009.5201339","url":null,"abstract":"Pairings permit several protocol simplifications and original scheme creation, for example Identity Based Cryptography protocols. Initially, the use of pairings did not involve any secret entry, consequently, side channel attacks were not a threat for pairing based cryptography. On the contrary, in an Identity Based Cryptographic protocol, one of the two entries to the pairing is secret. Side Channel Attacks can be therefore applied to find this secret. We realize a Differential Power Analysis(DPA) against the Miller algorithm, the central step to compute theWeil, Tate and Ate pairing. We show that the countermeasure which consist in setting the secret during a pairing computation at the first parameter is not sufficient to prevent a DPA attack.","PeriodicalId":245992,"journal":{"name":"2009 Ph.D. Research in Microelectronics and Electronics","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125601681","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-12DOI: 10.1109/RME.2009.5201330
Mustafa Taskaldiran, R. Morling, I. Kale
Turbo codes experience a significant decoding delay because of the iterative nature of the decoding algorithms, the high number of metric computations and the complexity added by the (de)interleaver. The extrinsic information is exchanged sequentially between two Soft-Input Soft-Output (SISO) decoders. Instead of this sequential process, a received frame can be divided into smaller windows to be processed in parallel. In this paper, a novel parallel processing methodology is proposed based on the previous parallel decoding techniques. A novel Contention-Free (CF) interleaver is proposed as part of the decoding architecture which allows using extrinsic Log-Likelihood Ratios (LLRs) immediately as a-priori LLRs to start the second half of the iterative turbo decoding. The simulation case studies performed in this paper show that our parallel decoding method can provide %80 time saving compared to the standard decoding and %30 time saving compared to the previous parallel decoding methods at the expense of 0.3dB Bit Error Rate (BER) performance degradation.
{"title":"Increasing the speed of parallel decoding of turbo codes","authors":"Mustafa Taskaldiran, R. Morling, I. Kale","doi":"10.1109/RME.2009.5201330","DOIUrl":"https://doi.org/10.1109/RME.2009.5201330","url":null,"abstract":"Turbo codes experience a significant decoding delay because of the iterative nature of the decoding algorithms, the high number of metric computations and the complexity added by the (de)interleaver. The extrinsic information is exchanged sequentially between two Soft-Input Soft-Output (SISO) decoders. Instead of this sequential process, a received frame can be divided into smaller windows to be processed in parallel. In this paper, a novel parallel processing methodology is proposed based on the previous parallel decoding techniques. A novel Contention-Free (CF) interleaver is proposed as part of the decoding architecture which allows using extrinsic Log-Likelihood Ratios (LLRs) immediately as a-priori LLRs to start the second half of the iterative turbo decoding. The simulation case studies performed in this paper show that our parallel decoding method can provide %80 time saving compared to the standard decoding and %30 time saving compared to the previous parallel decoding methods at the expense of 0.3dB Bit Error Rate (BER) performance degradation.","PeriodicalId":245992,"journal":{"name":"2009 Ph.D. Research in Microelectronics and Electronics","volume":"83 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132231367","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-12DOI: 10.1109/RME.2009.5201310
C. Di Carlo, A. De Marcellis, V. Stornelli, G. Ferri, D. Tiberio
In this paper we present a novel internal architecture of low-voltage and low-power positive secondgeneration current conveyor (CCII+). The proposed internal circuit topology, designed in standard CMOS technology (AMS 0.35µm), employs an n-type differential pair as input stage, while a cascoded push-pull configuration implements a very high impedance output stage. A degenerated nMOS common drain topology reduces X node impedance. The choice of internal CCII+ architecture, concerning both its stage architecture and transistor sizes, has been made in the direction of designing a quasi-ideal CCII+ in terms of parasitic components at its terminals. The developed CCII+ operates at low supply voltages of ±1V with a total power consumption of about 300µW, so it is suitable for general purpose portable applications. It has been also characterized implementing well-known applications, both in time and frequency domains, such as signal processing circuits and impedance simulators.
{"title":"A novel LV LP CMOS internal topology of CCII+ and its application in current-mode integrated circuits","authors":"C. Di Carlo, A. De Marcellis, V. Stornelli, G. Ferri, D. Tiberio","doi":"10.1109/RME.2009.5201310","DOIUrl":"https://doi.org/10.1109/RME.2009.5201310","url":null,"abstract":"In this paper we present a novel internal architecture of low-voltage and low-power positive secondgeneration current conveyor (CCII+). The proposed internal circuit topology, designed in standard CMOS technology (AMS 0.35µm), employs an n-type differential pair as input stage, while a cascoded push-pull configuration implements a very high impedance output stage. A degenerated nMOS common drain topology reduces X node impedance. The choice of internal CCII+ architecture, concerning both its stage architecture and transistor sizes, has been made in the direction of designing a quasi-ideal CCII+ in terms of parasitic components at its terminals. The developed CCII+ operates at low supply voltages of ±1V with a total power consumption of about 300µW, so it is suitable for general purpose portable applications. It has been also characterized implementing well-known applications, both in time and frequency domains, such as signal processing circuits and impedance simulators.","PeriodicalId":245992,"journal":{"name":"2009 Ph.D. Research in Microelectronics and Electronics","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131732034","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-12DOI: 10.1109/RME.2009.5201362
C. Boero, S. Carrara, G. De Micheli
Nano-biosensing provides new tools to investigate cellular differentiation and proliferation. Upon the various metabolic compounds secreted by cells during life cycles, glucose, lactate and hydrogen peroxide (H2O2) are of first interest. Nanostructured electrodes may enhance the compounds sensitivity in order to precisely detect cell cycle variation. In the present paper, the detection with electrodes nanostructured by using Multi- Walled Carbon Nanotubes (MWCNT) was investigated in order to develop an amperometric biosensor. Good improvement in sensitivity was obtained, suggesting that carbon nanotubes can be the right candidates to improve biosensing. The final aim of the study is the development of a bio-chip, which can be integrated in Petri dishes for automatic stem cell culture monitoring.
{"title":"Sensitivity enhancement by carbon nanotubes: Applications to stem cell cultures monitoring","authors":"C. Boero, S. Carrara, G. De Micheli","doi":"10.1109/RME.2009.5201362","DOIUrl":"https://doi.org/10.1109/RME.2009.5201362","url":null,"abstract":"Nano-biosensing provides new tools to investigate cellular differentiation and proliferation. Upon the various metabolic compounds secreted by cells during life cycles, glucose, lactate and hydrogen peroxide (H2O2) are of first interest. Nanostructured electrodes may enhance the compounds sensitivity in order to precisely detect cell cycle variation. In the present paper, the detection with electrodes nanostructured by using Multi- Walled Carbon Nanotubes (MWCNT) was investigated in order to develop an amperometric biosensor. Good improvement in sensitivity was obtained, suggesting that carbon nanotubes can be the right candidates to improve biosensing. The final aim of the study is the development of a bio-chip, which can be integrated in Petri dishes for automatic stem cell culture monitoring.","PeriodicalId":245992,"journal":{"name":"2009 Ph.D. Research in Microelectronics and Electronics","volume":"82 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122499345","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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