Pub Date : 2016-09-01DOI: 10.1109/ESSCIRC.2016.7598256
Jinmook Lee, Seongwook Park, Injoon Hong, H. Yoo
A low-power and high-speed speech enhancement processor for speech enhancement of noisy inputs is proposed to realize the robust speech recognition in smart glasses. It has 3 key schemes: multi-modal speech selection, look-up table based non-linear approximation circuits, and speech detection controlled dynamic clock gating. The multi-modal speech selection scheme uses three parameters to enhance the limited accuracy of the previous uni-modal user speech selection up to 98.1%. The non-linear function approximation circuit accelerates the throughput of the speech enhancement by 10.7×. The speech detection controlled clock gating reduces the redundant power consumption by 51% when there is no user voice. The proposed speech enhancement processor achieves 1.6Msamples/s throughput and 8.3mW average power consumption with the 98.1% true positive rate of speech selection in 65nm CMOS process.
{"title":"An 8.3mW 1.6Msamples/s multi-modal event-driven speech enhancement processor for robust speech recognition in smart glasses","authors":"Jinmook Lee, Seongwook Park, Injoon Hong, H. Yoo","doi":"10.1109/ESSCIRC.2016.7598256","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2016.7598256","url":null,"abstract":"A low-power and high-speed speech enhancement processor for speech enhancement of noisy inputs is proposed to realize the robust speech recognition in smart glasses. It has 3 key schemes: multi-modal speech selection, look-up table based non-linear approximation circuits, and speech detection controlled dynamic clock gating. The multi-modal speech selection scheme uses three parameters to enhance the limited accuracy of the previous uni-modal user speech selection up to 98.1%. The non-linear function approximation circuit accelerates the throughput of the speech enhancement by 10.7×. The speech detection controlled clock gating reduces the redundant power consumption by 51% when there is no user voice. The proposed speech enhancement processor achieves 1.6Msamples/s throughput and 8.3mW average power consumption with the 98.1% true positive rate of speech selection in 65nm CMOS process.","PeriodicalId":246471,"journal":{"name":"ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122132375","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-09-01DOI: 10.1109/ESSCIRC.2016.7598276
Dongsheng Yang, W. Deng, Bangan Liu, T. Siriburanon, K. Okada, A. Matsuzawa
This paper presents an LC-DCO based synthesizable injection-locked all-digital phase-locked loop. The superior noise performance of the LC-DCO enables the proposed synthesizable PLL to achieve top performance among the existing designs. Fabricated in a 65nm digital CMOS process, the chip occupies a core area of 0.12mm2. The measured integrated jitter is 0.142ps at a carrier of 3.0GHz while consuming a power of 4.6mW under 1V power supply. It achieves a figure of merit (FoM) of -250.3dB, which is the best for the synthesized PLL so far to the best knowledge of the authors.
{"title":"An LC-DCO based synthesizable injection-locked PLL with an FoM of −250.3dB","authors":"Dongsheng Yang, W. Deng, Bangan Liu, T. Siriburanon, K. Okada, A. Matsuzawa","doi":"10.1109/ESSCIRC.2016.7598276","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2016.7598276","url":null,"abstract":"This paper presents an LC-DCO based synthesizable injection-locked all-digital phase-locked loop. The superior noise performance of the LC-DCO enables the proposed synthesizable PLL to achieve top performance among the existing designs. Fabricated in a 65nm digital CMOS process, the chip occupies a core area of 0.12mm2. The measured integrated jitter is 0.142ps at a carrier of 3.0GHz while consuming a power of 4.6mW under 1V power supply. It achieves a figure of merit (FoM) of -250.3dB, which is the best for the synthesized PLL so far to the best knowledge of the authors.","PeriodicalId":246471,"journal":{"name":"ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122651881","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-09-01DOI: 10.1109/ESSCIRC.2016.7598341
Kwanyeob Chae, JongRyun Choi, Shinyoung Yi, Won Lee, Sanghoon Joo, Hyun‐Ho Kim, H. Yi, Y. Nam, J.I. Choi, Sanghune Park, Sanghyun Lee
This paper presents a 4.4Gbps/pin all-digital LPDDR4 PHY with a bit-slice architecture in 10nm FinFET process technology. The proposed bit-slice architecture includes new I/O structure for area reduction without any off-chip performance degradation and digital duty-tuning capability to maximize the valid window margin, which contributes to low voltage operation in memory interface system. The test chip in 10nm FinFET technology demonstrated stable 4.4Gbps memory access with 112ps valid window margin (49% UI) at 690mV. The implemented 16-bit LPDDR4 PHY occupies only 0.57 mm2 including a PLL.
{"title":"A 690mV 4.4Gbps/pin all-digital LPDDR4 PHY in 10nm FinFET technology","authors":"Kwanyeob Chae, JongRyun Choi, Shinyoung Yi, Won Lee, Sanghoon Joo, Hyun‐Ho Kim, H. Yi, Y. Nam, J.I. Choi, Sanghune Park, Sanghyun Lee","doi":"10.1109/ESSCIRC.2016.7598341","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2016.7598341","url":null,"abstract":"This paper presents a 4.4Gbps/pin all-digital LPDDR4 PHY with a bit-slice architecture in 10nm FinFET process technology. The proposed bit-slice architecture includes new I/O structure for area reduction without any off-chip performance degradation and digital duty-tuning capability to maximize the valid window margin, which contributes to low voltage operation in memory interface system. The test chip in 10nm FinFET technology demonstrated stable 4.4Gbps memory access with 112ps valid window margin (49% UI) at 690mV. The implemented 16-bit LPDDR4 PHY occupies only 0.57 mm2 including a PLL.","PeriodicalId":246471,"journal":{"name":"ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122870361","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-09-01DOI: 10.1109/ESSCIRC.2016.7598324
M. Crescentini, M. Biondi, M. Bennati, P. Alberti, G. Luciani, C. Tamburini, Matteo Pizzotti, A. Romani, M. Tartagni, David E. Bellasi, D. Rossi, L. Benini, M. Marchesi, D. Cristaudo, R. Canegallo
Wide-bandwidth lossless current sensors are critical in numerous applications, from current monitoring in DC-DC converters to non-invasive load monitoring. CMOS Hall sensor is a low-cost solution for current sensing and can be easily integrated as part of mixed-signal system-on-chips (SoCs). State-of-the-art CMOS Hall sensors offer only limited acquisition bandwidths of a few hundred kHz. This paper presents a 1 MHz Hall current sensor SoC integrating a broadband CMOS Hall sensor, two 2 MS/s ADCs and a multi-mode digital compressive sensing encoder for data rate reduction. The complete SoC is implemented in a STM 0.16 μm BCD technology, and occupies 16 mm2 while consuming less than 94 mW at 1.8 V.
{"title":"A 2 MS/s 10A Hall current sensor SoC with digital compressive sensing encoder in 0.16 µm BCD","authors":"M. Crescentini, M. Biondi, M. Bennati, P. Alberti, G. Luciani, C. Tamburini, Matteo Pizzotti, A. Romani, M. Tartagni, David E. Bellasi, D. Rossi, L. Benini, M. Marchesi, D. Cristaudo, R. Canegallo","doi":"10.1109/ESSCIRC.2016.7598324","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2016.7598324","url":null,"abstract":"Wide-bandwidth lossless current sensors are critical in numerous applications, from current monitoring in DC-DC converters to non-invasive load monitoring. CMOS Hall sensor is a low-cost solution for current sensing and can be easily integrated as part of mixed-signal system-on-chips (SoCs). State-of-the-art CMOS Hall sensors offer only limited acquisition bandwidths of a few hundred kHz. This paper presents a 1 MHz Hall current sensor SoC integrating a broadband CMOS Hall sensor, two 2 MS/s ADCs and a multi-mode digital compressive sensing encoder for data rate reduction. The complete SoC is implemented in a STM 0.16 μm BCD technology, and occupies 16 mm2 while consuming less than 94 mW at 1.8 V.","PeriodicalId":246471,"journal":{"name":"ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference","volume":"247 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122923521","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-09-01DOI: 10.1109/ESSCIRC.2016.7598321
M. Houdebine, E. Chataigner, R. Boulestin, C. Grundrich, D. Thevenet, S. Pruvost, H. Sherry, F. Colmagro, F. Bailleul, S. Dedieu
This paper presents a fully integrated and spur-free fractional frequency synthesizer based on a low noise 42.5-GHz SiGe quad-core VCO locked on a standard 40-MHz crystal unit. Consequently, optimal SNR is obtained for narrow bandwidth. Reference spurs are below -80 dBc thanks to a programmable digital loop filter in the range of 0.5 kHz to 50 kHz. The PLL architecture digitally controls the phase offset for beam forming and linearizes the VCO to ensure constant cut-off frequency and optimal SNR. Contrary to two-point modulation which requires calibration, radar modulation is simply added in one point after loop filter and before VCO linearizer. These blocks - XO, PLL and frequency doubler - are packaged in a BGA substrate.
{"title":"An 85-GHz fully integrated all digital fractional frequency synthesizer for e-band backhaul and radar applications in 55-nm BiCMOS","authors":"M. Houdebine, E. Chataigner, R. Boulestin, C. Grundrich, D. Thevenet, S. Pruvost, H. Sherry, F. Colmagro, F. Bailleul, S. Dedieu","doi":"10.1109/ESSCIRC.2016.7598321","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2016.7598321","url":null,"abstract":"This paper presents a fully integrated and spur-free fractional frequency synthesizer based on a low noise 42.5-GHz SiGe quad-core VCO locked on a standard 40-MHz crystal unit. Consequently, optimal SNR is obtained for narrow bandwidth. Reference spurs are below -80 dBc thanks to a programmable digital loop filter in the range of 0.5 kHz to 50 kHz. The PLL architecture digitally controls the phase offset for beam forming and linearizes the VCO to ensure constant cut-off frequency and optimal SNR. Contrary to two-point modulation which requires calibration, radar modulation is simply added in one point after loop filter and before VCO linearizer. These blocks - XO, PLL and frequency doubler - are packaged in a BGA substrate.","PeriodicalId":246471,"journal":{"name":"ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference","volume":"25 20","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113942924","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-09-01DOI: 10.1109/ESSCIRC.2016.7598299
A. Pipino, M. Matteis, A. Pezzotta, F. Resta, S. D’Amico, A. Baschirotto
A 4th-order single-loop Follow-the-Leader-Feedback (FLFB) low-pass filter is hereby presented. The outstanding FLFB noise behavior has been exploited to release a specific power budget for linearity performance enhancement. Moreover, two pairs of complex poles are synthesized by using a single compact Active-RC cell, avoiding cascade of two or more stages (typically needed for high order filters), and relaxing this way noise power constraints. A prototype of the filter has been integrated in CMOS 0.18μm technological node, having 22.5MHz -3dB low-pass frequency. 21.5dBm in-band IIP3 and 76μVRMS input referred in-band integrated noise have been achieved. The SNR for a -40dB-THD is 69dB. The power consumption is 7mA. The efficiency of the hereby proposed technique is demonstrated by the very high Figure-of-Merit (160J-1) achieved by the FLFB filter comparing with the Active-RC filters state-of-the-art.
{"title":"A 22.5MHz 21.5dBm-IIP3 4th-Order FLFB analog filter","authors":"A. Pipino, M. Matteis, A. Pezzotta, F. Resta, S. D’Amico, A. Baschirotto","doi":"10.1109/ESSCIRC.2016.7598299","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2016.7598299","url":null,"abstract":"A 4th-order single-loop Follow-the-Leader-Feedback (FLFB) low-pass filter is hereby presented. The outstanding FLFB noise behavior has been exploited to release a specific power budget for linearity performance enhancement. Moreover, two pairs of complex poles are synthesized by using a single compact Active-RC cell, avoiding cascade of two or more stages (typically needed for high order filters), and relaxing this way noise power constraints. A prototype of the filter has been integrated in CMOS 0.18μm technological node, having 22.5MHz -3dB low-pass frequency. 21.5dBm in-band IIP3 and 76μVRMS input referred in-band integrated noise have been achieved. The SNR for a -40dB-THD is 69dB. The power consumption is 7mA. The efficiency of the hereby proposed technique is demonstrated by the very high Figure-of-Merit (160J-1) achieved by the FLFB filter comparing with the Active-RC filters state-of-the-art.","PeriodicalId":246471,"journal":{"name":"ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference","volume":"2013 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114764665","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-09-01DOI: 10.1109/ESSCIRC.2016.7598263
I. Sourikopoulos, A. Frappé, A. Cathelin, L. Clavier, A. Kaiser
This paper discusses the design and characterization of a programmable digital delay line. The core of the proposed architecture is a thyristor-type delay element featuring the capability for coarse/fine tuning without using any additional hardware. This is made possible by taking advantage of body biasing features available in 28nm FDSOI CMOS. Body biasing offers unique performance characteristics, notably a very low sensitivity to the biasing voltage. The prototype delay line was designed featuring thermometer-code multi-stage activation and gate/body biasing control. A delay range from 560ps to 16.13ns is exhibited for the delay line with a 2GS/s input stream. The unit delay cell exhibits fs/mV sensitivity combined with an order of magnitude larger delay dynamic range and an energy efficiency of only 12.5 fJ/event.
{"title":"A digital delay line with coarse/fine tuning through gate/body biasing in 28nm FDSOI","authors":"I. Sourikopoulos, A. Frappé, A. Cathelin, L. Clavier, A. Kaiser","doi":"10.1109/ESSCIRC.2016.7598263","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2016.7598263","url":null,"abstract":"This paper discusses the design and characterization of a programmable digital delay line. The core of the proposed architecture is a thyristor-type delay element featuring the capability for coarse/fine tuning without using any additional hardware. This is made possible by taking advantage of body biasing features available in 28nm FDSOI CMOS. Body biasing offers unique performance characteristics, notably a very low sensitivity to the biasing voltage. The prototype delay line was designed featuring thermometer-code multi-stage activation and gate/body biasing control. A delay range from 560ps to 16.13ns is exhibited for the delay line with a 2GS/s input stream. The unit delay cell exhibits fs/mV sensitivity combined with an order of magnitude larger delay dynamic range and an energy efficiency of only 12.5 fJ/event.","PeriodicalId":246471,"journal":{"name":"ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131628276","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-09-01DOI: 10.1109/ESSCIRC.2016.7598345
T. Toifl, M. Braendli, A. Cevrero, P. Francese, M. Kossel, L. Kull, D. Luu, C. Menolfi, T. Morf, Ilter Özkaya, Hazar Yueksel
The constantly increasing need for I/O bandwidth push electrical backplane links to data rates of 50Gb/s and above. Although board materials have improved significantly, backplane links are increasingly limited by signal attenuation while suffering from ISI, jitter, device noise and cross-talk. In this paper we summarize these limitations, and show possible directions to cope with them in order to further extend the achievable data rate.
{"title":"Design considerations for 50G+ backplane links","authors":"T. Toifl, M. Braendli, A. Cevrero, P. Francese, M. Kossel, L. Kull, D. Luu, C. Menolfi, T. Morf, Ilter Özkaya, Hazar Yueksel","doi":"10.1109/ESSCIRC.2016.7598345","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2016.7598345","url":null,"abstract":"The constantly increasing need for I/O bandwidth push electrical backplane links to data rates of 50Gb/s and above. Although board materials have improved significantly, backplane links are increasingly limited by signal attenuation while suffering from ISI, jitter, device noise and cross-talk. In this paper we summarize these limitations, and show possible directions to cope with them in order to further extend the achievable data rate.","PeriodicalId":246471,"journal":{"name":"ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130276313","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-09-01DOI: 10.1109/ESSCIRC.2016.7598314
Michael Kalcher, Daniel Gruber, D. Ponton
A circuit architecture to generate differential CMOS quadrature (I/Q) local oscillator (LO) signals from a differential input at the same frequency is presented. The phase accuracy of the proposed architecture relies on the matching of two delays and linear phase interpolation. The feasibility of this approach is demonstrated by implementing an I/Q generator covering the operating frequency range from 1 GHz to 2.6 GHz, manufactured in a 28 nm Bulk-CMOS process. The phase accuracy is better than ±3° up to 2.5 GHz and better than ±5° among the entire operating frequency region achieving a phase noise performance of -163.2 dBc/Hz at 100 MHz offset at 2 GHz with a power consumption of only 4.4 mW with a 1.1V supply.
{"title":"Self-aligned open-loop local quadrature phase generator","authors":"Michael Kalcher, Daniel Gruber, D. Ponton","doi":"10.1109/ESSCIRC.2016.7598314","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2016.7598314","url":null,"abstract":"A circuit architecture to generate differential CMOS quadrature (I/Q) local oscillator (LO) signals from a differential input at the same frequency is presented. The phase accuracy of the proposed architecture relies on the matching of two delays and linear phase interpolation. The feasibility of this approach is demonstrated by implementing an I/Q generator covering the operating frequency range from 1 GHz to 2.6 GHz, manufactured in a 28 nm Bulk-CMOS process. The phase accuracy is better than ±3° up to 2.5 GHz and better than ±5° among the entire operating frequency region achieving a phase noise performance of -163.2 dBc/Hz at 100 MHz offset at 2 GHz with a power consumption of only 4.4 mW with a 1.1V supply.","PeriodicalId":246471,"journal":{"name":"ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130680778","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-09-01DOI: 10.1109/ESSCIRC.2016.7598259
R. Thirunarayanan, D. Ruffieux, N. Scolari, C. Enz
This paper presents a low start-up latency Transmitter (TX) that can achieve FSK data rates of upto 51.4 Mb/s for deployment in duty cycled microsensor nodes. Utilizing a Phase Domain Digital Synthesizer with an FBAR frequency reference, this TX has a start-up latency of just 1.5 μs. It has been integrated in a 65nm technology and outputs upto 3 dBm power. It achieves a phase noise of -110 dBc/Hz at 1 MHz offset and has a frequency coverage of 2.17 - 2.47 GHz. The power consumption of this TX (including the Digital Baseband) varies from 15 mW at 1.2 Mb/s to 21.4 mW at 51.4 Mb/s. At peak data rate, this leads to an Duty-Cycling-Energy/bit (which takes into account the start-up energy) of 500 pJ/b for transmitting packets of length 32 bytes. Moreover, the TX incorporates a Hybrid Requantizer circuit which helps to trade off in-band noise with the spurs due to the non-linearity induced ΣΔ noise folding.
{"title":"A 51.4 Mb/s FSK transmitter employing a Phase Domain Digital Synthesizer with 1.5 µs start-up for energy efficient duty cycling","authors":"R. Thirunarayanan, D. Ruffieux, N. Scolari, C. Enz","doi":"10.1109/ESSCIRC.2016.7598259","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2016.7598259","url":null,"abstract":"This paper presents a low start-up latency Transmitter (TX) that can achieve FSK data rates of upto 51.4 Mb/s for deployment in duty cycled microsensor nodes. Utilizing a Phase Domain Digital Synthesizer with an FBAR frequency reference, this TX has a start-up latency of just 1.5 μs. It has been integrated in a 65nm technology and outputs upto 3 dBm power. It achieves a phase noise of -110 dBc/Hz at 1 MHz offset and has a frequency coverage of 2.17 - 2.47 GHz. The power consumption of this TX (including the Digital Baseband) varies from 15 mW at 1.2 Mb/s to 21.4 mW at 51.4 Mb/s. At peak data rate, this leads to an Duty-Cycling-Energy/bit (which takes into account the start-up energy) of 500 pJ/b for transmitting packets of length 32 bytes. Moreover, the TX incorporates a Hybrid Requantizer circuit which helps to trade off in-band noise with the spurs due to the non-linearity induced ΣΔ noise folding.","PeriodicalId":246471,"journal":{"name":"ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference","volume":"74 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130853982","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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