Pub Date : 2016-09-01DOI: 10.1109/ESSCIRC.2016.7598300
Sang-Hoon Kim, Hoon Shin, Youngkyun Jeong, Junehee Lee, Jaehyuk Choi, J. Chun
We propose a dual-channel interface architecture that allocates high and low transition-density bit streams to two separate channels. The transmitter utilizes the stacked drivers with charge-recycling to reduce the power consumption. The DC-coupled receiver front-end circuits deal with the common-mode level variations and compensate for the channel loss. The tracked oversampling CDR which realizes fast lock acquisition below 1 baud period and low logic latency is shared by the two channels. Fabricated in a 65-nm low-power CMOS technology, the dual-channel transceiver achieves 12-Gb/s data rate while the transmitter consumes 20.43mW from a 1.2V power supply.
{"title":"A 12-Gb/s dual-channel transceiver for CMOS image sensor systems","authors":"Sang-Hoon Kim, Hoon Shin, Youngkyun Jeong, Junehee Lee, Jaehyuk Choi, J. Chun","doi":"10.1109/ESSCIRC.2016.7598300","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2016.7598300","url":null,"abstract":"We propose a dual-channel interface architecture that allocates high and low transition-density bit streams to two separate channels. The transmitter utilizes the stacked drivers with charge-recycling to reduce the power consumption. The DC-coupled receiver front-end circuits deal with the common-mode level variations and compensate for the channel loss. The tracked oversampling CDR which realizes fast lock acquisition below 1 baud period and low logic latency is shared by the two channels. Fabricated in a 65-nm low-power CMOS technology, the dual-channel transceiver achieves 12-Gb/s data rate while the transmitter consumes 20.43mW from a 1.2V power supply.","PeriodicalId":246471,"journal":{"name":"ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130524877","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-09-01DOI: 10.1109/ESSCIRC.2016.7598248
Chia-Hung Chen, Yi Zhang, G. Temes
Integrated sensor interface circuits require power-efficient high-accuracy data converters. Incremental A/D converters (IADCs) are often the best choice for these, since they can provide excellent energy efficiency, and are easily multiplexed, need only simple digital filtering, and allow low latency. By performing the conversion in multiple steps, the hardware can also be multiplexed among all steps. In this paper, the past, present and anticipated future of IADCs are described. The focus is on multi-step converters.
{"title":"History, present state-of-art and future of incremental ADCs","authors":"Chia-Hung Chen, Yi Zhang, G. Temes","doi":"10.1109/ESSCIRC.2016.7598248","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2016.7598248","url":null,"abstract":"Integrated sensor interface circuits require power-efficient high-accuracy data converters. Incremental A/D converters (IADCs) are often the best choice for these, since they can provide excellent energy efficiency, and are easily multiplexed, need only simple digital filtering, and allow low latency. By performing the conversion in multiple steps, the hardware can also be multiplexed among all steps. In this paper, the past, present and anticipated future of IADCs are described. The focus is on multi-step converters.","PeriodicalId":246471,"journal":{"name":"ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123741499","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-09-01DOI: 10.1109/ESSCIRC.2016.7598296
V. D. Smedt, J. Thoné, M. Wens
A 650 V three-phase IGBT motor driver is presented in this article. Apart from the power transistors and predrivers, also freewheeling diodes are present in the output power stage to drive inductive loads. The 15 V overdrive voltage as well as all other floating supplies are generated on-chip by means of a charge pump and cascoded current mirrors. The input signals for all switches are at ground level and level-shifted internally. Each half-bridge is able to switch at 20 kHz a 1.5 A current at 600 V and a 3 A current at 300 V. The ground connection contains a current shunt and a sense-amplifier, which can be used as a feedback signal in the BLDC control loop. The system is implemented in a 1 μm SoI technology with 650 V IGBT transistors.
本文介绍了一种650v三相IGBT电机驱动器。除了功率晶体管和预驱动器外，在输出功率级中还存在自由转动二极管来驱动感性负载。15 V的超驱动电压以及所有其他浮动电源都是通过电荷泵和级联电流镜在芯片上产生的。所有开关的输入信号都在地电平和内部电平移位。每个半桥能够在20khz时切换1.5 a的600 V电流和3a的300 V电流。接地连接包含电流分流器和感测放大器，可作为无刷直流控制回路中的反馈信号。该系统采用1 μm SoI技术，采用650 V IGBT晶体管。
{"title":"A 650 V, 3 A three-phase fully-integrated BLDC motor driver with charge pump and level shifters","authors":"V. D. Smedt, J. Thoné, M. Wens","doi":"10.1109/ESSCIRC.2016.7598296","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2016.7598296","url":null,"abstract":"A 650 V three-phase IGBT motor driver is presented in this article. Apart from the power transistors and predrivers, also freewheeling diodes are present in the output power stage to drive inductive loads. The 15 V overdrive voltage as well as all other floating supplies are generated on-chip by means of a charge pump and cascoded current mirrors. The input signals for all switches are at ground level and level-shifted internally. Each half-bridge is able to switch at 20 kHz a 1.5 A current at 600 V and a 3 A current at 300 V. The ground connection contains a current shunt and a sense-amplifier, which can be used as a feedback signal in the BLDC control loop. The system is implemented in a 1 μm SoI technology with 650 V IGBT transistors.","PeriodicalId":246471,"journal":{"name":"ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114099158","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-09-01DOI: 10.1109/ESSCIRC.2016.7598270
S. Ganta, A. Tomasini, A. Taparia, Taehee Cho, M. Kulkarni, O. Erdogan
This publication presents a cyclic A/D converter system, which can be used for column-parallel sensor readout applications. The converter system includes ADC, fully integrated ADC references, timing generator, calibration engine, and an on-chip ramp generator for complete on-chip testing. This publication solves the exaggerated issue of feed-forward transient glitches in capacitor-shared cyclic and pipelined ADCs. This publication also solves some existing issues in fully integrated references of pipeline and cyclic ADC, namely reduced voltage range, and memory effects. The area of the core cyclic ADC operating at 12 bit resolution and 2MS/s conversion rate is only 0.016mm2. The measured DNL and INL are +0.47/-0.68 LSB and +/-0.99 LSB respectively. The ADC is implemented in TSMC 55nm CMOS technology using 3.3V devices, the ADC consumes 850μW from 3.3V supply.
{"title":"A 12 bit, 2-MS/s, 0.016-mm2 column-parallel readout cyclic ADC, having 50% reduced slew rate requirement due to feed-forward spike eliminator","authors":"S. Ganta, A. Tomasini, A. Taparia, Taehee Cho, M. Kulkarni, O. Erdogan","doi":"10.1109/ESSCIRC.2016.7598270","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2016.7598270","url":null,"abstract":"This publication presents a cyclic A/D converter system, which can be used for column-parallel sensor readout applications. The converter system includes ADC, fully integrated ADC references, timing generator, calibration engine, and an on-chip ramp generator for complete on-chip testing. This publication solves the exaggerated issue of feed-forward transient glitches in capacitor-shared cyclic and pipelined ADCs. This publication also solves some existing issues in fully integrated references of pipeline and cyclic ADC, namely reduced voltage range, and memory effects. The area of the core cyclic ADC operating at 12 bit resolution and 2MS/s conversion rate is only 0.016mm2. The measured DNL and INL are +0.47/-0.68 LSB and +/-0.99 LSB respectively. The ADC is implemented in TSMC 55nm CMOS technology using 3.3V devices, the ADC consumes 850μW from 3.3V supply.","PeriodicalId":246471,"journal":{"name":"ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123872376","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-09-01DOI: 10.1109/ESSCIRC.2016.7598329
Xiyuan Tang, Long Chen, Jeonggoo Song, Nan Sun
This paper presents a 10-bit high-speed two-stage SAR ADC. Each bit uses a dedicated comparator to store its output and generate an asynchronous clock for the next comparison. By doing this, the SAR logic delay and power are significantly reduced. A modified bidirectional single-side switching technique is used to optimize the comparator speed and offset by controlling the input common mode voltage Vcm. To suppress the comparator offset mismatch induced nonlinearity, redundancy and a shared pre-amplifier are employed in the second fine stage. The pre-amplifier is implemented using a dynamic latch to avoid static power consumption. The prototype ADC in 40-nm CMOS achieves 55dB peak SNDR at 200MS/s sampling rate without any calibration. It consumes 750μW from 1.1V power supply, leading to a Walden FOM of 8.6fJ/conversion-step.
{"title":"A 10-b 750µW 200MS/s fully dynamic single-channel SAR ADC in 40nm CMOS","authors":"Xiyuan Tang, Long Chen, Jeonggoo Song, Nan Sun","doi":"10.1109/ESSCIRC.2016.7598329","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2016.7598329","url":null,"abstract":"This paper presents a 10-bit high-speed two-stage SAR ADC. Each bit uses a dedicated comparator to store its output and generate an asynchronous clock for the next comparison. By doing this, the SAR logic delay and power are significantly reduced. A modified bidirectional single-side switching technique is used to optimize the comparator speed and offset by controlling the input common mode voltage Vcm. To suppress the comparator offset mismatch induced nonlinearity, redundancy and a shared pre-amplifier are employed in the second fine stage. The pre-amplifier is implemented using a dynamic latch to avoid static power consumption. The prototype ADC in 40-nm CMOS achieves 55dB peak SNDR at 200MS/s sampling rate without any calibration. It consumes 750μW from 1.1V power supply, leading to a Walden FOM of 8.6fJ/conversion-step.","PeriodicalId":246471,"journal":{"name":"ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference","volume":"258 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116232765","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-09-01DOI: 10.1109/ESSCIRC.2016.7598311
A. Lahiri, Nitin Gupta
A 32 kHz input analog phase-locked loop (PLL) is proposed which employs: (i) active capacitor multiplication technique for reducing PLL area wherein the input parasitic capacitance from the VCO is utilized for loop-filter capacitor realization, (ii) loop-filter noise reduction technique for lowering its noise contribution on integrated jitter at PLL output and (iii) charge-pump leakage reduction technique for improving reference-spur performance. Realized in 28nm UTBB FD-SOI process, the PLL outputs 307.2MHz clock, provides an integrated jitter of 190psrms, has reference spur of -59.5dB, occupies 0.0175mm2 area and consumes 600μW power. The PLL has an FOM of -196.6dB.
{"title":"A 0.0175mm2 600µW 32kHz input 307MHz output PLL with 190psrms jitter in 28nm FD-SOI","authors":"A. Lahiri, Nitin Gupta","doi":"10.1109/ESSCIRC.2016.7598311","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2016.7598311","url":null,"abstract":"A 32 kHz input analog phase-locked loop (PLL) is proposed which employs: (i) active capacitor multiplication technique for reducing PLL area wherein the input parasitic capacitance from the VCO is utilized for loop-filter capacitor realization, (ii) loop-filter noise reduction technique for lowering its noise contribution on integrated jitter at PLL output and (iii) charge-pump leakage reduction technique for improving reference-spur performance. Realized in 28nm UTBB FD-SOI process, the PLL outputs 307.2MHz clock, provides an integrated jitter of 190psrms, has reference spur of -59.5dB, occupies 0.0175mm2 area and consumes 600μW power. The PLL has an FOM of -196.6dB.","PeriodicalId":246471,"journal":{"name":"ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122515612","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-09-01DOI: 10.1109/ESSCIRC.2016.7598336
Junmin Jiang, Yan Lu, W. Ki
A digitally controlled 2-/3-phase 6-ratio switched-capacitor (SC) DC-DC converter with low output voltage ripple and high efficiency is presented. Operating with a wide input voltage range of 1.6V to 3.3V, this SC converter can deliver a maximum power of 250mW to an output of 0.5V to 3V. Six voltage conversion ratios (VCRs) can be generated with only 2 flying capacitors by using 2- or 3-phase operation. Compared with a 2-phase SC converter, the maximum efficiency improvement is 20%. An adaptive ripple reduction scheme is proposed to achieve 4 times reduction in the output voltage ripple. Complexity of controller design is reduced by using digital synthesis and the technique is scalable. Fast loop response is achieved by synchronized hysteretic control. The converter achieves a peak efficiency of 91%.
{"title":"A digitally-controlled 2-/3-phase 6-ratio switched- capacitor DC-DC converter with adaptive ripple reduction and efficiency improvements","authors":"Junmin Jiang, Yan Lu, W. Ki","doi":"10.1109/ESSCIRC.2016.7598336","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2016.7598336","url":null,"abstract":"A digitally controlled 2-/3-phase 6-ratio switched-capacitor (SC) DC-DC converter with low output voltage ripple and high efficiency is presented. Operating with a wide input voltage range of 1.6V to 3.3V, this SC converter can deliver a maximum power of 250mW to an output of 0.5V to 3V. Six voltage conversion ratios (VCRs) can be generated with only 2 flying capacitors by using 2- or 3-phase operation. Compared with a 2-phase SC converter, the maximum efficiency improvement is 20%. An adaptive ripple reduction scheme is proposed to achieve 4 times reduction in the output voltage ripple. Complexity of controller design is reduced by using digital synthesis and the technique is scalable. Fast loop response is achieved by synchronized hysteretic control. The converter achieves a peak efficiency of 91%.","PeriodicalId":246471,"journal":{"name":"ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123586371","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-09-01DOI: 10.1109/ESSCIRC.2016.7598306
Saad Bin Nasir, Shreyas Sen, A. Raychowdhury
A hybrid (digital and analog) low dropout regulator (LDO) utilizing switched mode control is designed in 130 nm CMOS for fine grain power management, fast droop recovery and robust small signal regulation of multi-VCC digital loads. The design provides an optimal trade-off of performance and accuracy by switching between a digital and an analog control loop. The hybrid topology achieves robust small signal regulation and fast recovery from large signal transients or power state transitions. Measurements from a 130nm test-chip show Near-Threshold Voltage (NTV) operation, fast transient response of 18 ns for a load step of 10.3mA and a peak current efficiency of 98.64%.
{"title":"A 130nm hybrid low dropout regulator based on switched mode control for digital load circuits","authors":"Saad Bin Nasir, Shreyas Sen, A. Raychowdhury","doi":"10.1109/ESSCIRC.2016.7598306","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2016.7598306","url":null,"abstract":"A hybrid (digital and analog) low dropout regulator (LDO) utilizing switched mode control is designed in 130 nm CMOS for fine grain power management, fast droop recovery and robust small signal regulation of multi-VCC digital loads. The design provides an optimal trade-off of performance and accuracy by switching between a digital and an analog control loop. The hybrid topology achieves robust small signal regulation and fast recovery from large signal transients or power state transitions. Measurements from a 130nm test-chip show Near-Threshold Voltage (NTV) operation, fast transient response of 18 ns for a load step of 10.3mA and a peak current efficiency of 98.64%.","PeriodicalId":246471,"journal":{"name":"ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124890209","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-09-01DOI: 10.1109/ESSDERC.2016.7599574
G. Yeric
This paper will examine challenges in future device scaling and the implications arising from difficulties in delivering scaling benefits from devices to the circuit level, and ultimately up to the system level. These implications will serve to highlight opportunities in design-technology interactions to aid in overall system scaling.
{"title":"At the core of system scaling","authors":"G. Yeric","doi":"10.1109/ESSDERC.2016.7599574","DOIUrl":"https://doi.org/10.1109/ESSDERC.2016.7599574","url":null,"abstract":"This paper will examine challenges in future device scaling and the implications arising from difficulties in delivering scaling benefits from devices to the circuit level, and ultimately up to the system level. These implications will serve to highlight opportunities in design-technology interactions to aid in overall system scaling.","PeriodicalId":246471,"journal":{"name":"ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference","volume":"83 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124594798","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-09-01DOI: 10.1109/ESSCIRC.2016.7598241
T. Agarwal, I. Radu, P. Raghavan, G. Fiori, A. Thean, M. Heyns, W. Dehaene
In this paper, we study the impact of material parameters (i.e. effective mass and bandgap) for two-dimensional (2D) material based tunneling FETs (TFETs) on circuit level metrics. We estimate circuit level metrics (i.e delay and energy consumption) of 2D TFETs at different target OFF current (IOFF) for various combination of material parameters. To fulfill a given IOFF requirement for circuit level metrics, we study the the impact of effective mass and bandgap of the material on device level metrics such as sub-threshold slope, and IOFF. It is observed that it is imperative to have a smaller bandgap irrespective of higher effective mass of the material to achieve minimum energy-delay product (EDP) for a given delay or frequency of operation. The challenge with small bandgap materials is to curb ambipolar currents to meet target IOFF which poses a limit on the maximum performance achieved from the small bandgap material TFETs.
{"title":"Effect of material parameters on two-dimensional materials based TFETs: An energy-delay perspective","authors":"T. Agarwal, I. Radu, P. Raghavan, G. Fiori, A. Thean, M. Heyns, W. Dehaene","doi":"10.1109/ESSCIRC.2016.7598241","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2016.7598241","url":null,"abstract":"In this paper, we study the impact of material parameters (i.e. effective mass and bandgap) for two-dimensional (2D) material based tunneling FETs (TFETs) on circuit level metrics. We estimate circuit level metrics (i.e delay and energy consumption) of 2D TFETs at different target OFF current (IOFF) for various combination of material parameters. To fulfill a given IOFF requirement for circuit level metrics, we study the the impact of effective mass and bandgap of the material on device level metrics such as sub-threshold slope, and IOFF. It is observed that it is imperative to have a smaller bandgap irrespective of higher effective mass of the material to achieve minimum energy-delay product (EDP) for a given delay or frequency of operation. The challenge with small bandgap materials is to curb ambipolar currents to meet target IOFF which poses a limit on the maximum performance achieved from the small bandgap material TFETs.","PeriodicalId":246471,"journal":{"name":"ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference","volume":"90 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124618569","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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