Pub Date : 2016-09-01DOI: 10.1109/ESSCIRC.2016.7598337
N. Butzen, M. Steyaert
In this work a Multiple-Input Multiple-Output (MIMO) Switched-Capacitor (SC) converter is presented that generates Multiple DC voltages using only the parasitic capacitances already present in fully-integrated SC converters. In combination with the Scalable Parasitic Charge Redistribution technique, the presented MIMO converter can provide voltage rails for control blocks or clock generation in low-power SC converters, without any area overhead. The proposed converter only makes use of existing blocks and therefore only adds conductive losses, which means that for low output powers, efficiencies close to 100% can be achieved. A theoretical analysis of the converter is given and used to prove the efficiency of the converter compared to regular SC MIMO converters. The working principle of the proposed MIMO converter is verified with measurements, demonstrating a peak efficiency of 98.9%.
{"title":"MIMO Switched-Capacitor converter using only parasitic capacitance with Scalable Parasitic Charge Redistribution","authors":"N. Butzen, M. Steyaert","doi":"10.1109/ESSCIRC.2016.7598337","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2016.7598337","url":null,"abstract":"In this work a Multiple-Input Multiple-Output (MIMO) Switched-Capacitor (SC) converter is presented that generates Multiple DC voltages using only the parasitic capacitances already present in fully-integrated SC converters. In combination with the Scalable Parasitic Charge Redistribution technique, the presented MIMO converter can provide voltage rails for control blocks or clock generation in low-power SC converters, without any area overhead. The proposed converter only makes use of existing blocks and therefore only adds conductive losses, which means that for low output powers, efficiencies close to 100% can be achieved. A theoretical analysis of the converter is given and used to prove the efficiency of the converter compared to regular SC MIMO converters. The working principle of the proposed MIMO converter is verified with measurements, demonstrating a peak efficiency of 98.9%.","PeriodicalId":246471,"journal":{"name":"ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference","volume":"189 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133207680","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-09-01DOI: 10.1109/ESSCIRC.2016.7598234
G. Fettweis
We are at the doorstep of 5G wireless communications technology to be defined in standards and then being introduced. Besides the ever increase in data rate the difference over 4G will be defined by additional enabling connectivity. On the one hand, massive Internet of Things (IoT) will become possible. And on the other hand an infrastructure for remote controlling real and virtual objects, the Tactile Internet, will be enabled. This requires a new approach in architecting hardware/software architectures for digital processing of radio signals as well as applications. Scalability at a new level nee ds to be created to build a design infrastructure for developing the new application solutions enabled by 5G.
{"title":"5G and the future of IoT","authors":"G. Fettweis","doi":"10.1109/ESSCIRC.2016.7598234","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2016.7598234","url":null,"abstract":"We are at the doorstep of 5G wireless communications technology to be defined in standards and then being introduced. Besides the ever increase in data rate the difference over 4G will be defined by additional enabling connectivity. On the one hand, massive Internet of Things (IoT) will become possible. And on the other hand an infrastructure for remote controlling real and virtual objects, the Tactile Internet, will be enabled. This requires a new approach in architecting hardware/software architectures for digital processing of radio signals as well as applications. Scalability at a new level nee ds to be created to build a design infrastructure for developing the new application solutions enabled by 5G.","PeriodicalId":246471,"journal":{"name":"ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference","volume":"108 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133064712","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-09-01DOI: 10.1109/ESSCIRC.2016.7598334
Avishek Biswas, A. Chandrakasan
This paper presents a low-voltage, energy-efficient SRAM designed in a 28nm fully depleted SOI (FDSOI) technology. The SRAM achieves a minimum Vdd of 0.36V, while still having the area advantage by using 6T bit-cells. Dynamic forward body-biasing (DFBB) is used to improve the write margin. The proposed implementation of DFBB provides a 4.5× improvement in energy overhead compared to a conventional implementation. It also helps in reducing the switching energy for half-selected bit-lines. An average energy/bit-access of 52.5fJ has been achieved at 0.45V. Furthermore, by implementing data prediction in the read-path, up to 36% dynamic energy savings can be obtained.
{"title":"A 0.36V 128Kb 6T SRAM with energy-efficient dynamic body-biasing and output data prediction in 28nm FDSOI","authors":"Avishek Biswas, A. Chandrakasan","doi":"10.1109/ESSCIRC.2016.7598334","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2016.7598334","url":null,"abstract":"This paper presents a low-voltage, energy-efficient SRAM designed in a 28nm fully depleted SOI (FDSOI) technology. The SRAM achieves a minimum Vdd of 0.36V, while still having the area advantage by using 6T bit-cells. Dynamic forward body-biasing (DFBB) is used to improve the write margin. The proposed implementation of DFBB provides a 4.5× improvement in energy overhead compared to a conventional implementation. It also helps in reducing the switching energy for half-selected bit-lines. An average energy/bit-access of 52.5fJ has been achieved at 0.45V. Furthermore, by implementing data prediction in the read-path, up to 36% dynamic energy savings can be obtained.","PeriodicalId":246471,"journal":{"name":"ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121432450","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-09-01DOI: 10.1109/ESSCIRC.2016.7598315
Hundo Shin, R. Harjani
This paper presents a prototype analog 4-channel-I/Q polyphase-FFT filter bank (PFFB) using passive switched capacitor circuits to channelize wideband signals. Like FFTs, the proposed PFFB shares computations for low power. The PFFB allows for a longer “effective window length” than is possible in a standard FFT. This characteristic of the PFFB maintains a narrow main-lobe bandwidth combined with low side-lobe amplitudes. The passive switched capacitor structure enables high linearity and low power implementation. The measured performance of the prototype fabricated in TSMC 65nm CMOS shows >40dB side-lobe suppression, +25dBm IIP3, and 208μVrms integrated output noise for all channels at 1GS/s operation. The total power consumption for the PFFB (8-channels total) is 34.6mW (34.6pJ/conv).
{"title":"A 1GHz signal bandwidth 4-channel-I/Q polyphase-FFT filter bank","authors":"Hundo Shin, R. Harjani","doi":"10.1109/ESSCIRC.2016.7598315","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2016.7598315","url":null,"abstract":"This paper presents a prototype analog 4-channel-I/Q polyphase-FFT filter bank (PFFB) using passive switched capacitor circuits to channelize wideband signals. Like FFTs, the proposed PFFB shares computations for low power. The PFFB allows for a longer “effective window length” than is possible in a standard FFT. This characteristic of the PFFB maintains a narrow main-lobe bandwidth combined with low side-lobe amplitudes. The passive switched capacitor structure enables high linearity and low power implementation. The measured performance of the prototype fabricated in TSMC 65nm CMOS shows >40dB side-lobe suppression, +25dBm IIP3, and 208μVrms integrated output noise for all channels at 1GS/s operation. The total power consumption for the PFFB (8-channels total) is 34.6mW (34.6pJ/conv).","PeriodicalId":246471,"journal":{"name":"ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference","volume":"204 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115643793","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-09-01DOI: 10.1109/ESSCIRC.2016.7598232
Tobi Delbruckl
Conventional machine vision faces a fundamental latency-power tradeoff, where decreasing latency means increasing frame rate and power consumption. The communication by spikes in the brain provides the inspiration for developments of event-based vision sensors and processing, which could avoid this tradeoff entirely. This paper provides a personal perspective on developments of event-based vision sensors, algorithms, and applications over the period 2002–2016.
{"title":"Neuromorophic vision sensing and processing","authors":"Tobi Delbruckl","doi":"10.1109/ESSCIRC.2016.7598232","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2016.7598232","url":null,"abstract":"Conventional machine vision faces a fundamental latency-power tradeoff, where decreasing latency means increasing frame rate and power consumption. The communication by spikes in the brain provides the inspiration for developments of event-based vision sensors and processing, which could avoid this tradeoff entirely. This paper provides a personal perspective on developments of event-based vision sensors, algorithms, and applications over the period 2002–2016.","PeriodicalId":246471,"journal":{"name":"ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125489240","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-09-01DOI: 10.1109/ESSCIRC.2016.7598292
J. Constantin, Andrea Bonetti, A. Teman, T. C. Müller, Lorenz Schmid, A. Burg
This paper presents DynOR, a 32-bit 6-stage Open-RISC microprocessor with dynamic clock adjustment. To alleviate the issue of unused dynamic timing margins, the clock period of the processor is adjusted on a cycle-by-cycle level, based on the instruction types currently in flight in the pipeline. To this end, we employ a custom designed clock generation unit, capable of immediate glitch-free adjustments of the clock period over a wide range with fine granularity. Our chip measurements in 28nm FD-SOI technology show that DynOR provides an average speedup of 19% in program execution over a wide range of operating conditions, with a peak speedup for certain applications of up to 41%. Furthermore, this speedup can be traded off against energy, to reduce the chip power consumption for a typical die by up to 15%, compared to a static clocking scheme based on worst case excitation.
{"title":"DynOR: A 32-bit microprocessor in 28 nm FD-SOI with cycle-by-cycle dynamic clock adjustment","authors":"J. Constantin, Andrea Bonetti, A. Teman, T. C. Müller, Lorenz Schmid, A. Burg","doi":"10.1109/ESSCIRC.2016.7598292","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2016.7598292","url":null,"abstract":"This paper presents DynOR, a 32-bit 6-stage Open-RISC microprocessor with dynamic clock adjustment. To alleviate the issue of unused dynamic timing margins, the clock period of the processor is adjusted on a cycle-by-cycle level, based on the instruction types currently in flight in the pipeline. To this end, we employ a custom designed clock generation unit, capable of immediate glitch-free adjustments of the clock period over a wide range with fine granularity. Our chip measurements in 28nm FD-SOI technology show that DynOR provides an average speedup of 19% in program execution over a wide range of operating conditions, with a peak speedup for certain applications of up to 41%. Furthermore, this speedup can be traded off against energy, to reduce the chip power consumption for a typical die by up to 15%, compared to a static clocking scheme based on worst case excitation.","PeriodicalId":246471,"journal":{"name":"ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference","volume":"249 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121984753","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-09-01DOI: 10.1109/ESSCIRC.2016.7598285
E. Peterson, David A. Dinsmoor, D. Tyler, T. Denison
A prototype neuromuscular interface with distributed sensing and stimulation functions was developed to evaluate power isolation and maximize stimulation artifact rejection. Evaluation was performed in saline with representative stimulating and sensing electrodes. Stimulation pulses paced at 100 Hz were applied while sensing frequencies from 2.5 to 500 Hz. Two isolation topologies were evaluated, one in which a common ground connection was shared among the modules with AC-coupled power and one in which power and ground were both AC-coupled. The fully AC-coupled design provided 23 dB better common-mode rejection of stimulation artifact than the shared ground design. The effect of reference impedance between the fully isolated sense module and the saline tank was also found to significantly impact stimulation artifact rejection. These results inform system-level design for closed-loop distributed systems wherein the application necessitates concurrent stimulation and biomarker sensing functions.
{"title":"Stimulation artifact rejection in closed-loop, distributed neural interfaces","authors":"E. Peterson, David A. Dinsmoor, D. Tyler, T. Denison","doi":"10.1109/ESSCIRC.2016.7598285","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2016.7598285","url":null,"abstract":"A prototype neuromuscular interface with distributed sensing and stimulation functions was developed to evaluate power isolation and maximize stimulation artifact rejection. Evaluation was performed in saline with representative stimulating and sensing electrodes. Stimulation pulses paced at 100 Hz were applied while sensing frequencies from 2.5 to 500 Hz. Two isolation topologies were evaluated, one in which a common ground connection was shared among the modules with AC-coupled power and one in which power and ground were both AC-coupled. The fully AC-coupled design provided 23 dB better common-mode rejection of stimulation artifact than the shared ground design. The effect of reference impedance between the fully isolated sense module and the saline tank was also found to significantly impact stimulation artifact rejection. These results inform system-level design for closed-loop distributed systems wherein the application necessitates concurrent stimulation and biomarker sensing functions.","PeriodicalId":246471,"journal":{"name":"ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123303722","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-09-01DOI: 10.1109/ESSCIRC.2016.7598335
Zhao Chuan Lee, M. S. M. Siddiqui, Z. Kong, T. T. Kim
This paper presents circuit techniques that support on-chip SRAM dynamic reliability management to prevent half-selected cell stability failure due to Bias Temperature Instability (BTI) degradation. The proposed techniques monitor the BTI degradation in SRAM cells through a replica row and adjust the WWL voltage level with the assist of a two-phase write operation, where the WWL voltage level is divided into two phases to maintain the half-selected cell stability with BTI without compromising other circuit parameters. Test chip measurement shows that the half-selected cell stability failure is reduced significantly with the proposed techniques at a 10% area and 3.42% power overheads in 28-nm FDSOI 16kb SRAM.
{"title":"An 8T SRAM with BTI-Aware Stability Monitor and two-phase write operation for cell stability improvement in 28-nm FDSOI","authors":"Zhao Chuan Lee, M. S. M. Siddiqui, Z. Kong, T. T. Kim","doi":"10.1109/ESSCIRC.2016.7598335","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2016.7598335","url":null,"abstract":"This paper presents circuit techniques that support on-chip SRAM dynamic reliability management to prevent half-selected cell stability failure due to Bias Temperature Instability (BTI) degradation. The proposed techniques monitor the BTI degradation in SRAM cells through a replica row and adjust the WWL voltage level with the assist of a two-phase write operation, where the WWL voltage level is divided into two phases to maintain the half-selected cell stability with BTI without compromising other circuit parameters. Test chip measurement shows that the half-selected cell stability failure is reduced significantly with the proposed techniques at a 10% area and 3.42% power overheads in 28-nm FDSOI 16kb SRAM.","PeriodicalId":246471,"journal":{"name":"ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131243727","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-09-01DOI: 10.1109/ESSCIRC.2016.7598231
Ahmad Bahai
Ultra-low power systems and circuits are increasingly pivotal for many fast growing segments of semiconductor industry. A confluence of multiple technologies has brought the promising opportunity for pervasive connectivity of people and things closer than ever. Innovative system partitioning, advances in analog and digital circuit design, modern embedded sensing technologies and intelligent power management are critical to achieve the ambitious ultra-low power targets of the modern sensor nodes. In this review, we address some of the challenges and opportunities of ultra-low power system and circuit design.
{"title":"Ultra-low energy systems: Analog to information","authors":"Ahmad Bahai","doi":"10.1109/ESSCIRC.2016.7598231","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2016.7598231","url":null,"abstract":"Ultra-low power systems and circuits are increasingly pivotal for many fast growing segments of semiconductor industry. A confluence of multiple technologies has brought the promising opportunity for pervasive connectivity of people and things closer than ever. Innovative system partitioning, advances in analog and digital circuit design, modern embedded sensing technologies and intelligent power management are critical to achieve the ambitious ultra-low power targets of the modern sensor nodes. In this review, we address some of the challenges and opportunities of ultra-low power system and circuit design.","PeriodicalId":246471,"journal":{"name":"ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132498897","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-09-01DOI: 10.1109/ESSCIRC.2016.7598344
N. Pinckney, D. Sylvester, D. Blaauw
On-chip supply boosting can quickly restore a microprocessor core's power rail from near-threshold to super-threshold when critical code sections are encountered. We demonstrate a flip-chip implementation of a supply boosting technique, called Shortstop, which uses a transient supply rail and leverages the parasitic and intentional inductance of a package. To address package parasitic variation, an automatic tuning algorithm is shown. A 7.9mm2, 40nm CMOS prototype chip is attached to a custom ball grid array substrate, with integrated in-package inductors. Shortstop boosts a 2.7mm2 core from 0.5V to 0.75V in 14ns with only 27mV of droop on a shared 0.8V supply rail, marking a 57% faster transition with 67% lower supply noise than a dual-supply PMOS header design.
{"title":"Supply boosting for high-performance processors in flip-chip packages","authors":"N. Pinckney, D. Sylvester, D. Blaauw","doi":"10.1109/ESSCIRC.2016.7598344","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2016.7598344","url":null,"abstract":"On-chip supply boosting can quickly restore a microprocessor core's power rail from near-threshold to super-threshold when critical code sections are encountered. We demonstrate a flip-chip implementation of a supply boosting technique, called Shortstop, which uses a transient supply rail and leverages the parasitic and intentional inductance of a package. To address package parasitic variation, an automatic tuning algorithm is shown. A 7.9mm2, 40nm CMOS prototype chip is attached to a custom ball grid array substrate, with integrated in-package inductors. Shortstop boosts a 2.7mm2 core from 0.5V to 0.75V in 14ns with only 27mV of droop on a shared 0.8V supply rail, marking a 57% faster transition with 67% lower supply noise than a dual-supply PMOS header design.","PeriodicalId":246471,"journal":{"name":"ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115104218","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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