Pub Date : 2016-09-01DOI: 10.1109/ESSCIRC.2016.7598269
Jianyu Zhong, Yan Zhu, Chi-Hang Chan, Sai-Weng Sin, U. Seng-Pan, R. Martins
This paper presents a 12b 180 MS/s partial-interleaving Pipelined-SAR analog-to-digital converter (ADC). The 1st-stage is implemented with a 2b/cycle SAR ADC for high speed, where we propose a merged-residue-DAC technique to improve the noise performance. The capacitor pre-charging in conventional 2b/cycle operation wastes settling time and switching energy, while with this design approach the switching procedure is optimized to avoid the pre-charging for tri-level reference generation. The prototype ADC fabricated in 65nm CMOS achieves a SNDR of 63.8dB @DC input with 6mW power dissipation from a 1.2V supply, leading to a FoM @DC of 26.3 fJ/conv.-step.
{"title":"A 12b 180MS/s 0.068mm2 pipelined-SAR ADC with merged-residue DAC for noise reduction","authors":"Jianyu Zhong, Yan Zhu, Chi-Hang Chan, Sai-Weng Sin, U. Seng-Pan, R. Martins","doi":"10.1109/ESSCIRC.2016.7598269","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2016.7598269","url":null,"abstract":"This paper presents a 12b 180 MS/s partial-interleaving Pipelined-SAR analog-to-digital converter (ADC). The 1st-stage is implemented with a 2b/cycle SAR ADC for high speed, where we propose a merged-residue-DAC technique to improve the noise performance. The capacitor pre-charging in conventional 2b/cycle operation wastes settling time and switching energy, while with this design approach the switching procedure is optimized to avoid the pre-charging for tri-level reference generation. The prototype ADC fabricated in 65nm CMOS achieves a SNDR of 63.8dB @DC input with 6mW power dissipation from a 1.2V supply, leading to a FoM @DC of 26.3 fJ/conv.-step.","PeriodicalId":246471,"journal":{"name":"ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134286301","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-09-01DOI: 10.1109/ESSCIRC.2016.7598244
Masahiro Tanaka, Kota Tsurumi, T. Ishii, K. Takeuchi
For 1.0V operation NAND flash memory, heterogeneously integrated voltage generator is proposed and experimentally demonstrated. The proposed 2-stage boost converter uses high voltage (HV) transistors of standard CMOS process as the 1st stage and HV transistors of NAND flash process as the 2nd stage. The intermediate load capacitance is adaptively adjusted according to the number of NAND flash chips operating simultaneously. As a result, 89% ramp-up time decrease and about 15% chip cost reduction is achieved.
{"title":"Heterogeneously integrated program voltage generator for 1.0V operation NAND flash with best mix & match of standard CMOS process and NAND flash process","authors":"Masahiro Tanaka, Kota Tsurumi, T. Ishii, K. Takeuchi","doi":"10.1109/ESSCIRC.2016.7598244","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2016.7598244","url":null,"abstract":"For 1.0V operation NAND flash memory, heterogeneously integrated voltage generator is proposed and experimentally demonstrated. The proposed 2-stage boost converter uses high voltage (HV) transistors of standard CMOS process as the 1st stage and HV transistors of NAND flash process as the 2nd stage. The intermediate load capacitance is adaptively adjusted according to the number of NAND flash chips operating simultaneously. As a result, 89% ramp-up time decrease and about 15% chip cost reduction is achieved.","PeriodicalId":246471,"journal":{"name":"ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133142852","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-09-01DOI: 10.1109/ESSCIRC.2016.7598291
Hans Reyserhove, W. Dehaene
This paper presents a 16.07pJ/cycle 31MHz ARM Cortex M0 core in 40nm CMOS. The system was designed using differential transmission gates in an extended standard cell flow, taking into account variability, speed, energy and scalability. Extensive measurements over a range of 25 dies show it achieves sub-20pJ/cycle operation in a 330-500mV 10-48MHz range and is fully functional down to 190mV. Compared to state-of-the-art, a 40× speed and 4.8× EDP improvement is reported at the MEP. With low variation (σ/μ) on the clock frequency (3.5% at the MEP) and energy consumption (18.2% at the MEP), it combines the low variability, high speed and low energy of full custom work with the ease and design time of standard cell design.
本文提出了一个16.07pJ/cycle的40nm CMOS 31MHz ARM Cortex M0内核。考虑到可变性、速度、能量和可扩展性，该系统在扩展的标准细胞流中使用差分传输门设计。在25个芯片范围内的广泛测量表明，它在330-500mV 10-48MHz范围内实现了低于20pj /周期的操作，并且功能齐全，低至190mV。与最先进的技术相比，MEP报告了40倍的速度和4.8倍的EDP改进。时钟频率的低变化(σ/μ)(在MEP下为3.5%)和能量消耗(在MEP下为18.2%)，它结合了全定制工作的低变化、高速度和低能量，以及标准单元设计的易用性和设计时间。
{"title":"A 16.07pJ/cycle 31MHz fully differential transmission gate logic ARM Cortex M0 core in 40nm CMOS","authors":"Hans Reyserhove, W. Dehaene","doi":"10.1109/ESSCIRC.2016.7598291","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2016.7598291","url":null,"abstract":"This paper presents a 16.07pJ/cycle 31MHz ARM Cortex M0 core in 40nm CMOS. The system was designed using differential transmission gates in an extended standard cell flow, taking into account variability, speed, energy and scalability. Extensive measurements over a range of 25 dies show it achieves sub-20pJ/cycle operation in a 330-500mV 10-48MHz range and is fully functional down to 190mV. Compared to state-of-the-art, a 40× speed and 4.8× EDP improvement is reported at the MEP. With low variation (σ/μ) on the clock frequency (3.5% at the MEP) and energy consumption (18.2% at the MEP), it combines the low variability, high speed and low energy of full custom work with the ease and design time of standard cell design.","PeriodicalId":246471,"journal":{"name":"ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference","volume":"93 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122257124","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-09-01DOI: 10.1109/ESSCIRC.2016.7598348
N. Mehta, Chen Sun, M. Wade, Sen Lin, M. Popović, V. Stojanović
A high-sensitivity, fully-differential optical receiver for high-density photonic interconnects is presented. To realize fully-differential operation, a 3-dB power splitter and SiGe photodetector are integrated with the receiver, all in a CMOS 45nm SOI process. The proposed receiver improves sensitivity by suppressing common-mode and supply noise through fully-differential (FD) operation, achieving 12Gb/s at BER <10−12 with input sensitivity of 8.6µAPP while consuming 4.3mW. To understand the effectiveness of the proposed solution, we compare it to a conventional single-ended (SE) receiver on the same test-chip. Measured sensitivity is >2× better than the closest state-of-the-art design, achieving same energy per bit at higher data-rate.
{"title":"A 12Gb/s, 8.6µApp input sensitivity, monolithic-integrated fully differential optical receiver in CMOS 45nm SOI process","authors":"N. Mehta, Chen Sun, M. Wade, Sen Lin, M. Popović, V. Stojanović","doi":"10.1109/ESSCIRC.2016.7598348","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2016.7598348","url":null,"abstract":"A high-sensitivity, fully-differential optical receiver for high-density photonic interconnects is presented. To realize fully-differential operation, a 3-dB power splitter and SiGe photodetector are integrated with the receiver, all in a CMOS 45nm SOI process. The proposed receiver improves sensitivity by suppressing common-mode and supply noise through fully-differential (FD) operation, achieving 12Gb/s at BER <10−12 with input sensitivity of 8.6µAPP while consuming 4.3mW. To understand the effectiveness of the proposed solution, we compare it to a conventional single-ended (SE) receiver on the same test-chip. Measured sensitivity is >2× better than the closest state-of-the-art design, achieving same energy per bit at higher data-rate.","PeriodicalId":246471,"journal":{"name":"ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129264397","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-09-01DOI: 10.1109/ESSCIRC.2016.7598260
Yashar Rajavi, M. Taghivand, Kamal Aggarwal, Andrew Ma, A. Poon
We present an energy harvested ultra-low power transceiver for medical applications. The proposed design is RF-powered and enables bidirectional full-duplex communication using time-division duplexing (TDD) at 1.85GHz. The transceiver achieves a data rate of 7.2Mbps in TX, and 1.8Mbps in RX. The TX consumes 54μW, while the RX consumes 9.4μW of power. The prototype was fabricated in 40nm LP CMOS and occupies 0.8mm2.
{"title":"An energy harvested ultra-low power transceiver for Internet of Medical Things","authors":"Yashar Rajavi, M. Taghivand, Kamal Aggarwal, Andrew Ma, A. Poon","doi":"10.1109/ESSCIRC.2016.7598260","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2016.7598260","url":null,"abstract":"We present an energy harvested ultra-low power transceiver for medical applications. The proposed design is RF-powered and enables bidirectional full-duplex communication using time-division duplexing (TDD) at 1.85GHz. The transceiver achieves a data rate of 7.2Mbps in TX, and 1.8Mbps in RX. The TX consumes 54μW, while the RX consumes 9.4μW of power. The prototype was fabricated in 40nm LP CMOS and occupies 0.8mm2.","PeriodicalId":246471,"journal":{"name":"ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121511389","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-09-01DOI: 10.1109/ESSCIRC.2016.7598301
Marc Erett, James Hudner, D. Carey, R. Casey, Kevin Geary, Kay Hearne, Pedro Neto, T. Mallard, V. Sooden, Mark Smyth, Y. Frans, J. Im, P. Upadhyaya, Wenfeng Zhang, Winson Lin, Bruce Xu, Ken Chang
This paper presents a flexible 0.5-16.3Gb/s serial transceiver - fabricated in 16nm FinFET CMOS - and consuming 219mW/channel at 16.3Gb/s. The transceiver is fully adaptive to cover the FPGA requirement to interface to a multitude of combinations of data-rates and standards, such as 10G KR, PCIe Gen3/4, across a range of channel loss profiles. High performance techniques employed include a fully adaptive CTLE, AGC, an 11-tap DFE, wide-band LC PLLs and a low-latency CDR+PI for high-tracking-bandwidth clock and data recovery. Low power techniques such as half-rate clocking, DFE speculation, active inductors and data-rate-binned design are employed to meet stringent power budgets. At 16.3Gb/s, the receiver has a jitter tolerance of 0.3UI at 100MHz and the transceiver achieves BER <; 10-15 with up to 28dB loss at Nyquist.
{"title":"A 0.5-16.3Gbps multi-standard serial transceiver with 219mW/channel in 16nm FinFET","authors":"Marc Erett, James Hudner, D. Carey, R. Casey, Kevin Geary, Kay Hearne, Pedro Neto, T. Mallard, V. Sooden, Mark Smyth, Y. Frans, J. Im, P. Upadhyaya, Wenfeng Zhang, Winson Lin, Bruce Xu, Ken Chang","doi":"10.1109/ESSCIRC.2016.7598301","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2016.7598301","url":null,"abstract":"This paper presents a flexible 0.5-16.3Gb/s serial transceiver - fabricated in 16nm FinFET CMOS - and consuming 219mW/channel at 16.3Gb/s. The transceiver is fully adaptive to cover the FPGA requirement to interface to a multitude of combinations of data-rates and standards, such as 10G KR, PCIe Gen3/4, across a range of channel loss profiles. High performance techniques employed include a fully adaptive CTLE, AGC, an 11-tap DFE, wide-band LC PLLs and a low-latency CDR+PI for high-tracking-bandwidth clock and data recovery. Low power techniques such as half-rate clocking, DFE speculation, active inductors and data-rate-binned design are employed to meet stringent power budgets. At 16.3Gb/s, the receiver has a jitter tolerance of 0.3UI at 100MHz and the transceiver achieves BER <; 10-15 with up to 28dB loss at Nyquist.","PeriodicalId":246471,"journal":{"name":"ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference","volume":"141 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122762204","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-09-01DOI: 10.1109/ESSCIRC.2016.7598327
Wenjuan Guo, Nan Sun
This paper presents a novel noise shaping SAR architecture that is simple, robust and low power. It is fully passive and only needs minor modification to a conventional SAR ADC. Through a passive integrator, quantization noise, comparator noise and DAC noise are shaped with a noise transfer function of (1 - 0.75z-1). Unlike conventional multi-bit delta-sigma ADCs, both the noise transfer function and the error transfer function of DAC mismatches are immune to process-voltage-temperature variations. A prototype chip is fabricated in a 0.13μm CMOS process. At 1.2V and 2MS/s, the chip consumes 61μW power. SNDR increases by 6dB and the Schreier FoM increases by 3dB with OSR doubled. At an OSR of 8, SNDR is 74dB and the Schreier FoM is 167dB.
{"title":"A 12b-ENOB 61µW noise-shaping SAR ADC with a passive integrator","authors":"Wenjuan Guo, Nan Sun","doi":"10.1109/ESSCIRC.2016.7598327","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2016.7598327","url":null,"abstract":"This paper presents a novel noise shaping SAR architecture that is simple, robust and low power. It is fully passive and only needs minor modification to a conventional SAR ADC. Through a passive integrator, quantization noise, comparator noise and DAC noise are shaped with a noise transfer function of (1 - 0.75z-1). Unlike conventional multi-bit delta-sigma ADCs, both the noise transfer function and the error transfer function of DAC mismatches are immune to process-voltage-temperature variations. A prototype chip is fabricated in a 0.13μm CMOS process. At 1.2V and 2MS/s, the chip consumes 61μW power. SNDR increases by 6dB and the Schreier FoM increases by 3dB with OSR doubled. At an OSR of 8, SNDR is 74dB and the Schreier FoM is 167dB.","PeriodicalId":246471,"journal":{"name":"ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference","volume":"74 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123119854","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-09-01DOI: 10.1109/ESSCIRC.2016.7598340
Enkhbayasgalan Gantsog, Deyu Liu, A. Apsel
This paper demonstrates an all digital fully on-chip jitter measurement circuit with sub-picosecond resolution that can be used with or without an external reference. The circuit is integrated on a CMOS chip and outputs a digital code proportional to the jitter of high speed clock signals. It achieves low error while consuming less than 0.89 mW by using a low-speed stochastic under-sampler to approximate high speed sampling. Test chips were fabricated in a 65 nm CMOS process with an active area of 0.015 mm2. The absolute jitter and period jitter of a 6 GHz test clock were measured with root mean square error of 0.102 ps and 0.308 ps, respectively.
{"title":"0.89 mW on-chip jitter-measurement circuit for high speed clock with sub-picosecond resolution","authors":"Enkhbayasgalan Gantsog, Deyu Liu, A. Apsel","doi":"10.1109/ESSCIRC.2016.7598340","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2016.7598340","url":null,"abstract":"This paper demonstrates an all digital fully on-chip jitter measurement circuit with sub-picosecond resolution that can be used with or without an external reference. The circuit is integrated on a CMOS chip and outputs a digital code proportional to the jitter of high speed clock signals. It achieves low error while consuming less than 0.89 mW by using a low-speed stochastic under-sampler to approximate high speed sampling. Test chips were fabricated in a 65 nm CMOS process with an active area of 0.015 mm2. The absolute jitter and period jitter of a 6 GHz test clock were measured with root mean square error of 0.102 ps and 0.308 ps, respectively.","PeriodicalId":246471,"journal":{"name":"ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125409981","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-09-01DOI: 10.1109/ESSCIRC.2016.7598266
Minseo Kim, U. Ha, Yongsu Lee, K. Lee, H. Yoo
An ultra-low power true random number generator (TRNG) based on sub-ranging SAR ADC is proposed. The proposed TRNG shares the coarse-ADC circuit with sub-ranging SAR ADC for area reduction. The shared coarse-ADC not only plays the role of discrete-time chaotic circuit or TRNG's entropy source but also reduces overall SAR ADC energy consumption by selectively activating the fine-SAR ADC. Also, the proposed dynamic residue amplifier and adaptive-reset comparator generate chaotic map with low power consumption. TRNG core occupies 0.0045mm2 in 0.18μm CMOS technology and consumes 82nW at 270kbps throughput with 0.6V supply. The proposed TRNG passes all NIST tests and it achieves a state-of-the-art FOM of 0.3pJ/bit.
{"title":"A 82nW chaotic-map true random number generator based on sub-ranging SAR ADC","authors":"Minseo Kim, U. Ha, Yongsu Lee, K. Lee, H. Yoo","doi":"10.1109/ESSCIRC.2016.7598266","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2016.7598266","url":null,"abstract":"An ultra-low power true random number generator (TRNG) based on sub-ranging SAR ADC is proposed. The proposed TRNG shares the coarse-ADC circuit with sub-ranging SAR ADC for area reduction. The shared coarse-ADC not only plays the role of discrete-time chaotic circuit or TRNG's entropy source but also reduces overall SAR ADC energy consumption by selectively activating the fine-SAR ADC. Also, the proposed dynamic residue amplifier and adaptive-reset comparator generate chaotic map with low power consumption. TRNG core occupies 0.0045mm2 in 0.18μm CMOS technology and consumes 82nW at 270kbps throughput with 0.6V supply. The proposed TRNG passes all NIST tests and it achieves a state-of-the-art FOM of 0.3pJ/bit.","PeriodicalId":246471,"journal":{"name":"ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123969446","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-09-01DOI: 10.1109/ESSCIRC.2016.7598293
K. Takeuchi, Masaki Shimada, T. Okagaki, K. Shibutani, K. Nii, F. Tsuchiya
We propose wear-out estimator of remaining lifetime, which consists of two types of custom ring oscillators (ROs) and cumulative stress counters only. This on-chip estimator operates independently without disruption of MCU main operations and is aimed for advanced automotive MCUs, which demand sufficient reliability and real-time response along with high performance in cutting-edge applications such as ADAS. One of the custom ROs is temperature sensitive RO, which achieves the count-up speed proportional to exp(-Ea/kT), thus enabling estimation of the accumulated electro-migration (EM) stress that the die has experienced thus far. The other RO is voltage and temperature sensitive RO, which achieves the count-up speed proportional to Vn*exp(-Ea/kT) for use in TDDB stress estimation. The test chip of the custom ROs was fabricated by using 28nm HKMG process. The measured result successfully emulates more than one order of magnitude difference between 125C and 85C EM stress and 10× combinational accentuation of TDDB stress under simultaneous high voltage and temperature.
{"title":"FEOL/BEOL wear-out estimator using stress-to-frequency conversion of voltage/temperature-sensitive ring oscillators for 28nm automotive MCUs","authors":"K. Takeuchi, Masaki Shimada, T. Okagaki, K. Shibutani, K. Nii, F. Tsuchiya","doi":"10.1109/ESSCIRC.2016.7598293","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2016.7598293","url":null,"abstract":"We propose wear-out estimator of remaining lifetime, which consists of two types of custom ring oscillators (ROs) and cumulative stress counters only. This on-chip estimator operates independently without disruption of MCU main operations and is aimed for advanced automotive MCUs, which demand sufficient reliability and real-time response along with high performance in cutting-edge applications such as ADAS. One of the custom ROs is temperature sensitive RO, which achieves the count-up speed proportional to exp(-Ea/kT), thus enabling estimation of the accumulated electro-migration (EM) stress that the die has experienced thus far. The other RO is voltage and temperature sensitive RO, which achieves the count-up speed proportional to Vn*exp(-Ea/kT) for use in TDDB stress estimation. The test chip of the custom ROs was fabricated by using 28nm HKMG process. The measured result successfully emulates more than one order of magnitude difference between 125C and 85C EM stress and 10× combinational accentuation of TDDB stress under simultaneous high voltage and temperature.","PeriodicalId":246471,"journal":{"name":"ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121841056","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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