Pub Date : 2016-09-01DOI: 10.1109/ESSCIRC.2016.7598312
M. Scholl, Ye Zhang, R. Wunderlich, S. Heinen
This paper presents an area-efficient ultra-low-power 32 kHz clock source for low power wireless communication systems using a temperature-compensated charge-pump-based digitally controlled oscillator (DCO). A highly efficient digital calibration method is proposed to achieve frequency stability over process variation and temperature drifts. This calibration method locks the DCO's output frequency to the reference clock of the wireless communication system during its active state. The introduced calibration scheme offers high jitter immunity and short locking periods overcoming frequency calibration errors for typical ultra-low-power DCO's. The circuit area of the proposed ultra-low-power clock source is 100μm × 140μm in a 130nm RF CMOS technology. In measurements the proposed ultra-low-power clock source achieves a frequency stability of 10 ppm/°C from 10 °C to 100 °C for temperature drifts of less than 1 °C/s with 80nW power consumption.
{"title":"A 80 nW, 32 kHz charge-pump based ultra low power oscillator with temperature compensation","authors":"M. Scholl, Ye Zhang, R. Wunderlich, S. Heinen","doi":"10.1109/ESSCIRC.2016.7598312","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2016.7598312","url":null,"abstract":"This paper presents an area-efficient ultra-low-power 32 kHz clock source for low power wireless communication systems using a temperature-compensated charge-pump-based digitally controlled oscillator (DCO). A highly efficient digital calibration method is proposed to achieve frequency stability over process variation and temperature drifts. This calibration method locks the DCO's output frequency to the reference clock of the wireless communication system during its active state. The introduced calibration scheme offers high jitter immunity and short locking periods overcoming frequency calibration errors for typical ultra-low-power DCO's. The circuit area of the proposed ultra-low-power clock source is 100μm × 140μm in a 130nm RF CMOS technology. In measurements the proposed ultra-low-power clock source achieves a frequency stability of 10 ppm/°C from 10 °C to 100 °C for temperature drifts of less than 1 °C/s with 80nW power consumption.","PeriodicalId":246471,"journal":{"name":"ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127172475","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-09-01DOI: 10.1109/ESSCIRC.2016.7598279
Ying Wu, M. Shahmohammadi, Yue Chen, P. Lu, R. Staszewski
We present a digital-to-time converter (DTC)-assisted fractional-N wide-bandwidth all-digital PLL (ADPLL). It employs a MASH ΔΣ time-to-digital converter (TDC) to achieve low in-band phase noise, and a wide-tuning range digitally-controlled oscillator (DCO). Fabricated in 40nm CMOS, the ADPLL consumes 10.7 mW while outputting 1.73 to 3.38 GHz (after a ÷2 division) and achieves better than -109 dBc/Hz in-band phase noise and 420fsrms integrated jitter.
{"title":"A 3.5–6.8GHz wide-bandwidth DTC-assisted fractional-N all-digital PLL with a MASH ΔΣ TDC for low in-band phase noise","authors":"Ying Wu, M. Shahmohammadi, Yue Chen, P. Lu, R. Staszewski","doi":"10.1109/ESSCIRC.2016.7598279","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2016.7598279","url":null,"abstract":"We present a digital-to-time converter (DTC)-assisted fractional-N wide-bandwidth all-digital PLL (ADPLL). It employs a MASH ΔΣ time-to-digital converter (TDC) to achieve low in-band phase noise, and a wide-tuning range digitally-controlled oscillator (DCO). Fabricated in 40nm CMOS, the ADPLL consumes 10.7 mW while outputting 1.73 to 3.38 GHz (after a ÷2 division) and achieves better than -109 dBc/Hz in-band phase noise and 420fsrms integrated jitter.","PeriodicalId":246471,"journal":{"name":"ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126740548","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-09-01DOI: 10.1109/ESSCIRC.2016.7598298
A. Barbieri, S. Pernici
A Fully Balanced Differential Difference Amplifier (FB-DDA) with Dynamic Resistive Degeneration (DRD) is presented. Thanks to this technique, the tradeoff between noise and distortion proper of classic FB-DDA is overtaken, by means of a “Smooth Transition Controlling Circuit” that guarantees low noise performances for small input levels and low distortion performances for high input levels. The circuit has been adopted as the main buffering element in a direct readout circuit for MEMS analog microphones realized in a 0.13um CMOS process performing 112dB Dynamic Range and a maximum THD of about 1.6% with a -2dBV Input Signal.
{"title":"A Differential Difference Amplifier with Dynamic Resistive Degeneration for MEMS microphones","authors":"A. Barbieri, S. Pernici","doi":"10.1109/ESSCIRC.2016.7598298","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2016.7598298","url":null,"abstract":"A Fully Balanced Differential Difference Amplifier (FB-DDA) with Dynamic Resistive Degeneration (DRD) is presented. Thanks to this technique, the tradeoff between noise and distortion proper of classic FB-DDA is overtaken, by means of a “Smooth Transition Controlling Circuit” that guarantees low noise performances for small input levels and low distortion performances for high input levels. The circuit has been adopted as the main buffering element in a direct readout circuit for MEMS analog microphones realized in a 0.13um CMOS process performing 112dB Dynamic Range and a maximum THD of about 1.6% with a -2dBV Input Signal.","PeriodicalId":246471,"journal":{"name":"ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference","volume":"148 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128729510","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-09-01DOI: 10.1109/ESSCIRC.2016.7598290
T. Kaneko, Yuya Kimura, Koji Hirose, M. Miyahara, A. Matsuzawa
A continuous-time ΔΣ ADC with a new high-linearity Gm-cell is presented. A loop filter employing a Gm-C filter is preferable to an active-RC filter with op-amps for low power consumption and a large phase margin. However, distortion caused by the Gm-cell degrades the ADC performance. A cascoded flipped voltage follower Gm-cell is proposed in order to address this problem. Simulation results reveal that the IIP3 of the proposed Gm-cell is 8 dB higher than that of the conventional Gm-cell. The 20-MHz bandwidth continuous-time ΔΣ ADC employing the proposed Gm-cell achieves 75.8dB DR, 72.4 dB SNDR and 49.9 fJ/conversion-step FoM with 6.8mW power consumption.
提出了一种具有新型高线性gm单元的连续时间ΔΣ ADC。采用Gm-C滤波器的环路滤波器优于带运放的有源rc滤波器，具有低功耗和大相位裕度。然而，由Gm-cell引起的失真会降低ADC的性能。为了解决这一问题，提出了一种级联编码翻转电压跟随器Gm-cell。仿真结果表明，该Gm-cell的IIP3比传统Gm-cell的IIP3高8db。采用该Gm-cell的20 mhz带宽连续时间ΔΣ ADC可实现75.8dB DR、72.4 dB SNDR和49.9 fJ/转换步长FoM，功耗为6.8mW。
{"title":"A 76-dB-DR 6.8-mW 20-MHz bandwidth CT ΔΣ ADC with a high-linearity Gm-C filter","authors":"T. Kaneko, Yuya Kimura, Koji Hirose, M. Miyahara, A. Matsuzawa","doi":"10.1109/ESSCIRC.2016.7598290","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2016.7598290","url":null,"abstract":"A continuous-time ΔΣ ADC with a new high-linearity Gm-cell is presented. A loop filter employing a Gm-C filter is preferable to an active-RC filter with op-amps for low power consumption and a large phase margin. However, distortion caused by the Gm-cell degrades the ADC performance. A cascoded flipped voltage follower Gm-cell is proposed in order to address this problem. Simulation results reveal that the IIP3 of the proposed Gm-cell is 8 dB higher than that of the conventional Gm-cell. The 20-MHz bandwidth continuous-time ΔΣ ADC employing the proposed Gm-cell achieves 75.8dB DR, 72.4 dB SNDR and 49.9 fJ/conversion-step FoM with 6.8mW power consumption.","PeriodicalId":246471,"journal":{"name":"ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129990558","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-09-01DOI: 10.1109/ESSCIRC.2016.7598330
Kareem Ragab, Nan Sun
A divide-and-conquer approach to address comparator offset mismatch in loop-unrolled SAR ADC is presented. Redundancy and coarse foreground calibration mitigate MSB comparators offset mismatches. A novel background calibration loop matches LSB comparators offsets to a reference comparator. The proposed scheme avoids a dedicated calibration cycle that would slow down conversion. Additionally, it ensures input common mode voltage tracking for each comparator during both calibration and normal operation, without requiring external inputs or special DAC configuration. This enabled the use of a simple bidirectional single-side switching scheme to eliminate switching logic which further boosts speed and reduces switching power. An 8b prototype ADC achieves 45dB SNDR and a Nyquist FOM of 31.3fJ/conv-step at 350MS/s in 40nm CMOS.
{"title":"A 1.4mW 8b 350MS/s loop-unrolled SAR ADC with background offset calibration in 40nm CMOS","authors":"Kareem Ragab, Nan Sun","doi":"10.1109/ESSCIRC.2016.7598330","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2016.7598330","url":null,"abstract":"A divide-and-conquer approach to address comparator offset mismatch in loop-unrolled SAR ADC is presented. Redundancy and coarse foreground calibration mitigate MSB comparators offset mismatches. A novel background calibration loop matches LSB comparators offsets to a reference comparator. The proposed scheme avoids a dedicated calibration cycle that would slow down conversion. Additionally, it ensures input common mode voltage tracking for each comparator during both calibration and normal operation, without requiring external inputs or special DAC configuration. This enabled the use of a simple bidirectional single-side switching scheme to eliminate switching logic which further boosts speed and reduces switching power. An 8b prototype ADC achieves 45dB SNDR and a Nyquist FOM of 31.3fJ/conv-step at 350MS/s in 40nm CMOS.","PeriodicalId":246471,"journal":{"name":"ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117080532","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-09-01DOI: 10.1109/ESSCIRC.2016.7598235
J. Bardyn, T. Melly, Olivier Seller, N. Sornin
This paper focusses on LPWAN segment of IoT, describing network constraints and comparing existing and upcoming solutions in unlicensed and licensed frequency bands.
{"title":"IoT: The era of LPWAN is starting now","authors":"J. Bardyn, T. Melly, Olivier Seller, N. Sornin","doi":"10.1109/ESSCIRC.2016.7598235","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2016.7598235","url":null,"abstract":"This paper focusses on LPWAN segment of IoT, describing network constraints and comparing existing and upcoming solutions in unlicensed and licensed frequency bands.","PeriodicalId":246471,"journal":{"name":"ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133555308","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-09-01DOI: 10.1109/ESSCIRC.2016.7598251
Y. Shuto, Shuu'ichirou Yamamoto, S. Sugahara
Nonvolatile power-gating (NVPG) that is a power-gating architecture employing nonvolatile retention is expected as a highly efficient energy reduction technique for high-performance microprocessors and mobile/wearable SoC devices. In this paper, the NVPG architecture for SRAM is demonstrated. A 1kb nonvolatile SRAM (NV-SRAM) array with the peripheral circuits is implemented using 65nm silicon-on-thin-buried-oxide (SOTB) technology. The energy performance of the NVPG architecture for NV-SRAM is systematically analyzed based on important circuit parameters extracted from the chip. The energy efficiency evaluated by break-even time (BET) is strongly affected by the array structure and its peripherals. The body-bias-induced leakage reduction for the peripherals is highly effective at reducing BET. The NVPG architecture with NV-SRAM would be adaptable to core/module-level power-gating of multicore processors and SoCs.
{"title":"Energy performance of nonvolatile power-gating SRAM using SOTB technology","authors":"Y. Shuto, Shuu'ichirou Yamamoto, S. Sugahara","doi":"10.1109/ESSCIRC.2016.7598251","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2016.7598251","url":null,"abstract":"Nonvolatile power-gating (NVPG) that is a power-gating architecture employing nonvolatile retention is expected as a highly efficient energy reduction technique for high-performance microprocessors and mobile/wearable SoC devices. In this paper, the NVPG architecture for SRAM is demonstrated. A 1kb nonvolatile SRAM (NV-SRAM) array with the peripheral circuits is implemented using 65nm silicon-on-thin-buried-oxide (SOTB) technology. The energy performance of the NVPG architecture for NV-SRAM is systematically analyzed based on important circuit parameters extracted from the chip. The energy efficiency evaluated by break-even time (BET) is strongly affected by the array structure and its peripherals. The body-bias-induced leakage reduction for the peripherals is highly effective at reducing BET. The NVPG architecture with NV-SRAM would be adaptable to core/module-level power-gating of multicore processors and SoCs.","PeriodicalId":246471,"journal":{"name":"ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128025304","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-09-01DOI: 10.1109/ESSCIRC.2016.7598308
A. Schindler, Benno Koeppl, Ansgar Pottbaecker, M. Zannoth, B. Wicht
In various fields, there is a growing need for electric motor drives and inductive power converters. To achieve better switching behavior and lower EME in inductive switching applications, very precise gate control of the power MOSFETs by the gate driver is required. The driver presented in this paper can operate at voltages up to 60V, and it is able to change the gate current in 10 / 15ns (rise / fall delay) within a range of 20mA to 500mA. Achieved by a class B buffer in the output stage, this enables multiple current changes in a 100ns switching transition. A dip in the output current, caused by parasitic capacitances, is reduced from 80% of the full scale current to 20% by a cascode configuration in the driver output stage. The gate voltage is clamped to 11.5V, with a precise clamping circuit to reduce RDS,on with the full gate current, but without stressing the gate oxide with any over voltage. By fully integrating this concept in 130nm HV-BiCMOS, a reduction in external components for limiting overshoot, stress and EME can be achieved.
{"title":"Gate driver with 10 / 15ns in-transition variable drive current and 60% reduced current dip","authors":"A. Schindler, Benno Koeppl, Ansgar Pottbaecker, M. Zannoth, B. Wicht","doi":"10.1109/ESSCIRC.2016.7598308","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2016.7598308","url":null,"abstract":"In various fields, there is a growing need for electric motor drives and inductive power converters. To achieve better switching behavior and lower EME in inductive switching applications, very precise gate control of the power MOSFETs by the gate driver is required. The driver presented in this paper can operate at voltages up to 60V, and it is able to change the gate current in 10 / 15ns (rise / fall delay) within a range of 20mA to 500mA. Achieved by a class B buffer in the output stage, this enables multiple current changes in a 100ns switching transition. A dip in the output current, caused by parasitic capacitances, is reduced from 80% of the full scale current to 20% by a cascode configuration in the driver output stage. The gate voltage is clamped to 11.5V, with a precise clamping circuit to reduce RDS,on with the full gate current, but without stressing the gate oxide with any over voltage. By fully integrating this concept in 130nm HV-BiCMOS, a reduction in external components for limiting overshoot, stress and EME can be achieved.","PeriodicalId":246471,"journal":{"name":"ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130526012","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-09-01DOI: 10.1109/ESSCIRC.2016.7598258
Xiaoyang Wang, J. V. D. Heuvel, Gert-Jan van Schaik, Chuang Lu, Yuming He, A. Ba, B. Busze, M. Ding, Yao-Hong Liu, Nick Winkel, Menno Wildeboer, Christian Bachmann, K. Philips
A 2.4GHz transceiver SoC, operating at minimum 0.9V, is presented as a power-efficient and cost-effective solution for the coming Internet of Things (IoT) platform. The transceiver is compliant with Bluetooth Low Energy (BLE) 4.0/4.2/5.0 PHY and 802.15.4 standards. The measured sensitivity is -93dBm at 1V, and TX output power is 1dBm. Direct battery attachment is feasible, due to the 1.5μW deep-sleep power which enables μW-range average power consumption without Low Drop-Out (LDO) regulator. The radio is fabricated in 40nm CMOS technology.
{"title":"A 0.9–1.2V supplied, 2.4GHz Bluetooth Low Energy 4.0/4.2 and 802.15.4 transceiver SoC optimized for battery life","authors":"Xiaoyang Wang, J. V. D. Heuvel, Gert-Jan van Schaik, Chuang Lu, Yuming He, A. Ba, B. Busze, M. Ding, Yao-Hong Liu, Nick Winkel, Menno Wildeboer, Christian Bachmann, K. Philips","doi":"10.1109/ESSCIRC.2016.7598258","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2016.7598258","url":null,"abstract":"A 2.4GHz transceiver SoC, operating at minimum 0.9V, is presented as a power-efficient and cost-effective solution for the coming Internet of Things (IoT) platform. The transceiver is compliant with Bluetooth Low Energy (BLE) 4.0/4.2/5.0 PHY and 802.15.4 standards. The measured sensitivity is -93dBm at 1V, and TX output power is 1dBm. Direct battery attachment is feasible, due to the 1.5μW deep-sleep power which enables μW-range average power consumption without Low Drop-Out (LDO) regulator. The radio is fabricated in 40nm CMOS technology.","PeriodicalId":246471,"journal":{"name":"ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131503571","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-09-01DOI: 10.1109/ESSCIRC.2016.7598338
D. Lutz, P. Renz, B. Wicht
The power supply is one of the major challenges for applications like internet of things IoTs and smart home. The maintenance issue of batteries and the limited power level of energy harvesting is addressed by the integrated micro power supply presented in this paper. Connected to the 120/230 Vrms mains, which is one of the most reliable energy sources and anywhere indoor available, it provides a 3.3V DC output voltage. The micro power supply consists of a fully integrated ACDC and DCDC converter with one external low voltage SMD buffer capacitor. The micro power supply is fabricated in a low cost 0.35 μm 700 V CMOS technology and covers a die size of 7.7 mm2. The use of only one external low voltage SMD capacitor, results in an extremely compact form factor. The ACDC is a direct coupled, full wave rectifier with a subsequent bipolar shunt regulator, which provides an output voltage around 17 V. The DCDC stage is a fully integrated 4:1 SC DCDC converter with an input voltage as high as 17 V and a peak efficiency of 45 %. The power supply achieves an overall output power of 3 mW, resulting in a power density of 390 μW/mm2. This exceeds prior art by a factor of 11.
{"title":"A 120/230 Vrms-to-3.3V micro power supply with a fully integrated 17V SC DCDC converter","authors":"D. Lutz, P. Renz, B. Wicht","doi":"10.1109/ESSCIRC.2016.7598338","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2016.7598338","url":null,"abstract":"The power supply is one of the major challenges for applications like internet of things IoTs and smart home. The maintenance issue of batteries and the limited power level of energy harvesting is addressed by the integrated micro power supply presented in this paper. Connected to the 120/230 Vrms mains, which is one of the most reliable energy sources and anywhere indoor available, it provides a 3.3V DC output voltage. The micro power supply consists of a fully integrated ACDC and DCDC converter with one external low voltage SMD buffer capacitor. The micro power supply is fabricated in a low cost 0.35 μm 700 V CMOS technology and covers a die size of 7.7 mm2. The use of only one external low voltage SMD capacitor, results in an extremely compact form factor. The ACDC is a direct coupled, full wave rectifier with a subsequent bipolar shunt regulator, which provides an output voltage around 17 V. The DCDC stage is a fully integrated 4:1 SC DCDC converter with an input voltage as high as 17 V and a peak efficiency of 45 %. The power supply achieves an overall output power of 3 mW, resulting in a power density of 390 μW/mm2. This exceeds prior art by a factor of 11.","PeriodicalId":246471,"journal":{"name":"ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122063048","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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