Pub Date : 2016-09-01DOI: 10.1109/ESSCIRC.2016.7598262
Takuji Miki, N. Miura, Kento Mizuta, S. Dosho, M. Nagata
This paper presents a 500MHz-BW -52.5dB-THD Voltage-to-Time Converter (VTC) in 28nm CMOS. A two-step transition inverter raises the VT conversion gain to 100ps/V which is >10× higher than a conventional current-starved inverter. The number of required inverter stages is reduced to 4 from 64, resulting in 1/8 conversion latency and thus 13.2dB THD suppression at 500MHz full Nyquist. A test-chip measurement successfully demonstrates -52.5dB THD at 500MHz without sampling-and-hold. Effective VT conversion linearity is measured to be 1ps/LSB with INL/DNL of less than +/-0.53LSB. The proposed VTC consumes 84μm2 silicon area and 0.18mW at 1GS/s.
{"title":"A 500MHz-BW −52.5dB-THD Voltage-to-Time Converter utilizing a two-step transition inverter","authors":"Takuji Miki, N. Miura, Kento Mizuta, S. Dosho, M. Nagata","doi":"10.1109/ESSCIRC.2016.7598262","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2016.7598262","url":null,"abstract":"This paper presents a 500MHz-BW -52.5dB-THD Voltage-to-Time Converter (VTC) in 28nm CMOS. A two-step transition inverter raises the VT conversion gain to 100ps/V which is >10× higher than a conventional current-starved inverter. The number of required inverter stages is reduced to 4 from 64, resulting in 1/8 conversion latency and thus 13.2dB THD suppression at 500MHz full Nyquist. A test-chip measurement successfully demonstrates -52.5dB THD at 500MHz without sampling-and-hold. Effective VT conversion linearity is measured to be 1ps/LSB with INL/DNL of less than +/-0.53LSB. The proposed VTC consumes 84μm2 silicon area and 0.18mW at 1GS/s.","PeriodicalId":246471,"journal":{"name":"ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127884385","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-09-01DOI: 10.1109/ESSCIRC.2016.7598255
Priyanka Raina, M. Tikekar, A. Chandrakasan
Camera shake is the leading cause of blur in cell-phone camera images. Removing blur requires deconvolving the blurred image with a kernel which is typically unknown and needs to be estimated from the blurred image. This kernel estimation is computationally intensive and takes several minutes on a CPU which makes it unsuitable for mobile devices. This work presents the first hardware accelerator for kernel estimation for image deblurring applications. Our approach, using a multi-resolution IRLS deconvolution engine with DFT based matrix multiplication, a high-throughput image correlator and a high-speed selective update based gradient projection solver, achieves a 78× reduction in kernel estimation runtime, and a 56× reduction in total deblurring time for a 1920×1080 image enabling quick feedback to the user. Configurability in kernel size and number of iterations gives up to 10× energy scalability, allowing the system to trade-off runtime with image quality. The test chip, fabricated in 40 nm CMOS, consumes 105 mJ for kernel estimation running at 83 MHz and 0.9 V, making it suitable for integration into mobile devices.
{"title":"An energy-scalable accelerator for blind image deblurring","authors":"Priyanka Raina, M. Tikekar, A. Chandrakasan","doi":"10.1109/ESSCIRC.2016.7598255","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2016.7598255","url":null,"abstract":"Camera shake is the leading cause of blur in cell-phone camera images. Removing blur requires deconvolving the blurred image with a kernel which is typically unknown and needs to be estimated from the blurred image. This kernel estimation is computationally intensive and takes several minutes on a CPU which makes it unsuitable for mobile devices. This work presents the first hardware accelerator for kernel estimation for image deblurring applications. Our approach, using a multi-resolution IRLS deconvolution engine with DFT based matrix multiplication, a high-throughput image correlator and a high-speed selective update based gradient projection solver, achieves a 78× reduction in kernel estimation runtime, and a 56× reduction in total deblurring time for a 1920×1080 image enabling quick feedback to the user. Configurability in kernel size and number of iterations gives up to 10× energy scalability, allowing the system to trade-off runtime with image quality. The test chip, fabricated in 40 nm CMOS, consumes 105 mJ for kernel estimation running at 83 MHz and 0.9 V, making it suitable for integration into mobile devices.","PeriodicalId":246471,"journal":{"name":"ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130453419","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-09-01DOI: 10.1109/ESSCIRC.2016.7598236
Xiaolin Lu, I. Kim, A. Xhafa, Jianwei Zhou
This paper presents the use of wireless sensor network (WSN) technologies in a newly growing application space in industrial Internet or industry 4.0. This application space focuses on factory automation and field process management that we call Machine Area Network (MAN) applications. We describe key requirements, major technical challenges and how hardware and software can be combined to address these requirements in MAN. A mechanism that allows machine-to-machine (M2M) direct data sharing using a time-synchronous network that utilizes a time-stamping approach is also presented. The paper also discusses scalability of the network and how it crosses the boundaries of media specific characteristics that enables flexible network setup. TI silicon-based Intelligent Industrial Internet sensor node platform is briefly discussed to tackle above technical challenges in MAN industrial applications.
{"title":"WSN for Machine Area Network applications","authors":"Xiaolin Lu, I. Kim, A. Xhafa, Jianwei Zhou","doi":"10.1109/ESSCIRC.2016.7598236","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2016.7598236","url":null,"abstract":"This paper presents the use of wireless sensor network (WSN) technologies in a newly growing application space in industrial Internet or industry 4.0. This application space focuses on factory automation and field process management that we call Machine Area Network (MAN) applications. We describe key requirements, major technical challenges and how hardware and software can be combined to address these requirements in MAN. A mechanism that allows machine-to-machine (M2M) direct data sharing using a time-synchronous network that utilizes a time-stamping approach is also presented. The paper also discusses scalability of the network and how it crosses the boundaries of media specific characteristics that enables flexible network setup. TI silicon-based Intelligent Industrial Internet sensor node platform is briefly discussed to tackle above technical challenges in MAN industrial applications.","PeriodicalId":246471,"journal":{"name":"ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134634247","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-09-01DOI: 10.1109/ESSCIRC.2016.7598243
Pankaj Sharma, L. Bernard, A. Bazigos, A. Magrez, L. Forró, A. Ionescu
While RF transistor amplifiers—such as the field effect transistor (FET) amplifier which leverages its transconductance for amplification—are the key enablers of signal amplification in today's wireless communication; their ability to provide amplification degrades with increasing frequencies, thereby requiring multiple amplification stages which makes the device noisy, expensive and bigger in size. Owing to their broadband amplification capabilities, reflection-type amplifiers based on negative differential resistance (NDR) devices provide means to overcome these limitations. Herein, we propose a novel reflection amplifier circuit consisting of three graphene FETs (GFETs) which leverages its unique NDR characteristics. We show through rigorous simulation and modeling that broadband amplification exceeding several hundreds of GHz should be possible for the scaled graphene circuit. In addition, both the gain and frequency of operation can be highly modulated by varying the bias in the NDR region. Finally, we provide an experimental evidence of reflection amplification in the proposed circuit.
{"title":"Reflection amplifier based on graphene","authors":"Pankaj Sharma, L. Bernard, A. Bazigos, A. Magrez, L. Forró, A. Ionescu","doi":"10.1109/ESSCIRC.2016.7598243","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2016.7598243","url":null,"abstract":"While RF transistor amplifiers—such as the field effect transistor (FET) amplifier which leverages its transconductance for amplification—are the key enablers of signal amplification in today's wireless communication; their ability to provide amplification degrades with increasing frequencies, thereby requiring multiple amplification stages which makes the device noisy, expensive and bigger in size. Owing to their broadband amplification capabilities, reflection-type amplifiers based on negative differential resistance (NDR) devices provide means to overcome these limitations. Herein, we propose a novel reflection amplifier circuit consisting of three graphene FETs (GFETs) which leverages its unique NDR characteristics. We show through rigorous simulation and modeling that broadband amplification exceeding several hundreds of GHz should be possible for the scaled graphene circuit. In addition, both the gain and frequency of operation can be highly modulated by varying the bias in the NDR region. Finally, we provide an experimental evidence of reflection amplification in the proposed circuit.","PeriodicalId":246471,"journal":{"name":"ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference","volume":"122 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133851696","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-09-01DOI: 10.1109/ESSCIRC.2016.7598294
Ben Keller, M. Cochet, B. Zimmer, Yunsup Lee, Milovan Blagojevic, Jaehwa Kwak, A. Puggelli, Stevo Bailey, P. Chiu, D. Dabbelt, Colin Schmidt, E. Alon, K. Asanović, B. Nikolić
This work presents a RISC-V system-on-chip (SoC) with integrated voltage regulation and power management implemented in 28nm FD-SOI. A fully integrated switched-capacitor DC-DC converter, coupled with an adaptive clocking system, achieves 82-89% system conversion efficiency across a wide operating range, yielding a total system efficiency of 41.8 double-precision GFLOPS/W. Measurement circuits can detect changes in processor workload and an integrated power management unit responds by adjusting the core voltage at sub-microsecond timescales. The power management system reduces the energy consumption of a synthetic benchmark by 39.8% with negligible performance penalty and 2.0% area overhead, enabling extremely fine-grained (<;1μs) adaptive voltage scaling for mobile devices.
{"title":"Sub-microsecond adaptive voltage scaling in a 28nm FD-SOI processor SoC","authors":"Ben Keller, M. Cochet, B. Zimmer, Yunsup Lee, Milovan Blagojevic, Jaehwa Kwak, A. Puggelli, Stevo Bailey, P. Chiu, D. Dabbelt, Colin Schmidt, E. Alon, K. Asanović, B. Nikolić","doi":"10.1109/ESSCIRC.2016.7598294","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2016.7598294","url":null,"abstract":"This work presents a RISC-V system-on-chip (SoC) with integrated voltage regulation and power management implemented in 28nm FD-SOI. A fully integrated switched-capacitor DC-DC converter, coupled with an adaptive clocking system, achieves 82-89% system conversion efficiency across a wide operating range, yielding a total system efficiency of 41.8 double-precision GFLOPS/W. Measurement circuits can detect changes in processor workload and an integrated power management unit responds by adjusting the core voltage at sub-microsecond timescales. The power management system reduces the energy consumption of a synthetic benchmark by 39.8% with negligible performance penalty and 2.0% area overhead, enabling extremely fine-grained (<;1μs) adaptive voltage scaling for mobile devices.","PeriodicalId":246471,"journal":{"name":"ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124485214","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-09-01DOI: 10.1109/ESSCIRC.2016.7598284
E. Pepin, J. Uehlin, D. Micheletti, S. Perlmutter, J. Rudell
A high-voltage compliant, 65nm bulk-CMOS neural stimulator front-end is presented which can interface with a wide range of electrode impedances. With bulk-CMOS compatibility, the presented design can be easily integrated on the same silicon chip with other blocks needed for implantable bidirectional neural interfaces (e.g. high-density neural recording, DSP, memory, wireless interfaces). Measurements show voltage compliance exceeding +/-10V (with 1V and 2.5V devices) when driving 50μA to 2mA biphasic stimulus through resistive and capacitive electrode models. In vivo measurement results are provided (anesthetized rat) which demonstrate the efficacy of the integrated stimulator in bidirectional neural interface applications. The stimulator front-end active die area is 2mm2. While delivering 2mA, 200μs pulse-width biphasic stimulus at 300Hz the chip consumes 9.33mW; stand-by power consumption is approximately 300μW.
{"title":"A high-voltage compliant, electrode-invariant neural stimulator front-end in 65nm bulk-CMOS","authors":"E. Pepin, J. Uehlin, D. Micheletti, S. Perlmutter, J. Rudell","doi":"10.1109/ESSCIRC.2016.7598284","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2016.7598284","url":null,"abstract":"A high-voltage compliant, 65nm bulk-CMOS neural stimulator front-end is presented which can interface with a wide range of electrode impedances. With bulk-CMOS compatibility, the presented design can be easily integrated on the same silicon chip with other blocks needed for implantable bidirectional neural interfaces (e.g. high-density neural recording, DSP, memory, wireless interfaces). Measurements show voltage compliance exceeding +/-10V (with 1V and 2.5V devices) when driving 50μA to 2mA biphasic stimulus through resistive and capacitive electrode models. In vivo measurement results are provided (anesthetized rat) which demonstrate the efficacy of the integrated stimulator in bidirectional neural interface applications. The stimulator front-end active die area is 2mm2. While delivering 2mA, 200μs pulse-width biphasic stimulus at 300Hz the chip consumes 9.33mW; stand-by power consumption is approximately 300μW.","PeriodicalId":246471,"journal":{"name":"ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131660190","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-09-01DOI: 10.1109/ESSCIRC.2016.7598351
Karim Rawy, Felix Kalathiparambil George, D. Maurath, T. T. Kim
This paper presents a novel ultra-low power maximum power point tracking (MPPT) technique with a wide tracking range. An indirect, non-interrupting and approach using a novel timing-based tracking algorithm is proposed. This reduces processing current consumption down to 3.4-μA. Moreover, the proposed tracking method is self-adaptive to various types of photo-voltaic cells and thermo-electric generators and avoids external re-configuration or change of passive components for different operation conditions. A test chip was fabricated in 65-nm CMOS technology. It can harvest energy within 0.4 V to 1.7 V with a tracking response time of less than 300 ms with the minimum supply voltage of 0.8 V. The tracking efficiency is up to 96.2 % when supplied by a PV micro-cell array using an irradiation range of 200 lux to 1000 lux.
{"title":"A time-based self-adaptive energy-harvesting MPPT with 5.1-µW power consumption and a wide tracking range of 10-µA to 1-mA","authors":"Karim Rawy, Felix Kalathiparambil George, D. Maurath, T. T. Kim","doi":"10.1109/ESSCIRC.2016.7598351","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2016.7598351","url":null,"abstract":"This paper presents a novel ultra-low power maximum power point tracking (MPPT) technique with a wide tracking range. An indirect, non-interrupting and approach using a novel timing-based tracking algorithm is proposed. This reduces processing current consumption down to 3.4-μA. Moreover, the proposed tracking method is self-adaptive to various types of photo-voltaic cells and thermo-electric generators and avoids external re-configuration or change of passive components for different operation conditions. A test chip was fabricated in 65-nm CMOS technology. It can harvest energy within 0.4 V to 1.7 V with a tracking response time of less than 300 ms with the minimum supply voltage of 0.8 V. The tracking efficiency is up to 96.2 % when supplied by a PV micro-cell array using an irradiation range of 200 lux to 1000 lux.","PeriodicalId":246471,"journal":{"name":"ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference","volume":"36 3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115253854","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-09-01DOI: 10.1109/ESSCIRC.2016.7598328
Maoqiang Liu, A. Roermund, P. Harpe
In this work, a novel DAC reset scheme for SAR ADCs is proposed, which eliminates the reset energy consumption. This reset energy consumption can be significant and is seldom optimized in low power switching schemes. The scheme can be applied to all differentially reset and switched DACs. This `swap-to-reset' operation is applied to the 2 MSBs of a 12b SAR ADC fabricated in 65nm CMOS, resulting in an energy saving of 33% for the DAC or 18% for the whole ADC. Besides swapping, rotation is also applied to the 2 MSBs of the DAC to enhance the linearity to 88dB SFDR. The SAR ADC operates at 0.8V VDD and 40kS/s, achieving an SNDR of 64.2dB and a FoM of 7.1fJ/conversion-step.
本文提出了一种新的SAR adc的DAC复位方案，消除了复位能耗。在低功率开关方案中，这种复位能耗可能是显著的，并且很少得到优化。该方案适用于所有差分复位和开关dac。这种“交换复位”操作应用于65nm CMOS制造的12b SAR ADC的2个msb，导致DAC节能33%或整个ADC节能18%。除交换外，还对DAC的2 msb进行旋转，以增强线性度至88dB SFDR。SAR ADC工作在0.8V VDD和40kS/s下，SNDR为64.2dB, FoM为7.1fJ/转换步长。
{"title":"A 7.1fJ/conv.-step 88dB-SFDR 12b SAR ADC with energy-efficient swap-to-reset","authors":"Maoqiang Liu, A. Roermund, P. Harpe","doi":"10.1109/ESSCIRC.2016.7598328","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2016.7598328","url":null,"abstract":"In this work, a novel DAC reset scheme for SAR ADCs is proposed, which eliminates the reset energy consumption. This reset energy consumption can be significant and is seldom optimized in low power switching schemes. The scheme can be applied to all differentially reset and switched DACs. This `swap-to-reset' operation is applied to the 2 MSBs of a 12b SAR ADC fabricated in 65nm CMOS, resulting in an energy saving of 33% for the DAC or 18% for the whole ADC. Besides swapping, rotation is also applied to the 2 MSBs of the DAC to enhance the linearity to 88dB SFDR. The SAR ADC operates at 0.8V VDD and 40kS/s, achieving an SNDR of 64.2dB and a FoM of 7.1fJ/conversion-step.","PeriodicalId":246471,"journal":{"name":"ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference","volume":"113 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121211547","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-09-01DOI: 10.1109/ESSCIRC.2016.7598320
Rui-Xian Wang, F. Dai
This paper presents a multi-ring coupled oscillator design that employs the common-source capacitive coupling technique to achieve improved phase noise by minimizing noise injection from tail current and adjacent rings. The proposed inductor-less ring oscillator also provides additional output phases for low noise multiphase clock generation. Implemented in a 130 nm CMOS technology, the 1.5 GHz triple-ring coupled ring oscillator achieved measured phase noise of -110.17 dBc/Hz @ 1 MHz offset, demonstrating 7 dB phase noise reduction comparing to its single-ring oscillator counterpart.
{"title":"A 1∼1.5 GHz capacitive coupled inductor-less multi-ring oscillator with improved phase noise","authors":"Rui-Xian Wang, F. Dai","doi":"10.1109/ESSCIRC.2016.7598320","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2016.7598320","url":null,"abstract":"This paper presents a multi-ring coupled oscillator design that employs the common-source capacitive coupling technique to achieve improved phase noise by minimizing noise injection from tail current and adjacent rings. The proposed inductor-less ring oscillator also provides additional output phases for low noise multiphase clock generation. Implemented in a 130 nm CMOS technology, the 1.5 GHz triple-ring coupled ring oscillator achieved measured phase noise of -110.17 dBc/Hz @ 1 MHz offset, demonstrating 7 dB phase noise reduction comparing to its single-ring oscillator counterpart.","PeriodicalId":246471,"journal":{"name":"ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121212217","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-09-01DOI: 10.1109/ESSCIRC.2016.7598304
Hazar Yueksel, M. Braendli, A. Burg, G. Cherubini, R. Cideciyan, P. Francese, S. Furrer, M. Kossel, L. Kull, D. Luu, C. Menolfi, T. Morf, T. Toifl
The implementation of a digital four-level pulse-amplitude-modulation reduced-state sliding-block Viterbi detector (VD) with two substates and two embedded per-survivor decision-feedback taps operating at one-eighth of the modulation rate is described. Implemented in an experimental chip fabricated in 14nm CMOS, the VD is designed to recover data at 25.6 Gb/s over an emulated time-dispersive channel. The power consumption of the VD together with the test circuitry is 105mW at a supply of 0.7V, achieving an overall energy efficiency of 4.1 pJ/b. At a supply of 0.8V, a data rate of 30.4 Gb/s is achieved with an energy efficiency of 5.3 pJ/b. The VD occupies an area of 0.507×0.717mm2. Experimental results showing system performance are obtained using a (215-1)-bit pseudo-random binary sequence. The impact on the bit error rate of the synchronization length for block initialization is also measured.
{"title":"A 4.1 pJ/b 25.6 Gb/s 4-PAM reduced-state sliding-block Viterbi detector in 14 nm CMOS","authors":"Hazar Yueksel, M. Braendli, A. Burg, G. Cherubini, R. Cideciyan, P. Francese, S. Furrer, M. Kossel, L. Kull, D. Luu, C. Menolfi, T. Morf, T. Toifl","doi":"10.1109/ESSCIRC.2016.7598304","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2016.7598304","url":null,"abstract":"The implementation of a digital four-level pulse-amplitude-modulation reduced-state sliding-block Viterbi detector (VD) with two substates and two embedded per-survivor decision-feedback taps operating at one-eighth of the modulation rate is described. Implemented in an experimental chip fabricated in 14nm CMOS, the VD is designed to recover data at 25.6 Gb/s over an emulated time-dispersive channel. The power consumption of the VD together with the test circuitry is 105mW at a supply of 0.7V, achieving an overall energy efficiency of 4.1 pJ/b. At a supply of 0.8V, a data rate of 30.4 Gb/s is achieved with an energy efficiency of 5.3 pJ/b. The VD occupies an area of 0.507×0.717mm2. Experimental results showing system performance are obtained using a (215-1)-bit pseudo-random binary sequence. The impact on the bit error rate of the synchronization length for block initialization is also measured.","PeriodicalId":246471,"journal":{"name":"ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121584810","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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