Pub Date : 2016-09-01DOI: 10.1109/ESSCIRC.2016.7598281
J. Handwerker, M. Eder, M. Tibiletti, V. Rasche, K. Scheffler, J. Becker, M. Ortmanns, J. Anders
In this paper we present fully-integrated field probes for real-time trajectory mapping during magnetic resonance imaging (MRI) experiments. The field probes co-integrate an NMR microcoil and the required transceiver electronics on a single ASIC manufactured in a 0.13μm CMOS technology. Thanks to an on-chip PLL, power amplifier and low-IF quadrature receiver, all connections to and from the chip carry only low frequency signals allowing for an effective reduction of the magnetic coupling between the field probes and the MRI scanner during imaging. The small form factor and low power consumption of 16.5mW allows for the realization of arrays of field probes, which in contrast to single probes enable the correction of higher order field imperfections. Measured trajectory maps acquired with a prototype array consisting of four probes demonstrate the excellent sensor performance achievable using the proposed approach.
{"title":"An array of fully-integrated quadrature TX/RX NMR field probes for MRI trajectory mapping","authors":"J. Handwerker, M. Eder, M. Tibiletti, V. Rasche, K. Scheffler, J. Becker, M. Ortmanns, J. Anders","doi":"10.1109/ESSCIRC.2016.7598281","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2016.7598281","url":null,"abstract":"In this paper we present fully-integrated field probes for real-time trajectory mapping during magnetic resonance imaging (MRI) experiments. The field probes co-integrate an NMR microcoil and the required transceiver electronics on a single ASIC manufactured in a 0.13μm CMOS technology. Thanks to an on-chip PLL, power amplifier and low-IF quadrature receiver, all connections to and from the chip carry only low frequency signals allowing for an effective reduction of the magnetic coupling between the field probes and the MRI scanner during imaging. The small form factor and low power consumption of 16.5mW allows for the realization of arrays of field probes, which in contrast to single probes enable the correction of higher order field imperfections. Measured trajectory maps acquired with a prototype array consisting of four probes demonstrate the excellent sensor performance achievable using the proposed approach.","PeriodicalId":246471,"journal":{"name":"ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference","volume":"458 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122734413","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-09-01DOI: 10.1109/ESSCIRC.2016.7598272
Xiao Xiao, Amanda Pratt, A. Niknejad, E. Alon, B. Nikolić
A wideband time-division duplex (TDD) front-end with an integrated transmit/receive (T/R) switching technique is implemented in 65nm CMOS. By re-using the PA as an LNA during receive mode, the system eliminates the conventional series T/R switch from the signal path and utilizes only DC mode control switches to enable TDD co-existence. With integrated front-end balun transformer, the full polar transmitter achieves 20dBm peak output power with 32.7% peak drain efficiency. In receive mode, the PA is reconfigured into a wideband 3.4GHz-5.4GHz LNA achieving -6.7dBm P1dB and 5.1dB NF.
{"title":"A 65nm CMOS wideband TDD front-end with integrated T/R switching via PA re-use","authors":"Xiao Xiao, Amanda Pratt, A. Niknejad, E. Alon, B. Nikolić","doi":"10.1109/ESSCIRC.2016.7598272","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2016.7598272","url":null,"abstract":"A wideband time-division duplex (TDD) front-end with an integrated transmit/receive (T/R) switching technique is implemented in 65nm CMOS. By re-using the PA as an LNA during receive mode, the system eliminates the conventional series T/R switch from the signal path and utilizes only DC mode control switches to enable TDD co-existence. With integrated front-end balun transformer, the full polar transmitter achieves 20dBm peak output power with 32.7% peak drain efficiency. In receive mode, the PA is reconfigured into a wideband 3.4GHz-5.4GHz LNA achieving -6.7dBm P1dB and 5.1dB NF.","PeriodicalId":246471,"journal":{"name":"ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference","volume":"178 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115220871","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-09-01DOI: 10.1109/ESSCIRC.2016.7598331
D. Muratore, Alper Akdikmen, E. Bonizzoni, F. Maloberti, U. Chio, Sai-Weng Sin, R. Martins
This paper presents the prototype of a single channel 8-bit 0.7-GS/s A/D converter implemented in a 65-nm CMOS process. The required thresholds are generated from the resistive interpolation embedded within the preamplifier preceding the latches. The active area of the chip is 150 × 220 μm2 and the total power consumption is 5.96 mW. At Nyquist, the ADC achieves 6.62 ENOB, resulting in a figure of merit equal to 86.7 fJ/conversion-step.
本文介绍了一种采用65纳米CMOS工艺实现的单通道8位0.7-GS/s a /D转换器的原型。所需的阈值由嵌入在锁存器之前的前置放大器内的电阻插值产生。芯片的有效面积为150 × 220 μm2，总功耗为5.96 mW。在奈奎斯特，ADC达到6.62 ENOB，其优点等于86.7 fJ/转换步长。
{"title":"An 8-bit 0.7-GS/s single channel flash-SAR ADC in 65-nm CMOS technology","authors":"D. Muratore, Alper Akdikmen, E. Bonizzoni, F. Maloberti, U. Chio, Sai-Weng Sin, R. Martins","doi":"10.1109/ESSCIRC.2016.7598331","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2016.7598331","url":null,"abstract":"This paper presents the prototype of a single channel 8-bit 0.7-GS/s A/D converter implemented in a 65-nm CMOS process. The required thresholds are generated from the resistive interpolation embedded within the preamplifier preceding the latches. The active area of the chip is 150 × 220 μm2 and the total power consumption is 5.96 mW. At Nyquist, the ADC achieves 6.62 ENOB, resulting in a figure of merit equal to 86.7 fJ/conversion-step.","PeriodicalId":246471,"journal":{"name":"ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115329638","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-09-01DOI: 10.1109/ESSCIRC.2016.7598257
Shing-Tak Yan, Lu Ye, Hongbing Wu, R. Kulkarni, Edward Myers, H. Shih, Shadi Saberi, Darshan Kadia, Dizle Ozis, Lei Zhou, Eric Middleton, Joo Leong Tham
This paper describes the first dual-band MIMO 802.11a/b/g/n/ac WLAN RF transceiver capable of simultaneous dual-band operation. The measured receiver sensitivity of 2 GHz at 54 Mbps is -78.3 dBm and of 5 GHz for VHT80 is -66 dBm. The 802.11ac 2×2 MIMO 20 MHz MCS0 2 GHz and 5 GHz receiver sensitivity levels are -96 dBm and -95.5 dBm respectively. Integrated power amplifiers with Psat of +29 dBm enable the 2 GHz transmitters to achieve TX output power of +23.5 dBm at 54 Mbps 64-QAM. The 5 GHz transmitters achieve +17 dBm output for VHT80 256-QAM. This WLAN-BT connectivity SoC is implemented in 40 nm CMOS technology.
{"title":"An 802.11a/b/g/n/ac WLAN Transceiver for 2×2 MIMO and simultaneous dual-band operation with +29 dBm Psat integrated power amplifiers","authors":"Shing-Tak Yan, Lu Ye, Hongbing Wu, R. Kulkarni, Edward Myers, H. Shih, Shadi Saberi, Darshan Kadia, Dizle Ozis, Lei Zhou, Eric Middleton, Joo Leong Tham","doi":"10.1109/ESSCIRC.2016.7598257","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2016.7598257","url":null,"abstract":"This paper describes the first dual-band MIMO 802.11a/b/g/n/ac WLAN RF transceiver capable of simultaneous dual-band operation. The measured receiver sensitivity of 2 GHz at 54 Mbps is -78.3 dBm and of 5 GHz for VHT80 is -66 dBm. The 802.11ac 2×2 MIMO 20 MHz MCS0 2 GHz and 5 GHz receiver sensitivity levels are -96 dBm and -95.5 dBm respectively. Integrated power amplifiers with Psat of +29 dBm enable the 2 GHz transmitters to achieve TX output power of +23.5 dBm at 54 Mbps 64-QAM. The 5 GHz transmitters achieve +17 dBm output for VHT80 256-QAM. This WLAN-BT connectivity SoC is implemented in 40 nm CMOS technology.","PeriodicalId":246471,"journal":{"name":"ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference","volume":"229 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114581689","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-09-01DOI: 10.1109/ESSCIRC.2016.7598267
David Stuart Robertson, A. Buchwald, Michael J. Flynn, Hae-Seung Lee, U. Moon, B. Murmann
The authors discuss several papers that have been presented over the last decade that are worth additional consideration by readers interested in data converter circuits. The papers have been selected for different reasons: some have become trend-setters, others present particularly interesting ideas that may yet set future trends.
{"title":"Data converter reflections: 19 papers from the last ten years that deserve a second look","authors":"David Stuart Robertson, A. Buchwald, Michael J. Flynn, Hae-Seung Lee, U. Moon, B. Murmann","doi":"10.1109/ESSCIRC.2016.7598267","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2016.7598267","url":null,"abstract":"The authors discuss several papers that have been presented over the last decade that are worth additional consideration by readers interested in data converter circuits. The papers have been selected for different reasons: some have become trend-setters, others present particularly interesting ideas that may yet set future trends.","PeriodicalId":246471,"journal":{"name":"ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115794875","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-09-01DOI: 10.1109/ESSCIRC.2016.7598265
C. Fraisse, A. Nagari
The sense path design for new MEMS applications requires up to 20-Bit dynamic range in small low-frequency bandwidth removing the offset and 1/f noise. In this paper a new sense chain design, aimed to reach 19-Bit dynamic range in 150Hz bandwidth has been presented implementing a new full-chopper system using chopped integrators. The proposed sense path has been successfully inserted into a new gyroscope MEMS based device with a target of 1.5mdps/sqrt(Hz) noise. The circuit has been implemented in 0.13μm CMOS technology.
{"title":"A ΣΔ sense chain using chopped integrators for ultra-low-noise MEMS system","authors":"C. Fraisse, A. Nagari","doi":"10.1109/ESSCIRC.2016.7598265","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2016.7598265","url":null,"abstract":"The sense path design for new MEMS applications requires up to 20-Bit dynamic range in small low-frequency bandwidth removing the offset and 1/f noise. In this paper a new sense chain design, aimed to reach 19-Bit dynamic range in 150Hz bandwidth has been presented implementing a new full-chopper system using chopped integrators. The proposed sense path has been successfully inserted into a new gyroscope MEMS based device with a target of 1.5mdps/sqrt(Hz) noise. The circuit has been implemented in 0.13μm CMOS technology.","PeriodicalId":246471,"journal":{"name":"ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference","volume":"113 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124911375","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-09-01DOI: 10.1109/ESSCIRC.2016.7598307
S. Gangopadhyay, Saad Bin Nasir, A. Subramanian, V. Sathe, A. Raychowdhury
A fully-digital, single-loop Unified Voltage and Frequency Regulator (UVFR) is designed in 130nm CMOS to provide the correct supply to digital loads to meet a timing criteria. Simultaneously a Tunable Replica Circuit (TRC) based local oscillator is generated from the regulated supply and clocks the load. Measurements show 0.84V to 0.27V range of operation, and 27% supply guardband reduction at iso-performance through adaptation and resiliency which are intrinsic to the control loop.
{"title":"UVFR: A Unified Voltage and Frequency Regulator with 500MHz/0.84V to 100KHz/0.27V operating range, 99.4% current efficiency and 27% supply guardband reduction","authors":"S. Gangopadhyay, Saad Bin Nasir, A. Subramanian, V. Sathe, A. Raychowdhury","doi":"10.1109/ESSCIRC.2016.7598307","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2016.7598307","url":null,"abstract":"A fully-digital, single-loop Unified Voltage and Frequency Regulator (UVFR) is designed in 130nm CMOS to provide the correct supply to digital loads to meet a timing criteria. Simultaneously a Tunable Replica Circuit (TRC) based local oscillator is generated from the regulated supply and clocks the load. Measurements show 0.84V to 0.27V range of operation, and 27% supply guardband reduction at iso-performance through adaptation and resiliency which are intrinsic to the control loop.","PeriodicalId":246471,"journal":{"name":"ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128902352","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-09-01DOI: 10.1109/ESSCIRC.2016.7598316
Qingrui Meng, R. Harjani
This paper presents a novel four-channel, four-beam receiver core based on a FFT core that is easily extended to a larger number of beams. This architecture is particulary well suited for MIMO systems where multiple beams are used for increased throughput. Like the FFT, the proposed architecture reuses computations for multi-beam systems. In particular, the proposed architecture redistributes the computations so as to maximize the reuse of the structure that already exist in a receiver chain. In many fashions the architecture is quite similar to a Butler matrix but unlike the Butler matrix it does not use large passive components at RF. Further, we exploit the normally occurring quadrature down-conversion process to implement the tap weights. In comparison to traditional MIMO architectures, that effectively duplicate each path, the distributed computations of this architecture provide partial spatial filtering before the final stage, improving interference rejection for the blocks between the LNA and the ADC. Additionally, because of the spatial filtering prior to the ADC, a single interferer only jams a single beam allowing for continued operation though at a lower combined throughput. The four-beam receiver core prototype in 65nm CMOS implements the basic FFT based architecture but does not include an LNA or extensive IF stages. This four-channel design consumes 56mW power and occupies an active area of 0.65mm2 excluding pads and test circuits.
{"title":"An easily extendable FFT based four-channel, four-beam receiver with progressive partial spatial filtering in 65nm","authors":"Qingrui Meng, R. Harjani","doi":"10.1109/ESSCIRC.2016.7598316","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2016.7598316","url":null,"abstract":"This paper presents a novel four-channel, four-beam receiver core based on a FFT core that is easily extended to a larger number of beams. This architecture is particulary well suited for MIMO systems where multiple beams are used for increased throughput. Like the FFT, the proposed architecture reuses computations for multi-beam systems. In particular, the proposed architecture redistributes the computations so as to maximize the reuse of the structure that already exist in a receiver chain. In many fashions the architecture is quite similar to a Butler matrix but unlike the Butler matrix it does not use large passive components at RF. Further, we exploit the normally occurring quadrature down-conversion process to implement the tap weights. In comparison to traditional MIMO architectures, that effectively duplicate each path, the distributed computations of this architecture provide partial spatial filtering before the final stage, improving interference rejection for the blocks between the LNA and the ADC. Additionally, because of the spatial filtering prior to the ADC, a single interferer only jams a single beam allowing for continued operation though at a lower combined throughput. The four-beam receiver core prototype in 65nm CMOS implements the basic FFT based architecture but does not include an LNA or extensive IF stages. This four-channel design consumes 56mW power and occupies an active area of 0.65mm2 excluding pads and test circuits.","PeriodicalId":246471,"journal":{"name":"ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122407072","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-09-01DOI: 10.1109/ESSCIRC.2016.7598280
C. Ho, M. Chen
This work proposes a DSP technique to mitigate the interference-induced spurious tones coupled to the digitally controlled oscillator (DCO) of a digital phase locked loop (DPLL). We leverage the digitized phase information at the time-to-digital converter (TDC) output, and formulate an adaptive algorithm to identify the interference pattern from any electrical or magnetic coupling path, and inject the cancellation signal accordingly. The proposed algorithm also keeps track of the magnitude and phase variation in the background. We experiment with the algorithm in a 65nm 3-5 GHz DPLL prototype and observe 10 ~ 30 dB spur reduction from different coupling paths to the DCO over various interference frequencies. Additionally, the prototype measures reference spur of <;-110dBc and phase noise of - 129dBc/Hz at 3MHz offset frequency.
{"title":"Interference-induced DCO spur mitigation for digital phase locked loop in 65-nm CMOS","authors":"C. Ho, M. Chen","doi":"10.1109/ESSCIRC.2016.7598280","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2016.7598280","url":null,"abstract":"This work proposes a DSP technique to mitigate the interference-induced spurious tones coupled to the digitally controlled oscillator (DCO) of a digital phase locked loop (DPLL). We leverage the digitized phase information at the time-to-digital converter (TDC) output, and formulate an adaptive algorithm to identify the interference pattern from any electrical or magnetic coupling path, and inject the cancellation signal accordingly. The proposed algorithm also keeps track of the magnitude and phase variation in the background. We experiment with the algorithm in a 65nm 3-5 GHz DPLL prototype and observe 10 ~ 30 dB spur reduction from different coupling paths to the DCO over various interference frequencies. Additionally, the prototype measures reference spur of <;-110dBc and phase noise of - 129dBc/Hz at 3MHz offset frequency.","PeriodicalId":246471,"journal":{"name":"ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121136251","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-09-01DOI: 10.1109/ESSCIRC.2016.7598273
Suchendranath Popuri, V. Pasupureddi, J. Sturm
A tunable gain and tunable band low-noise amplifier (LNA) for IEEE 802.11ac WLAN standard is proposed, with low noise figure and high linearity. The LNA is based on an active balun cascode topology with buffered negative feedback to achieve a differential signalling at the output. The unique feature of the proposed LNA includes highly linear, continuously tunable gain from 3 dB to 23 dB, in addition to a tunable frequency band from 4.5 GHz to 5.5 GHz, while meeting other critical LNA parameters such as noise figure and third order input inter-modulation point (IIP3). Tunable gain is achieved with the help of active CMOS resistors (ACR) at the core LNA load and also in the active negative feedback path, while tunable frequency band is achieved by a tunable LC tank load. The buffered negative feedback with cascode active balun provides the low noise figure and competitive IIP3. The LNA is implemented in 1.2V, 65nm CMOS technology. Measured LNA performance shows a noise figure of 2 dB and IIP3 of -6.5dBm at the highest gain of 23 dB and a noise figure of 6 dB and IIP3 of +10dBm at the lowest gain of 3 dB. The active chip area of the LNA is 0.043mm2 with a moderate power consumption of 16mW.
{"title":"A tunable gain and tunable band active balun LNA for IEEE 802.11ac WLAN receivers","authors":"Suchendranath Popuri, V. Pasupureddi, J. Sturm","doi":"10.1109/ESSCIRC.2016.7598273","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2016.7598273","url":null,"abstract":"A tunable gain and tunable band low-noise amplifier (LNA) for IEEE 802.11ac WLAN standard is proposed, with low noise figure and high linearity. The LNA is based on an active balun cascode topology with buffered negative feedback to achieve a differential signalling at the output. The unique feature of the proposed LNA includes highly linear, continuously tunable gain from 3 dB to 23 dB, in addition to a tunable frequency band from 4.5 GHz to 5.5 GHz, while meeting other critical LNA parameters such as noise figure and third order input inter-modulation point (IIP3). Tunable gain is achieved with the help of active CMOS resistors (ACR) at the core LNA load and also in the active negative feedback path, while tunable frequency band is achieved by a tunable LC tank load. The buffered negative feedback with cascode active balun provides the low noise figure and competitive IIP3. The LNA is implemented in 1.2V, 65nm CMOS technology. Measured LNA performance shows a noise figure of 2 dB and IIP3 of -6.5dBm at the highest gain of 23 dB and a noise figure of 6 dB and IIP3 of +10dBm at the lowest gain of 3 dB. The active chip area of the LNA is 0.043mm2 with a moderate power consumption of 16mW.","PeriodicalId":246471,"journal":{"name":"ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference","volume":"72 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121235346","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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