Pub Date : 2018-10-01DOI: 10.1109/SMICND.2018.8539778
A. F. Bîzîitu, B. L. Goras
Integrated charge pumps optimized for driving resistive loads are usually using a feedback control loop for improving the power efficiency over the entire specified load range. We propose a new circuit topology that combines charge recycling with a feedback control loop based on a regulated clock buffer supply that is also capable of adiabatic charging. The clock buffer supply regulation, as well as the adiabatic charging mechanism are both employed via a single on-chip fast transient response voltage regulator.
{"title":"Regulation Mechanism for Dickson Charge Pumps Using Charge Recycling and Adiabatic Charging","authors":"A. F. Bîzîitu, B. L. Goras","doi":"10.1109/SMICND.2018.8539778","DOIUrl":"https://doi.org/10.1109/SMICND.2018.8539778","url":null,"abstract":"Integrated charge pumps optimized for driving resistive loads are usually using a feedback control loop for improving the power efficiency over the entire specified load range. We propose a new circuit topology that combines charge recycling with a feedback control loop based on a regulated clock buffer supply that is also capable of adiabatic charging. The clock buffer supply regulation, as well as the adiabatic charging mechanism are both employed via a single on-chip fast transient response voltage regulator.","PeriodicalId":247062,"journal":{"name":"2018 International Semiconductor Conference (CAS)","volume":"161 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115971489","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-10-01DOI: 10.1109/SMICND.2018.8539744
G. de Martino, F. Pezzimenti, F. D. Della Corte
The current-voltage characteristics of a 4H-SiC MOSFET dimensioned for a breakdown voltage of 650 V are investigated by means of a numerical simulation study that takes into account the defect state distribution at the oxide-semiconductor interface in the channel region. The modelling analysis reveals that, for these low-voltage devices, the channel resistance component plays a key role in determining the MOSFET specific ON-state resistance (RON) under different voltage biases and temperatures. The RON value is in the order of a few mΩ×cm2.
{"title":"Interface Trap Effects in the Design of a 4H-SiC MOSFET for Low Voltage Applications","authors":"G. de Martino, F. Pezzimenti, F. D. Della Corte","doi":"10.1109/SMICND.2018.8539744","DOIUrl":"https://doi.org/10.1109/SMICND.2018.8539744","url":null,"abstract":"The current-voltage characteristics of a 4H-SiC MOSFET dimensioned for a breakdown voltage of 650 V are investigated by means of a numerical simulation study that takes into account the defect state distribution at the oxide-semiconductor interface in the channel region. The modelling analysis reveals that, for these low-voltage devices, the channel resistance component plays a key role in determining the MOSFET specific ON-state resistance (RON) under different voltage biases and temperatures. The RON value is in the order of a few mΩ×cm2.","PeriodicalId":247062,"journal":{"name":"2018 International Semiconductor Conference (CAS)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126369734","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-10-01DOI: 10.1109/smicnd.2018.8539748
A. Bunea, D. Neculoiu, A. Dinescu
This paper proposes a quasi-wafer level packaging approach of surface acoustic wave band pass filters (SAW-BPF) with operating frequencies above 5 GHz. A Poly(methyl methacrylate) (PMMA) cap is designed, fabricated and glued using an epoxy resin directly on the GaN/Si chip. First a coplanar waveguide transmission line is packaged and measured up to 65 GHz. Results show additional insertion losses of only 0.1 dB up to millimeter wave frequencies. A 5.6 GHz SAW-BPF is then packaged using the same approach. Measurement results show excellent properties of the packaged device for a temperature range between −150 … + 150°C.
{"title":"Wafer Level Packaging of GaN/Si SAW Band Pass Filters with Operating Frequencies Above 5 GHz","authors":"A. Bunea, D. Neculoiu, A. Dinescu","doi":"10.1109/smicnd.2018.8539748","DOIUrl":"https://doi.org/10.1109/smicnd.2018.8539748","url":null,"abstract":"This paper proposes a quasi-wafer level packaging approach of surface acoustic wave band pass filters (SAW-BPF) with operating frequencies above 5 GHz. A Poly(methyl methacrylate) (PMMA) cap is designed, fabricated and glued using an epoxy resin directly on the GaN/Si chip. First a coplanar waveguide transmission line is packaged and measured up to 65 GHz. Results show additional insertion losses of only 0.1 dB up to millimeter wave frequencies. A 5.6 GHz SAW-BPF is then packaged using the same approach. Measurement results show excellent properties of the packaged device for a temperature range between −150 … + 150°C.","PeriodicalId":247062,"journal":{"name":"2018 International Semiconductor Conference (CAS)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132455586","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-10-01DOI: 10.1109/SMICND.2018.8539745
I. Stavarache, L. Nedelcu, V. Teodorescu, V. Maraloiu, I. Dascalescu, M. Ciurea
The films of SiGe nanocrystals in SiO2on Si substrate were obtained by co-sputtering Si, Ge, and SiO2followed by rapid thermal annealing. The films structure and morphology together with electrical and photoelectrical properties were studied by x-ray diffraction, transmission electron microscopy, current - voltage and spectral photocurrent measurements. The photocurrent spectra at 300, 200 and 100 K were correlated with results obtained from X-ray diffractograms and transmission electron microscopy. The photocurrent spectra show an extension in near infrared due to the enriching SiGe nanocrystals in Ge.
{"title":"GeSi Nanocrystals in SiO2 Matrix with Extended Photoresponse in Near Infrared","authors":"I. Stavarache, L. Nedelcu, V. Teodorescu, V. Maraloiu, I. Dascalescu, M. Ciurea","doi":"10.1109/SMICND.2018.8539745","DOIUrl":"https://doi.org/10.1109/SMICND.2018.8539745","url":null,"abstract":"The films of SiGe nanocrystals in SiO2on Si substrate were obtained by co-sputtering Si, Ge, and SiO2followed by rapid thermal annealing. The films structure and morphology together with electrical and photoelectrical properties were studied by x-ray diffraction, transmission electron microscopy, current - voltage and spectral photocurrent measurements. The photocurrent spectra at 300, 200 and 100 K were correlated with results obtained from X-ray diffractograms and transmission electron microscopy. The photocurrent spectra show an extension in near infrared due to the enriching SiGe nanocrystals in Ge.","PeriodicalId":247062,"journal":{"name":"2018 International Semiconductor Conference (CAS)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115340851","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-10-01DOI: 10.1109/SMICND.2018.8539791
Mihai Dicianu, Vlad Ionescu, C. Dan
This paper presents a 5V LDO architecture with a buffered error amplifier. This is achieved by using a functional block called a dual complementary buffer which consists of two buffers, one using a NMOS output transistor, the other a PMOS output transistor. The main advantage of this architecture is the rail-to-rail output voltage swing of the buffer, improving performance in both the tracking and the regulating operating regions of the voltage regulator. Simulation results show load regulation of 4.47uV/mA and line regulation of 3.92uV/v. The maximum input voltage is 40V and the maximum load current is 200mA. The LDO was simulated using a 0.8um BiCMOS process.
{"title":"LDO with a Dual Complementary Buffer Architecture","authors":"Mihai Dicianu, Vlad Ionescu, C. Dan","doi":"10.1109/SMICND.2018.8539791","DOIUrl":"https://doi.org/10.1109/SMICND.2018.8539791","url":null,"abstract":"This paper presents a 5V LDO architecture with a buffered error amplifier. This is achieved by using a functional block called a dual complementary buffer which consists of two buffers, one using a NMOS output transistor, the other a PMOS output transistor. The main advantage of this architecture is the rail-to-rail output voltage swing of the buffer, improving performance in both the tracking and the regulating operating regions of the voltage regulator. Simulation results show load regulation of 4.47uV/mA and line regulation of 3.92uV/v. The maximum input voltage is 40V and the maximum load current is 200mA. The LDO was simulated using a 0.8um BiCMOS process.","PeriodicalId":247062,"journal":{"name":"2018 International Semiconductor Conference (CAS)","volume":"106 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115153761","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-10-01DOI: 10.1109/SMICND.2018.8539846
G. Bonteanu, A. Cracan
A low power and low area voltage mode CMOS capacitance multiplication technique is presented. The multiplication factor is conveniently given by the transconductance ratio of two transistors, thereby improving the immunity to process and temperature variations. A low power wide range adjustable relaxation oscillator is presented as application.
{"title":"Low Power and Low Area CMOS Capacitance Multiplier","authors":"G. Bonteanu, A. Cracan","doi":"10.1109/SMICND.2018.8539846","DOIUrl":"https://doi.org/10.1109/SMICND.2018.8539846","url":null,"abstract":"A low power and low area voltage mode CMOS capacitance multiplication technique is presented. The multiplication factor is conveniently given by the transconductance ratio of two transistors, thereby improving the immunity to process and temperature variations. A low power wide range adjustable relaxation oscillator is presented as application.","PeriodicalId":247062,"journal":{"name":"2018 International Semiconductor Conference (CAS)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123333838","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-10-01DOI: 10.1109/SMICND.2018.8539743
V. Placinta, L. N. Cojocariu, C. Ravariu
In this paper we present a survey of radiation induced failures in the Input/Output blocks of an SRAM-based Field Programmable Gate Array (FPGA), using a ring oscillator-based measurement technique. This study has been done on Xilinx's KINTEX-7 FPGA, while exposed to ion and X-rays beams. Two types of failures have been identified, amplitude and duty cycle failures, and the cross-section values were estimated to be approximately 0.6 · 10−5cm2/device for the amplitude failures and 1.6 · 10−5cm2/device for the other ones.
{"title":"I/O Blocks Reliability for an SRAM-Based FPGA When Exposed to Ionizing Radiation","authors":"V. Placinta, L. N. Cojocariu, C. Ravariu","doi":"10.1109/SMICND.2018.8539743","DOIUrl":"https://doi.org/10.1109/SMICND.2018.8539743","url":null,"abstract":"In this paper we present a survey of radiation induced failures in the Input/Output blocks of an SRAM-based Field Programmable Gate Array (FPGA), using a ring oscillator-based measurement technique. This study has been done on Xilinx's KINTEX-7 FPGA, while exposed to ion and X-rays beams. Two types of failures have been identified, amplitude and duty cycle failures, and the cross-section values were estimated to be approximately 0.6 · 10<sup>−5</sup>cm<sup>2</sup>/device for the amplitude failures and 1.6 · 10<sup>−5</sup>cm<sup>2</sup>/device for the other ones.","PeriodicalId":247062,"journal":{"name":"2018 International Semiconductor Conference (CAS)","volume":"184 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128606766","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-10-01DOI: 10.1109/SMICND.2018.8539761
M. T. Sultan, J. Gudmundsson, A. Manolescu, M.L. Ciureai, H. Svavarsson
The effect of room temperature hydrogen plasma treatment on the photoconductive properties of the SiO2 matrix containing SiGe nanoparticles is investigated. A considerable increase in photocurrent intensity is observed after plasma treatment. The increase is partly attributed to neutralization of dangling bonds around the nanoparticles and partly to passivation of non-radiative centers and defects in the matrix and at the nanoparticles-matrix interfaces.
{"title":"The Effect of H2/Ar Plasma Treatment Over Photoconductivity of Sige Nanoparticles Sandwiched Between Silicon Oxide Matrix","authors":"M. T. Sultan, J. Gudmundsson, A. Manolescu, M.L. Ciureai, H. Svavarsson","doi":"10.1109/SMICND.2018.8539761","DOIUrl":"https://doi.org/10.1109/SMICND.2018.8539761","url":null,"abstract":"The effect of room temperature hydrogen plasma treatment on the photoconductive properties of the SiO2 matrix containing SiGe nanoparticles is investigated. A considerable increase in photocurrent intensity is observed after plasma treatment. The increase is partly attributed to neutralization of dangling bonds around the nanoparticles and partly to passivation of non-radiative centers and defects in the matrix and at the nanoparticles-matrix interfaces.","PeriodicalId":247062,"journal":{"name":"2018 International Semiconductor Conference (CAS)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125165203","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-10-01DOI: 10.1109/SMICND.2018.8539793
L. M. Cursaru Popescu, A. Plăiașu, C. Ducu, R. Piticescu, I. Tudor
In this study, CNT-PANI composites were prepared in soft chemical synthesis conditions using hydrothermal method. Our aim is to obtain CNT-PANI films with potential applications in VOC's detection, using an environmental friendly, low energy consumption technique: hydrothermal-electrochemical deposition of composite films. Thin films were characterized by AFM and FT-IR analyses.
{"title":"Carbon Nanotube/Polyaniline Composite Films Prepared by Hydrothermal- Electrochemical Method for Biosensor Applications","authors":"L. M. Cursaru Popescu, A. Plăiașu, C. Ducu, R. Piticescu, I. Tudor","doi":"10.1109/SMICND.2018.8539793","DOIUrl":"https://doi.org/10.1109/SMICND.2018.8539793","url":null,"abstract":"In this study, CNT-PANI composites were prepared in soft chemical synthesis conditions using hydrothermal method. Our aim is to obtain CNT-PANI films with potential applications in VOC's detection, using an environmental friendly, low energy consumption technique: hydrothermal-electrochemical deposition of composite films. Thin films were characterized by AFM and FT-IR analyses.","PeriodicalId":247062,"journal":{"name":"2018 International Semiconductor Conference (CAS)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126538949","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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