Pub Date : 2018-10-01DOI: 10.1109/SMICND.2018.8539796
Radu-Valentin Petrica, Mihaela-Daniela Dobre, P. Coll, F. Draghici, G. Brezeanu
Novel low-voltage and high-speed level shifter topologies will be presented. The level shifters circuits were designed in 40 nm technology using 1.2V devices and zero-VT transistors. These techniques will provide functionality near the threshold region. The simulated results were compared with a reference architecture. The resulted level shifters will be integrated in an already tested I/O structure. The results were analyzed in terms of electrical performance and silicon area.
{"title":"Comparison of Level Shifter Architectures: Application to I/O Cell","authors":"Radu-Valentin Petrica, Mihaela-Daniela Dobre, P. Coll, F. Draghici, G. Brezeanu","doi":"10.1109/SMICND.2018.8539796","DOIUrl":"https://doi.org/10.1109/SMICND.2018.8539796","url":null,"abstract":"Novel low-voltage and high-speed level shifter topologies will be presented. The level shifters circuits were designed in 40 nm technology using 1.2V devices and zero-VT transistors. These techniques will provide functionality near the threshold region. The simulated results were compared with a reference architecture. The resulted level shifters will be integrated in an already tested I/O structure. The results were analyzed in terms of electrical performance and silicon area.","PeriodicalId":247062,"journal":{"name":"2018 International Semiconductor Conference (CAS)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130901960","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-10-01DOI: 10.1109/SMICND.2018.8539764
I. Hurez, Ted Y. G. Chen, F. Vlădoianu, V. Anghel, G. Brezeanu
This paper presents a fault detection and reporting technique for galvanically isolated Insulated Gate Bipolar Transistor (IGBT) gate drivers. This technique provides robust transmission of Under Voltage Lock Out (UVLO) and Desaturation (DESAT) events. The proposed method was verified by means of simulations and implemented in a standard 0.25µm CMOS BCD technology, as part of a galvanically isolated IGBT gate driver. Experimental results highlight proper reporting of UVLO and DESAT faults.
{"title":"Message Recovered: A Robust Fault Detection and Reporting Method for Galvanically Isolated IGBT Gate Drivers","authors":"I. Hurez, Ted Y. G. Chen, F. Vlădoianu, V. Anghel, G. Brezeanu","doi":"10.1109/SMICND.2018.8539764","DOIUrl":"https://doi.org/10.1109/SMICND.2018.8539764","url":null,"abstract":"This paper presents a fault detection and reporting technique for galvanically isolated Insulated Gate Bipolar Transistor (IGBT) gate drivers. This technique provides robust transmission of Under Voltage Lock Out (UVLO) and Desaturation (DESAT) events. The proposed method was verified by means of simulations and implemented in a standard 0.25µm CMOS BCD technology, as part of a galvanically isolated IGBT gate driver. Experimental results highlight proper reporting of UVLO and DESAT faults.","PeriodicalId":247062,"journal":{"name":"2018 International Semiconductor Conference (CAS)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116132163","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-10-01DOI: 10.1109/SMICND.2018.8539812
A. Antonescu, L. Dobrescu, D. Dobrescu
A new technique for adjusting the duty cycle in low cost 70MHz charge/discharge based oscillator topology is proposed. Added circuitry is optimized in order to maintain the frequency variation of the initial oscillator topology (without duty cycle adjustment) for a supply voltage range between 1.6V and 2V. The circuit uses different bias currents for each stage and it is implemented using Cadence design suite. It features reduces sensitivity to supply voltage range of the output frequency and low duty cycle variation.
{"title":"Duty Cycle Adjustment for the Low Cost High Frequency Charge/Discharge CMOS Oscillator","authors":"A. Antonescu, L. Dobrescu, D. Dobrescu","doi":"10.1109/SMICND.2018.8539812","DOIUrl":"https://doi.org/10.1109/SMICND.2018.8539812","url":null,"abstract":"A new technique for adjusting the duty cycle in low cost 70MHz charge/discharge based oscillator topology is proposed. Added circuitry is optimized in order to maintain the frequency variation of the initial oscillator topology (without duty cycle adjustment) for a supply voltage range between 1.6V and 2V. The circuit uses different bias currents for each stage and it is implemented using Cadence design suite. It features reduces sensitivity to supply voltage range of the output frequency and low duty cycle variation.","PeriodicalId":247062,"journal":{"name":"2018 International Semiconductor Conference (CAS)","volume":"15 9","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121007825","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-10-01DOI: 10.1109/SMICND.2018.8539757
N. C. Laurenciu, S. Cotofana
With CMOS feature size heading towards atomic dimensions, unjustifiable static power, reliability, and economic implications are exacerbating, prompting for research on new materials, devices, and/or computation paradigms. Within this context, Graphene Nanoribbons (GNRs), owing to graphene's excellent electronic properties, may serve as basic blocks for carbon-based nanoelectronics. In this paper, we present the two main avenues, i.e., graphene FET- and GNR- based, undertaken towards graphene based computing. The first approach is conservative and focuses on the realization of graphene FET transistor based switches as MOSFET replacements to maintain the state of the art logic Boolean algebra paradigm design methodology. The second one follows a different line of thinking and seeks GNR-based structures able to provide more complex behaviours by making better use of graphene's conduction properties. We first discuss Graphene Nanoribbon (GNR) based field Effect Transistors (GNRFETs) and Tunnelling GNR based Transistors (GNRTFETs) and their utilization as underlying elements for Boolean gate implementations. Subsequently, we present GNR-based structures that can directly compute Boolean functions, e.g., NAND, XOR, by means of one GNR only and a way to complementary arrange them in energy effective gates. To get inside into the potential of the two avenues we consider an inverter as discussion vehicle and evaluate the designs in terms of area and energy consumption. The GNR-based structure outperforms its counterparts by 15× up to 104× and 230× smaller delay and 6 to 7 and 4 orders of magnitude smaller power than the GNRFET-and GNRTFET- based designs, respectively. Moreover, when compared with CMOS 7 nm Boolean gates GNR-based desgns exhibit up to 6× smaller delay, and up to 2 orders of magnitude smaller active area, and total power consumption. Our analysis confirms that the alternative GNR-based design paradigm, which transcends the traditional switch based approach and takes better advantage of graphene intrinsicnproperties, is better suited for future carbon based nanoelectronics.
{"title":"On Effective Graphene Based Computing","authors":"N. C. Laurenciu, S. Cotofana","doi":"10.1109/SMICND.2018.8539757","DOIUrl":"https://doi.org/10.1109/SMICND.2018.8539757","url":null,"abstract":"With CMOS feature size heading towards atomic dimensions, unjustifiable static power, reliability, and economic implications are exacerbating, prompting for research on new materials, devices, and/or computation paradigms. Within this context, Graphene Nanoribbons (GNRs), owing to graphene's excellent electronic properties, may serve as basic blocks for carbon-based nanoelectronics. In this paper, we present the two main avenues, i.e., graphene FET- and GNR- based, undertaken towards graphene based computing. The first approach is conservative and focuses on the realization of graphene FET transistor based switches as MOSFET replacements to maintain the state of the art logic Boolean algebra paradigm design methodology. The second one follows a different line of thinking and seeks GNR-based structures able to provide more complex behaviours by making better use of graphene's conduction properties. We first discuss Graphene Nanoribbon (GNR) based field Effect Transistors (GNRFETs) and Tunnelling GNR based Transistors (GNRTFETs) and their utilization as underlying elements for Boolean gate implementations. Subsequently, we present GNR-based structures that can directly compute Boolean functions, e.g., NAND, XOR, by means of one GNR only and a way to complementary arrange them in energy effective gates. To get inside into the potential of the two avenues we consider an inverter as discussion vehicle and evaluate the designs in terms of area and energy consumption. The GNR-based structure outperforms its counterparts by 15× up to 104× and 230× smaller delay and 6 to 7 and 4 orders of magnitude smaller power than the GNRFET-and GNRTFET- based designs, respectively. Moreover, when compared with CMOS 7 nm Boolean gates GNR-based desgns exhibit up to 6× smaller delay, and up to 2 orders of magnitude smaller active area, and total power consumption. Our analysis confirms that the alternative GNR-based design paradigm, which transcends the traditional switch based approach and takes better advantage of graphene intrinsicnproperties, is better suited for future carbon based nanoelectronics.","PeriodicalId":247062,"journal":{"name":"2018 International Semiconductor Conference (CAS)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122417402","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-10-01DOI: 10.1109/smicnd.2018.8539784
CAS 2018 organized by National Institute for Research and Development in Microtechnologies - IMT Bucharest
由国家微技术研究与发展研究所-布加勒斯特IMT组织的CAS 2018
{"title":"CAS 2018 Organized by National Institute for Research and Development in Microtechnologies - IMT Bucharest","authors":"","doi":"10.1109/smicnd.2018.8539784","DOIUrl":"https://doi.org/10.1109/smicnd.2018.8539784","url":null,"abstract":"CAS 2018 organized by National Institute for Research and Development in Microtechnologies - IMT Bucharest","PeriodicalId":247062,"journal":{"name":"2018 International Semiconductor Conference (CAS)","volume":"90 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123103537","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-10-01DOI: 10.1109/SMICND.2018.8539803
G. Muscalu, B. Firtat, S. Dinulescu, C. Moldovan, Adrian Anghelescu, I. Stan
The purpose of this paper is the studying of an off the shelf solution for power harvesting and storage circuitry for a previously designed lead-free energy harvester. The energy harvester is designed to work at a resonant frequency of 460Hz and consists in a double array of piezoelectric cantilevers (2 × 10) using zinc oxide as a lead-free piezoelectric material. The energy from the harvester is processed by LTC3588, a nanopower energy harvesting power supply (Abstract).
{"title":"Power Harvesting and Storage Circuit for a Double Array of Lead-Free Piezoelectric Cantilevers","authors":"G. Muscalu, B. Firtat, S. Dinulescu, C. Moldovan, Adrian Anghelescu, I. Stan","doi":"10.1109/SMICND.2018.8539803","DOIUrl":"https://doi.org/10.1109/SMICND.2018.8539803","url":null,"abstract":"The purpose of this paper is the studying of an off the shelf solution for power harvesting and storage circuitry for a previously designed lead-free energy harvester. The energy harvester is designed to work at a resonant frequency of 460Hz and consists in a double array of piezoelectric cantilevers (2 × 10) using zinc oxide as a lead-free piezoelectric material. The energy from the harvester is processed by LTC3588, a nanopower energy harvesting power supply (Abstract).","PeriodicalId":247062,"journal":{"name":"2018 International Semiconductor Conference (CAS)","volume":"135 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115678603","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-10-01DOI: 10.1109/SMICND.2018.8539783
C. Oprea, A. Ndiaye, A. Trandafir, F. Cimpoesu, Mihai A. Cîrţu
We report results of a computational study to understand the dye regeneration mechanism of organic dyes in conjunction with cobalt(II) complexes. We are able to determine the parameters of Marcus' theory for electron transfer by means of density functional theory calculations of the energy in various dye-electrolyte configurations.
{"title":"Electron Transfer and Dye Regeneration in Dye-Sensitized Solar Cells","authors":"C. Oprea, A. Ndiaye, A. Trandafir, F. Cimpoesu, Mihai A. Cîrţu","doi":"10.1109/SMICND.2018.8539783","DOIUrl":"https://doi.org/10.1109/SMICND.2018.8539783","url":null,"abstract":"We report results of a computational study to understand the dye regeneration mechanism of organic dyes in conjunction with cobalt(II) complexes. We are able to determine the parameters of Marcus' theory for electron transfer by means of density functional theory calculations of the energy in various dye-electrolyte configurations.","PeriodicalId":247062,"journal":{"name":"2018 International Semiconductor Conference (CAS)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126821972","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-10-01DOI: 10.1109/SMICND.2018.8539762
M. Fanoro, S. S. Olokede, S. Sinha
This paper presents the impact of a singlewire degeneration microstrip transmission line (MTL) on the gain and noise figure of a millimeter wave low noise amplifier (LNA) at 60 GHz, designed using 0.13 μm SiGe BiCMOS technology. To accomplish this, the performance of the designed LNA is varied with and without the presence of singlewire degeneration MTL in a setup at the first stage of the LNA, using a common emitter transistor topology. Initial results show that the introduction of the singlewire degeneration MTL in the schematic resulted in a decrease in the gain and an increased noise figure of the LNA, while without the presence of a singlewire MTL, the common emitter transistor of the cascode configuration gave rise to a satisfactory increase in gain and reduced noise figure for the LNA. A maximum gain of 15.91 dB and a minimum noise figure of 6.74 dB were recorded when MTL was added to the LNA circuit, while a maximum gain of 20.84 dB and a minimum noise figure of 6.16 dB was recorded when the singlewire MTL was disconnected.
{"title":"Effect of Degeneration on a Millimeter Wave LNA: Application of Microstrip Transmission Lines","authors":"M. Fanoro, S. S. Olokede, S. Sinha","doi":"10.1109/SMICND.2018.8539762","DOIUrl":"https://doi.org/10.1109/SMICND.2018.8539762","url":null,"abstract":"This paper presents the impact of a singlewire degeneration microstrip transmission line (MTL) on the gain and noise figure of a millimeter wave low noise amplifier (LNA) at 60 GHz, designed using 0.13 μm SiGe BiCMOS technology. To accomplish this, the performance of the designed LNA is varied with and without the presence of singlewire degeneration MTL in a setup at the first stage of the LNA, using a common emitter transistor topology. Initial results show that the introduction of the singlewire degeneration MTL in the schematic resulted in a decrease in the gain and an increased noise figure of the LNA, while without the presence of a singlewire MTL, the common emitter transistor of the cascode configuration gave rise to a satisfactory increase in gain and reduced noise figure for the LNA. A maximum gain of 15.91 dB and a minimum noise figure of 6.74 dB were recorded when MTL was added to the LNA circuit, while a maximum gain of 20.84 dB and a minimum noise figure of 6.16 dB was recorded when the singlewire MTL was disconnected.","PeriodicalId":247062,"journal":{"name":"2018 International Semiconductor Conference (CAS)","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121774841","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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