Pub Date : 2011-12-01DOI: 10.1109/ICECS.2011.6122350
A. Mallat, P. Gérard, L. Vandendorpe
In this paper we present an impulse radio ultra wideband generator based on a field-programmable gate array with high-speed serial module. By defining a pattern of one bit set to “1” and remaining bits set to “0” we generate a monopulse. By defining multiple patterns accordingly we generate time-hopping waveforms for multi-users. In order to shape the generated monopulses, either we apply them directly to the transmit antenna or we combine the complementary outputs after shifting one of them. Some experimental results are shown.
{"title":"Multi-user time-hopping IR-UWB generator based on FPGA with high-speed serial module","authors":"A. Mallat, P. Gérard, L. Vandendorpe","doi":"10.1109/ICECS.2011.6122350","DOIUrl":"https://doi.org/10.1109/ICECS.2011.6122350","url":null,"abstract":"In this paper we present an impulse radio ultra wideband generator based on a field-programmable gate array with high-speed serial module. By defining a pattern of one bit set to “1” and remaining bits set to “0” we generate a monopulse. By defining multiple patterns accordingly we generate time-hopping waveforms for multi-users. In order to shape the generated monopulses, either we apply them directly to the transmit antenna or we combine the complementary outputs after shifting one of them. Some experimental results are shown.","PeriodicalId":251525,"journal":{"name":"2011 18th IEEE International Conference on Electronics, Circuits, and Systems","volume":"396 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114918275","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-01DOI: 10.1109/ICECS.2011.6122258
Sylvain Maréchal, F. Krummenacher, M. Kayal
This paper describes an optimal filter design procedure for a cascaded sigma-delta modulator, starting with a block schematic of a second-order topology and deriving step by step the optimal decoder. The presented filter enhances the resolution of the MASH ADC. The obtained resolution is compared to the classic linear filter.
{"title":"Optimal filtering of an incremental second-order MASH11 sigma-delta modulator","authors":"Sylvain Maréchal, F. Krummenacher, M. Kayal","doi":"10.1109/ICECS.2011.6122258","DOIUrl":"https://doi.org/10.1109/ICECS.2011.6122258","url":null,"abstract":"This paper describes an optimal filter design procedure for a cascaded sigma-delta modulator, starting with a block schematic of a second-order topology and deriving step by step the optimal decoder. The presented filter enhances the resolution of the MASH ADC. The obtained resolution is compared to the classic linear filter.","PeriodicalId":251525,"journal":{"name":"2011 18th IEEE International Conference on Electronics, Circuits, and Systems","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125803728","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-01DOI: 10.1109/ICECS.2011.6122339
Ye Zhang, N. Zimmermann, R. Wunderlich, S. Heinen
In this paper, a ring oscillator based fractional-N frequency synthesizer whose output frequency ranges from 600 MHz to 1.2 GHz is proposed. ΣΔ modulation is implemented to randomize the fractional spurs. The issues regarding a wide output frequency range are analyzed, and solved by the compensation and adaptive controlled architecture. Power and area optimization is also considered. The synthesizer was implemented in 65 nm CMOS. At 1 GHz output frequency, a phase noise performance of −107 dBc/Hz at 1 MHz offset and 5.3 ps rms jitter are achieved.
{"title":"A wide-frequency-range fractional-N synthesizer for clock generation in 65nm CMOS","authors":"Ye Zhang, N. Zimmermann, R. Wunderlich, S. Heinen","doi":"10.1109/ICECS.2011.6122339","DOIUrl":"https://doi.org/10.1109/ICECS.2011.6122339","url":null,"abstract":"In this paper, a ring oscillator based fractional-N frequency synthesizer whose output frequency ranges from 600 MHz to 1.2 GHz is proposed. ΣΔ modulation is implemented to randomize the fractional spurs. The issues regarding a wide output frequency range are analyzed, and solved by the compensation and adaptive controlled architecture. Power and area optimization is also considered. The synthesizer was implemented in 65 nm CMOS. At 1 GHz output frequency, a phase noise performance of −107 dBc/Hz at 1 MHz offset and 5.3 ps rms jitter are achieved.","PeriodicalId":251525,"journal":{"name":"2011 18th IEEE International Conference on Electronics, Circuits, and Systems","volume":"125 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126872787","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-01DOI: 10.1109/ICECS.2011.6122383
Efstathios Sotiriou-Xanthopoulos, D. Diamantopoulos, G. Economakos, D. Soudris
Reconfigurable computing is a cost-effective alternative to technology shrinking in order to achieve higher performance in digital design, especially considering run time reconfiguration. Research in the field consists of new reconfig-urable architectures, either coarse-grain or fine-grain, and new methodologies to map applications onto them. A special case of coarse-grain reconfigurable components are morphable multipliers, which use multiplexers to feed different inputs and form different connection schemes within the datapath of conventional multipliers. These connection schemes form different components that can be utilized when the initial multiplier is idle. Morphable components offer performance improvements but the use of extra multiplexers impose power overheads. This paper applies two low-power design techniques, power gating and multi Vth components, for the design of low-power morphable multipliers. Experimentation with these multipliers show that they can offer performance, area and power improvements compared to other alternative architectures, making them valuable building blocks for hardware synthesis.
{"title":"Design and experimentation with low-power morphable multipliers","authors":"Efstathios Sotiriou-Xanthopoulos, D. Diamantopoulos, G. Economakos, D. Soudris","doi":"10.1109/ICECS.2011.6122383","DOIUrl":"https://doi.org/10.1109/ICECS.2011.6122383","url":null,"abstract":"Reconfigurable computing is a cost-effective alternative to technology shrinking in order to achieve higher performance in digital design, especially considering run time reconfiguration. Research in the field consists of new reconfig-urable architectures, either coarse-grain or fine-grain, and new methodologies to map applications onto them. A special case of coarse-grain reconfigurable components are morphable multipliers, which use multiplexers to feed different inputs and form different connection schemes within the datapath of conventional multipliers. These connection schemes form different components that can be utilized when the initial multiplier is idle. Morphable components offer performance improvements but the use of extra multiplexers impose power overheads. This paper applies two low-power design techniques, power gating and multi Vth components, for the design of low-power morphable multipliers. Experimentation with these multipliers show that they can offer performance, area and power improvements compared to other alternative architectures, making them valuable building blocks for hardware synthesis.","PeriodicalId":251525,"journal":{"name":"2011 18th IEEE International Conference on Electronics, Circuits, and Systems","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126563871","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-01DOI: 10.1109/ICECS.2011.6122247
Chelho Chung, Young-Han Kim, Tae-Hun Ki, Kyusung Bae, Jongbae Kim
This paper presents a ultra low power 900 MHz RF transceiver IC. The IC harvests energy from 900 MHz RF carrier wave. The IC has −17 dBm minimum read operation power sensitivity. Analog function blocks, a digital baseband, and a memory system operate with 0.8 V ∼ 2.0 V supply voltage range without voltage regulator. Only current-starved ring oscillator operates 0.6 V with calibration. Most of analog blocks adopted low power subthreshold operating design. The memory system is chosen 512-bit Fowler-Nordheim tunneling non volatile memory (NVM). Digital baseband is designed to clock gating, clock recovery, balanced power distribution, and adaptive power consumption methodology. The transceiver IC is implemented in the 0.18-μm CMOS technology. The overall power consumption of designed IC is only 2.64 μW at 0.8 V supply voltage. The chip size is 0.65 mm × 0.65 mm.
本文设计了一种超低功耗900 MHz射频收发器集成电路，该集成电路从900 MHz射频载波中获取能量。IC的最小读操作功率灵敏度为−17dbm。模拟功能模块、数字基带和存储系统在0.8 V ~ 2.0 V供电电压范围内工作，不需要电压调节器。只有电流匮乏的环形振荡器工作0.6 V与校准。大部分模拟模块采用低功耗亚阈值工作设计。存储系统选用512位的Fowler-Nordheim隧道非易失性存储器(NVM)。数字基带被设计成时钟门控、时钟恢复、平衡功率分配和自适应功耗方法。收发器IC采用0.18 μm CMOS技术实现。在0.8 V电源电压下，设计的集成电路的总功耗仅为2.64 μW。芯片尺寸为0.65 mm × 0.65 mm。
{"title":"Fully integrated ultra-low-power 900 MHz RF transceiver for batteryless wireless microsystems","authors":"Chelho Chung, Young-Han Kim, Tae-Hun Ki, Kyusung Bae, Jongbae Kim","doi":"10.1109/ICECS.2011.6122247","DOIUrl":"https://doi.org/10.1109/ICECS.2011.6122247","url":null,"abstract":"This paper presents a ultra low power 900 MHz RF transceiver IC. The IC harvests energy from 900 MHz RF carrier wave. The IC has −17 dBm minimum read operation power sensitivity. Analog function blocks, a digital baseband, and a memory system operate with 0.8 V ∼ 2.0 V supply voltage range without voltage regulator. Only current-starved ring oscillator operates 0.6 V with calibration. Most of analog blocks adopted low power subthreshold operating design. The memory system is chosen 512-bit Fowler-Nordheim tunneling non volatile memory (NVM). Digital baseband is designed to clock gating, clock recovery, balanced power distribution, and adaptive power consumption methodology. The transceiver IC is implemented in the 0.18-μm CMOS technology. The overall power consumption of designed IC is only 2.64 μW at 0.8 V supply voltage. The chip size is 0.65 mm × 0.65 mm.","PeriodicalId":251525,"journal":{"name":"2011 18th IEEE International Conference on Electronics, Circuits, and Systems","volume":"308 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123626899","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-01DOI: 10.1109/ICECS.2011.6122244
A. Reis, J. F. Rocha, A. Gameiro, J. P. Carvalho
This work studies the effects of the prefilter bandwidth in the sequential symbol synchronizers based on pulse comparison at rate and positive quarter rate. We consider three prefilter bandwidths namely B1=∞, B2=2.tx and B3=1.tx, where tx is the bit rate. The synchronizer has two variants one operating by both transitions at bit rate and other operating by positive transitions at quarter rate. Each variant has two versions namely the manual and the automatic. The objective is to study the prefilter bandwidth with four synchronizers and to evaluate their output jitter UIRMS (Unit Interval Root Mean Square) versus input SNR (Signal Noise Ratio).
{"title":"Prefilter bandwidth effects in sequential symbol synchronizers based on pulse comparison operating by positive transitions at quarter rate","authors":"A. Reis, J. F. Rocha, A. Gameiro, J. P. Carvalho","doi":"10.1109/ICECS.2011.6122244","DOIUrl":"https://doi.org/10.1109/ICECS.2011.6122244","url":null,"abstract":"This work studies the effects of the prefilter bandwidth in the sequential symbol synchronizers based on pulse comparison at rate and positive quarter rate. We consider three prefilter bandwidths namely B1=∞, B2=2.tx and B3=1.tx, where tx is the bit rate. The synchronizer has two variants one operating by both transitions at bit rate and other operating by positive transitions at quarter rate. Each variant has two versions namely the manual and the automatic. The objective is to study the prefilter bandwidth with four synchronizers and to evaluate their output jitter UIRMS (Unit Interval Root Mean Square) versus input SNR (Signal Noise Ratio).","PeriodicalId":251525,"journal":{"name":"2011 18th IEEE International Conference on Electronics, Circuits, and Systems","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131355257","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-01DOI: 10.1109/ICECS.2011.6122264
M. Elsayed, F. Nabki, M. El-Gamal
This paper reports on the design and suggested fabrication steps of a bulk mode dodecagon disk gyroscope. A major contribution of this work, compared to prior art, is that it enables the fabrication of this important class of gyroscopes in commercially available and low-cost SOI technologies — e.g. MEMSCAP's SOIMUMPs. The structure was simulated using COMSOL, operates at 8.14 MHz, and exhibits a competitive rate sensitivity of ∼2.3 pA/°/s, a high dynamic range of 2000°/s, and a mechanical noise of 1°/√hr, for a quality factor of 10,000.
{"title":"A 2000°/s dynamic range bulk mode dodecagon gyro for a commercial SOI technology","authors":"M. Elsayed, F. Nabki, M. El-Gamal","doi":"10.1109/ICECS.2011.6122264","DOIUrl":"https://doi.org/10.1109/ICECS.2011.6122264","url":null,"abstract":"This paper reports on the design and suggested fabrication steps of a bulk mode dodecagon disk gyroscope. A major contribution of this work, compared to prior art, is that it enables the fabrication of this important class of gyroscopes in commercially available and low-cost SOI technologies — e.g. MEMSCAP's SOIMUMPs. The structure was simulated using COMSOL, operates at 8.14 MHz, and exhibits a competitive rate sensitivity of ∼2.3 pA/°/s, a high dynamic range of 2000°/s, and a mechanical noise of 1°/√hr, for a quality factor of 10,000.","PeriodicalId":251525,"journal":{"name":"2011 18th IEEE International Conference on Electronics, Circuits, and Systems","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126479708","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-01DOI: 10.1109/ICECS.2011.6122317
M. M. Silva, J. Swart, L. C. Moreira, W. Noije
This paper presents a CMOS pixel motion detector based on an current-mode APS (Active Pixel Sensor) topology using standard 0.35μm CMOS process. We propose a design with transmission gate to control two copier cells to compare different integration time. The pixel output is a differential current signal proportional to the difference between the two current copier cells level. The whole circuit has been simulated using LTSpice and the results had demonstrated the circuit capability to operate as a motion detector. Simulations show an average power consumption of 99nW per pixel respectively at 3.3V power supply voltage. The complete circuit pixel occupies a very small area of 33μm ×73μm.
{"title":"Current-mode motion detector sensor using copier cell in CMOS technology","authors":"M. M. Silva, J. Swart, L. C. Moreira, W. Noije","doi":"10.1109/ICECS.2011.6122317","DOIUrl":"https://doi.org/10.1109/ICECS.2011.6122317","url":null,"abstract":"This paper presents a CMOS pixel motion detector based on an current-mode APS (Active Pixel Sensor) topology using standard 0.35μm CMOS process. We propose a design with transmission gate to control two copier cells to compare different integration time. The pixel output is a differential current signal proportional to the difference between the two current copier cells level. The whole circuit has been simulated using LTSpice and the results had demonstrated the circuit capability to operate as a motion detector. Simulations show an average power consumption of 99nW per pixel respectively at 3.3V power supply voltage. The complete circuit pixel occupies a very small area of 33μm ×73μm.","PeriodicalId":251525,"journal":{"name":"2011 18th IEEE International Conference on Electronics, Circuits, and Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131689245","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-01DOI: 10.1109/ICECS.2011.6122325
A. Hussaini, R. Abd‐Alhameed, Jonathan Rodriguez
Without a holistic design and fabrication approach, future wireless communication devices would be extremely large in size to accommodate multiple radio access technologies (RATs) compared to today's more conventional mono-mode devices. Typically multiple RAT devices will be comprised of multiple RF power amplifiers, low noise amplifiers (LNA), RF band pass filters, modulators and demodulators; one for each wireless technology. Obviously, this will increase the complexity of the circuit design and will cover a large part of the circuit space leading to power hungry devices. Radio frequency microelectromechanical systems (RF-MEMS) can be good candidate for innovative RF front end devices since it is reconfigurable features in nature therefore allowing a reduction in the number of external components in a single device for the use of multiple RATs. This paper discusses the history, state of the art of tunable RF filter and beyond.
{"title":"Tunable RF filters: Survey and beyond","authors":"A. Hussaini, R. Abd‐Alhameed, Jonathan Rodriguez","doi":"10.1109/ICECS.2011.6122325","DOIUrl":"https://doi.org/10.1109/ICECS.2011.6122325","url":null,"abstract":"Without a holistic design and fabrication approach, future wireless communication devices would be extremely large in size to accommodate multiple radio access technologies (RATs) compared to today's more conventional mono-mode devices. Typically multiple RAT devices will be comprised of multiple RF power amplifiers, low noise amplifiers (LNA), RF band pass filters, modulators and demodulators; one for each wireless technology. Obviously, this will increase the complexity of the circuit design and will cover a large part of the circuit space leading to power hungry devices. Radio frequency microelectromechanical systems (RF-MEMS) can be good candidate for innovative RF front end devices since it is reconfigurable features in nature therefore allowing a reduction in the number of external components in a single device for the use of multiple RATs. This paper discusses the history, state of the art of tunable RF filter and beyond.","PeriodicalId":251525,"journal":{"name":"2011 18th IEEE International Conference on Electronics, Circuits, and Systems","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124637750","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-01DOI: 10.1109/ICECS.2011.6122280
P. Jamshidi, S. Naseh
This paper presents a 3–9 GHz CMOS low noise amplifier (LNA) designed in a 0.18 μm CMOS technology which uses negative feedback with magnetic coupling at the input of a common source-LNA instead of resistive feedback. Using the proposed topology, power gain of 14.1±1 dB and noise figure between 2.24–2.45 dB was achieved in a bandwidth (BW) of 3–9 GHz. The total drawn power of the proposed circuit from a 1.5-V power supply is 5.1 mW, while the input and output matching criteria are well satisfied. The values of all elements were determined using genetic algorithms.
{"title":"Wideband LNA with reactive feedback at the input matching network","authors":"P. Jamshidi, S. Naseh","doi":"10.1109/ICECS.2011.6122280","DOIUrl":"https://doi.org/10.1109/ICECS.2011.6122280","url":null,"abstract":"This paper presents a 3–9 GHz CMOS low noise amplifier (LNA) designed in a 0.18 μm CMOS technology which uses negative feedback with magnetic coupling at the input of a common source-LNA instead of resistive feedback. Using the proposed topology, power gain of 14.1±1 dB and noise figure between 2.24–2.45 dB was achieved in a bandwidth (BW) of 3–9 GHz. The total drawn power of the proposed circuit from a 1.5-V power supply is 5.1 mW, while the input and output matching criteria are well satisfied. The values of all elements were determined using genetic algorithms.","PeriodicalId":251525,"journal":{"name":"2011 18th IEEE International Conference on Electronics, Circuits, and Systems","volume":"54 11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130876412","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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