Pub Date : 2011-12-01DOI: 10.1109/ICECS.2011.6122380
Gerson Scartezzini, R. Reis
Optimization of circuits to reduce power consumption is more and more important. Techniques to reduce power at architectural level are not sufficient to minimize the impact of power consumption in modern designs, using nano CMOS technologies. Classical standard cells methodology is widely used in digital designs. However it is far away of power optimization at physical design level. It is becoming necessary the establishment of a new physical design methodology to improve power reduction, mainly due to the leakage power increase. It is needed a methodology to allow the automatic generation of the layout of any logic function. The method should also optimize the circuit as much as possible. Considering this, the paper is focused in showing that the use of transistors networks gives a better solution in terms of power and delay than the traditional approach of using predesigned cells available in commercial standard cell libraries. The presented comparisons show an average reduction of 74% in leakage power and 21% in delay.
{"title":"Power consumption in transistor networks versus in standard cells","authors":"Gerson Scartezzini, R. Reis","doi":"10.1109/ICECS.2011.6122380","DOIUrl":"https://doi.org/10.1109/ICECS.2011.6122380","url":null,"abstract":"Optimization of circuits to reduce power consumption is more and more important. Techniques to reduce power at architectural level are not sufficient to minimize the impact of power consumption in modern designs, using nano CMOS technologies. Classical standard cells methodology is widely used in digital designs. However it is far away of power optimization at physical design level. It is becoming necessary the establishment of a new physical design methodology to improve power reduction, mainly due to the leakage power increase. It is needed a methodology to allow the automatic generation of the layout of any logic function. The method should also optimize the circuit as much as possible. Considering this, the paper is focused in showing that the use of transistors networks gives a better solution in terms of power and delay than the traditional approach of using predesigned cells available in commercial standard cell libraries. The presented comparisons show an average reduction of 74% in leakage power and 21% in delay.","PeriodicalId":251525,"journal":{"name":"2011 18th IEEE International Conference on Electronics, Circuits, and Systems","volume":"122 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133931077","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-01DOI: 10.1109/ICECS.2011.6122241
N. El-Kork, R. Shubair, P. Moretti, B. Jacquier
We report Near Field Optical Microscopy and spectroscopy of hybrid nanoparticles. They exhibit luminescence properties suitable for their use as biological markers. A direct application is demonstrated: Hybrid Nanoparticle Biosensors.
{"title":"Hybrid nanoparticle biomarkers in Near-Field Optical Microscopy","authors":"N. El-Kork, R. Shubair, P. Moretti, B. Jacquier","doi":"10.1109/ICECS.2011.6122241","DOIUrl":"https://doi.org/10.1109/ICECS.2011.6122241","url":null,"abstract":"We report Near Field Optical Microscopy and spectroscopy of hybrid nanoparticles. They exhibit luminescence properties suitable for their use as biological markers. A direct application is demonstrated: Hybrid Nanoparticle Biosensors.","PeriodicalId":251525,"journal":{"name":"2011 18th IEEE International Conference on Electronics, Circuits, and Systems","volume":"238 ","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133969728","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-01DOI: 10.1109/ICECS.2011.6122289
Yiming Li, Yi Li, Mingtian Zhou
Given a LB-compact floorplan, it is obvious that we can get other floorplans with the same topology and area but different wire length by the white space distribution. In this paper, a greedy algorithm is proposed for wire length optimization. We derive significant conditions to identify the moving ranges of movable blocks. The moving cost tree is constructed. The maximum reduction on total half-perimeter wire length (HPWL) and offset for each block can be evaluated. Experimental results show that the greedy algorithm is effectively.
{"title":"A greedy algorithm for wire length optimization","authors":"Yiming Li, Yi Li, Mingtian Zhou","doi":"10.1109/ICECS.2011.6122289","DOIUrl":"https://doi.org/10.1109/ICECS.2011.6122289","url":null,"abstract":"Given a LB-compact floorplan, it is obvious that we can get other floorplans with the same topology and area but different wire length by the white space distribution. In this paper, a greedy algorithm is proposed for wire length optimization. We derive significant conditions to identify the moving ranges of movable blocks. The moving cost tree is constructed. The maximum reduction on total half-perimeter wire length (HPWL) and offset for each block can be evaluated. Experimental results show that the greedy algorithm is effectively.","PeriodicalId":251525,"journal":{"name":"2011 18th IEEE International Conference on Electronics, Circuits, and Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129466019","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-01DOI: 10.1109/ICECS.2011.6122225
R. Cellier, G. Pillonnet, N. Abouchi, R. M'Rad, A. Nagari
Analog input Class D Amplifiers are widely used in battery powered systems such as mobile phones to achieve high efficiency but it suffers from a complex DAC to convert the digital audio signal into an analog one. To increase the playback time, this paper presents digital input class D amplifiers using digital modulation. The proposed Class D amplifier is also controlled using an analog loop to achieve a good power supply immunity and low harmonic distortion. Usual AC analysis of this loop cannot be done due to its switching behavior. Very long transient simulation was the only solution to predict the dynamics performances of the control. To overcome this issue, the presented work includes a modeling method in order to study faster the control performances. The proposed modeling is then used to increase the audio quality reproduction of our digital input Class D amplifier. The complete audio path is implemented in CMOS 130nm process and characterized in order to validate the architecture, the modeling method and the integrated design.
{"title":"Analysis and design of an analog control loop for digital input class D amplifiers","authors":"R. Cellier, G. Pillonnet, N. Abouchi, R. M'Rad, A. Nagari","doi":"10.1109/ICECS.2011.6122225","DOIUrl":"https://doi.org/10.1109/ICECS.2011.6122225","url":null,"abstract":"Analog input Class D Amplifiers are widely used in battery powered systems such as mobile phones to achieve high efficiency but it suffers from a complex DAC to convert the digital audio signal into an analog one. To increase the playback time, this paper presents digital input class D amplifiers using digital modulation. The proposed Class D amplifier is also controlled using an analog loop to achieve a good power supply immunity and low harmonic distortion. Usual AC analysis of this loop cannot be done due to its switching behavior. Very long transient simulation was the only solution to predict the dynamics performances of the control. To overcome this issue, the presented work includes a modeling method in order to study faster the control performances. The proposed modeling is then used to increase the audio quality reproduction of our digital input Class D amplifier. The complete audio path is implemented in CMOS 130nm process and characterized in order to validate the architecture, the modeling method and the integrated design.","PeriodicalId":251525,"journal":{"name":"2011 18th IEEE International Conference on Electronics, Circuits, and Systems","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129833393","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-01DOI: 10.1109/ICECS.2011.6122255
Abderrezak Marzaki, V. Bidal, R. Laffont, W. Rahajandraibe, J. Portal, R. Bouchakour
A new DCG-FGT (Dual-Control-Gate Floating-Gate Transistor) transistor model for static and transient simulations is presented. The PSP MOS description is used as a basis for the formulation of the conduction channel behavior. The floating gate potential is implicitly computed with an added charge neutrality relation that ensures a good convergence. The model is running under electrical simulator (ELDO) and is characterized thanks to ICCAP software. It has been validated on an advanced STMicroelectronics technology. The final objective of this work is to provide an accurate and scalable model available in design framework.
{"title":"PSP based DCG-FGT transistor model including characterization procedure","authors":"Abderrezak Marzaki, V. Bidal, R. Laffont, W. Rahajandraibe, J. Portal, R. Bouchakour","doi":"10.1109/ICECS.2011.6122255","DOIUrl":"https://doi.org/10.1109/ICECS.2011.6122255","url":null,"abstract":"A new DCG-FGT (Dual-Control-Gate Floating-Gate Transistor) transistor model for static and transient simulations is presented. The PSP MOS description is used as a basis for the formulation of the conduction channel behavior. The floating gate potential is implicitly computed with an added charge neutrality relation that ensures a good convergence. The model is running under electrical simulator (ELDO) and is characterized thanks to ICCAP software. It has been validated on an advanced STMicroelectronics technology. The final objective of this work is to provide an accurate and scalable model available in design framework.","PeriodicalId":251525,"journal":{"name":"2011 18th IEEE International Conference on Electronics, Circuits, and Systems","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116825978","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-01DOI: 10.1109/ICECS.2011.6122302
B. Zeinali, M. Yavari
A new digital background calibration algorithm for pipelined analog-to-digital converters is proposed in this paper. It is based on error estimation with non-precision calibration signals for foreground correction and a modified split structure for converting the foreground structure to the background one. This architecture allows improving the calibration signals accuracy contrarily to linear gain error coefficient, while the modified split structure does not need matching between the two channels. The presented algorithm is investigated in system level in MATLAB for a 12-bit pipelined ADC. It achieves an improvement equal to 36.5 dB and 44.5 dB for SNDR and SFDR, respectively where the input signal frequency is 39 MHz with a 100 MHz sampling frequency.
{"title":"A new digital background correction algorithm with non-precision calibration signals for pipelined ADCs","authors":"B. Zeinali, M. Yavari","doi":"10.1109/ICECS.2011.6122302","DOIUrl":"https://doi.org/10.1109/ICECS.2011.6122302","url":null,"abstract":"A new digital background calibration algorithm for pipelined analog-to-digital converters is proposed in this paper. It is based on error estimation with non-precision calibration signals for foreground correction and a modified split structure for converting the foreground structure to the background one. This architecture allows improving the calibration signals accuracy contrarily to linear gain error coefficient, while the modified split structure does not need matching between the two channels. The presented algorithm is investigated in system level in MATLAB for a 12-bit pipelined ADC. It achieves an improvement equal to 36.5 dB and 44.5 dB for SNDR and SFDR, respectively where the input signal frequency is 39 MHz with a 100 MHz sampling frequency.","PeriodicalId":251525,"journal":{"name":"2011 18th IEEE International Conference on Electronics, Circuits, and Systems","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133524957","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-01DOI: 10.1109/ICECS.2011.6122342
M. Tormos, C. Tanougast, A. Dandache, P. Bretillon, P. Kasser
In this paper, we evaluate the performances of distributed Tarokh Space Frequency Block Coding (SFBC) compared to classical Single Frequency Network (SFN) and Distributed Alamouti MISO with SFN (MISO-SFN) for the emerging second generation digital TV Broadcasting (DVB-T2). We showed the performance of SFN and Alamouti MISO-SFN for two, three and four transmitters for DVB-T2 chain. We also compared the performances of distributed Tarokh MISO compared to SFN and Alamouti MISO-SFN for three transmitters in OFDM transmission with LDPC and BCH coding to be similar as DVB-T2 chain. The results showed clearly that the distributed Tarokh diversity can be used to improve the DVB-T2 network of three antennas and more.
{"title":"Performance evaluation of distributed Tarokh SFBC and Alamouti MISO for SFN DVB-T2 broadcast networks","authors":"M. Tormos, C. Tanougast, A. Dandache, P. Bretillon, P. Kasser","doi":"10.1109/ICECS.2011.6122342","DOIUrl":"https://doi.org/10.1109/ICECS.2011.6122342","url":null,"abstract":"In this paper, we evaluate the performances of distributed Tarokh Space Frequency Block Coding (SFBC) compared to classical Single Frequency Network (SFN) and Distributed Alamouti MISO with SFN (MISO-SFN) for the emerging second generation digital TV Broadcasting (DVB-T2). We showed the performance of SFN and Alamouti MISO-SFN for two, three and four transmitters for DVB-T2 chain. We also compared the performances of distributed Tarokh MISO compared to SFN and Alamouti MISO-SFN for three transmitters in OFDM transmission with LDPC and BCH coding to be similar as DVB-T2 chain. The results showed clearly that the distributed Tarokh diversity can be used to improve the DVB-T2 network of three antennas and more.","PeriodicalId":251525,"journal":{"name":"2011 18th IEEE International Conference on Electronics, Circuits, and Systems","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129348921","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-01DOI: 10.1109/ICECS.2011.6122261
Qingyun Ma, M. Haider, Y. Massoud
Ubiquitous monitoring of sensor data and long term reliable operation of sensor units have been studied extensively either for environmental monitoring or for biomedical applications. Long term operation of sensor units requires continuous wireless signal at the output. The proposed rectifier unit is designed and simulated using 0.5-μm standard CMOS process. Simulation results show that power supply from an external source to avoid unwieldy wires or periodic battery replacements. Inductive-power transfer, as a suitable way of driving the sensor electronics, needs a high efficiency rectifier unit to convert the harvested wireless energy into a usable DC level. However, conventional full-wave bridge rectifier with a lower output voltage and a significant power loss lowers the overall efficiency of the inductive-link system. In this paper, a class-E type zero-voltage-switching structure is presented to achieve a high efficiency rectifier circuit. The symmetrical differential class-E switching structures are driven by differential AC signals that result in a low-loss full-wave rectified the proposed rectifier circuit can achieve more than 76% power conversion efficiency for an input AC signal of 7 MHz frequency with signal amplitude of 2 V (peak).
{"title":"Power-loss reduction of a MOSFET cross-coupled rectifier by employing zero-voltage switching","authors":"Qingyun Ma, M. Haider, Y. Massoud","doi":"10.1109/ICECS.2011.6122261","DOIUrl":"https://doi.org/10.1109/ICECS.2011.6122261","url":null,"abstract":"Ubiquitous monitoring of sensor data and long term reliable operation of sensor units have been studied extensively either for environmental monitoring or for biomedical applications. Long term operation of sensor units requires continuous wireless signal at the output. The proposed rectifier unit is designed and simulated using 0.5-μm standard CMOS process. Simulation results show that power supply from an external source to avoid unwieldy wires or periodic battery replacements. Inductive-power transfer, as a suitable way of driving the sensor electronics, needs a high efficiency rectifier unit to convert the harvested wireless energy into a usable DC level. However, conventional full-wave bridge rectifier with a lower output voltage and a significant power loss lowers the overall efficiency of the inductive-link system. In this paper, a class-E type zero-voltage-switching structure is presented to achieve a high efficiency rectifier circuit. The symmetrical differential class-E switching structures are driven by differential AC signals that result in a low-loss full-wave rectified the proposed rectifier circuit can achieve more than 76% power conversion efficiency for an input AC signal of 7 MHz frequency with signal amplitude of 2 V (peak).","PeriodicalId":251525,"journal":{"name":"2011 18th IEEE International Conference on Electronics, Circuits, and Systems","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125229658","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-01DOI: 10.1109/ICECS.2011.6122265
Jean Marie Darmanin, I. Grech, E. Gatt, O. Casha
The miniaturisation and reduction in cost of acceleration sensors led to the increase of use of said sensors in a large number of devices. Such include: Inertial Measurement Units (IMUs), air-bag deployment mechanism and consumer electronic devices. This paper presents three alternative designs of capacitive sensing MEMS 2-axis accelerometers. All designs have a common fabrication process but each design features different characteristics in terms of spring design and layout. A novel design methodology was devised such that the three designs have approximately the same characteristics such that cross-comparisons can be done. The resonant frequency was designed to be about 1.5 kHz and the accelerometers have a sensitivity of 400 aF/ms−2. Behavioural Model Simulations using Saber® Simulator and Finite Element Method (FEM) analysis were performed on these three designs. A comparison between the two different types of simulators was performed. This resulted in the conclusion that both simulators have comparable results and the variation between theoretical and simulation results can be attributed to the assumptions and inaccuracies of the mathematical model used in the theoretical computation.
{"title":"Design of a 2-axis MEMS accelerometer","authors":"Jean Marie Darmanin, I. Grech, E. Gatt, O. Casha","doi":"10.1109/ICECS.2011.6122265","DOIUrl":"https://doi.org/10.1109/ICECS.2011.6122265","url":null,"abstract":"The miniaturisation and reduction in cost of acceleration sensors led to the increase of use of said sensors in a large number of devices. Such include: Inertial Measurement Units (IMUs), air-bag deployment mechanism and consumer electronic devices. This paper presents three alternative designs of capacitive sensing MEMS 2-axis accelerometers. All designs have a common fabrication process but each design features different characteristics in terms of spring design and layout. A novel design methodology was devised such that the three designs have approximately the same characteristics such that cross-comparisons can be done. The resonant frequency was designed to be about 1.5 kHz and the accelerometers have a sensitivity of 400 aF/ms−2. Behavioural Model Simulations using Saber® Simulator and Finite Element Method (FEM) analysis were performed on these three designs. A comparison between the two different types of simulators was performed. This resulted in the conclusion that both simulators have comparable results and the variation between theoretical and simulation results can be attributed to the assumptions and inaccuracies of the mathematical model used in the theoretical computation.","PeriodicalId":251525,"journal":{"name":"2011 18th IEEE International Conference on Electronics, Circuits, and Systems","volume":"121 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127283035","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-01DOI: 10.1109/ICECS.2011.6122275
Vikas Singal, Y. Massoud
The random demodulator architecture is a compressive sensing based receiver that allows the reconstruction of frequency-sparse signals from measurements acquired at a rate below the signal's Nyquist rate. This in turn results in tremendous power savings in receivers because of the direct correlation between the power consumption of analog-to-digital converters (ADCs) in communication receivers and the sampling rate at which these ADCs operate. In this paper, we propose a random demodulator with a software-based integrator resetting scheme that does not use a switch to reset the integrator as in the conventional random demodulator system, but rather modifies the random signal so that the integrator is reset by zeroing the input. We show that the proposed system is equivalent to the conventional random demodulator, but is more practical to implement because of the many artifacts presented by switches.
{"title":"A random demodulator with a software-based integrator resetting scheme","authors":"Vikas Singal, Y. Massoud","doi":"10.1109/ICECS.2011.6122275","DOIUrl":"https://doi.org/10.1109/ICECS.2011.6122275","url":null,"abstract":"The random demodulator architecture is a compressive sensing based receiver that allows the reconstruction of frequency-sparse signals from measurements acquired at a rate below the signal's Nyquist rate. This in turn results in tremendous power savings in receivers because of the direct correlation between the power consumption of analog-to-digital converters (ADCs) in communication receivers and the sampling rate at which these ADCs operate. In this paper, we propose a random demodulator with a software-based integrator resetting scheme that does not use a switch to reset the integrator as in the conventional random demodulator system, but rather modifies the random signal so that the integrator is reset by zeroing the input. We show that the proposed system is equivalent to the conventional random demodulator, but is more practical to implement because of the many artifacts presented by switches.","PeriodicalId":251525,"journal":{"name":"2011 18th IEEE International Conference on Electronics, Circuits, and Systems","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128916986","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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