Pub Date : 2011-12-01DOI: 10.1109/ICECS.2011.6122297
S. Adami, N. Degrenne, C. Vollaire, B. Allard, F. Buret, F. Costa
In this paper, an ultra-low voltage and power DC/DC converter is presented. This converter harvests energy from a Microbial Fuel Cell (MFC) in order to feed another circuit such as an autonomous wireless sensor. The MFC behaves as a voltage generator of 475mV open-circuit voltage with a 600Ω serial internal impedance. The maximum delivered power is therefore around 100μW. The DC/DC converter provides output voltage in the range 2–7.5V and performs impedance matching with source. The converter achieves when associated with the MFC, 60% peak efficiency. Furthermore, this DC/DC converter is self-operating without the need for external power source of start-up assistance.
{"title":"Autonomous ultra-low power DC/DC converter for Microbial Fuel Cells","authors":"S. Adami, N. Degrenne, C. Vollaire, B. Allard, F. Buret, F. Costa","doi":"10.1109/ICECS.2011.6122297","DOIUrl":"https://doi.org/10.1109/ICECS.2011.6122297","url":null,"abstract":"In this paper, an ultra-low voltage and power DC/DC converter is presented. This converter harvests energy from a Microbial Fuel Cell (MFC) in order to feed another circuit such as an autonomous wireless sensor. The MFC behaves as a voltage generator of 475mV open-circuit voltage with a 600Ω serial internal impedance. The maximum delivered power is therefore around 100μW. The DC/DC converter provides output voltage in the range 2–7.5V and performs impedance matching with source. The converter achieves when associated with the MFC, 60% peak efficiency. Furthermore, this DC/DC converter is self-operating without the need for external power source of start-up assistance.","PeriodicalId":251525,"journal":{"name":"2011 18th IEEE International Conference on Electronics, Circuits, and Systems","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134266916","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-01DOI: 10.1109/ICECS.2011.6122271
Karim Eduardo Hay Alonso, A. Harb, L. Martínez
This article considers a bidirectional converter topology based on active dual-bridge topology. It proposes a modulation strategy required for power factor correction and presents results obtained in an implementation.
{"title":"Modulation characteristics for a bidirectional AC-DC converter based on dual active bridge (January 2010)","authors":"Karim Eduardo Hay Alonso, A. Harb, L. Martínez","doi":"10.1109/ICECS.2011.6122271","DOIUrl":"https://doi.org/10.1109/ICECS.2011.6122271","url":null,"abstract":"This article considers a bidirectional converter topology based on active dual-bridge topology. It proposes a modulation strategy required for power factor correction and presents results obtained in an implementation.","PeriodicalId":251525,"journal":{"name":"2011 18th IEEE International Conference on Electronics, Circuits, and Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122354776","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-01DOI: 10.1109/ICECS.2011.6122361
A. Samir, E. Kussener, W. Rahajandraibe, L. Girardeau, Y. Bert, H. Barthélemy
A low power voltage reference generator operating with a supply voltage ranging from 1.6V to 3.6V has been implemented in a 90-nm standard CMOS process. The reference is based on MOSFETs that are biased in the weak inversion region to consume nanowatts of power and uses no resistors. The maximum supply current at 3.6V and at 125°C is 173nA. It provides an 771mV voltage reference. A temperature coefficient of 7.5ppm/°C is achieved at best and 39.5ppm/°C on average, in a range from −40 to 125°C, as the combined effect of a suppression of the temperature dependence of mobility and the compensation of the threshold voltage temperature variation. The total block area is 0.03mm2.
{"title":"A 90-nm CMOS resistor-free compact trimmable voltage reference for ultra-low power low cost applications","authors":"A. Samir, E. Kussener, W. Rahajandraibe, L. Girardeau, Y. Bert, H. Barthélemy","doi":"10.1109/ICECS.2011.6122361","DOIUrl":"https://doi.org/10.1109/ICECS.2011.6122361","url":null,"abstract":"A low power voltage reference generator operating with a supply voltage ranging from 1.6V to 3.6V has been implemented in a 90-nm standard CMOS process. The reference is based on MOSFETs that are biased in the weak inversion region to consume nanowatts of power and uses no resistors. The maximum supply current at 3.6V and at 125°C is 173nA. It provides an 771mV voltage reference. A temperature coefficient of 7.5ppm/°C is achieved at best and 39.5ppm/°C on average, in a range from −40 to 125°C, as the combined effect of a suppression of the temperature dependence of mobility and the compensation of the threshold voltage temperature variation. The total block area is 0.03mm2.","PeriodicalId":251525,"journal":{"name":"2011 18th IEEE International Conference on Electronics, Circuits, and Systems","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122355323","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-01DOI: 10.1109/ICECS.2011.6122352
Amirhossein Ansari, M. Yavari
In this paper, a new full on-chip CMOS low-noise amplifier (LNA) topology for the range of 50 MHz to 10 GHz is introduced that has very low power consumption. It exploits the combination of a common-gate (CG) stage for wideband input matching and a common-source (CS) stage for canceling the noise and distortion of CG stage. Moreover the CS stage used both nMOS and pMOS transistors to improve the IIP2. Simulated in a 90 nm RF CMOS technology, the proposed LNA achieves a noise figure of 2.3 dB to 2.8 dB and input return loss (S11) less than −10 dB over whole the bandwidth while consumes only 6 mW from a 1 V power supply. The average of the power gain (S21) is 12 dB. The achieved IIP3 and IIP2 are about −5 dBm and 20 dBm, respectively.
{"title":"A very wideband low noise amplifier for cognitive radios","authors":"Amirhossein Ansari, M. Yavari","doi":"10.1109/ICECS.2011.6122352","DOIUrl":"https://doi.org/10.1109/ICECS.2011.6122352","url":null,"abstract":"In this paper, a new full on-chip CMOS low-noise amplifier (LNA) topology for the range of 50 MHz to 10 GHz is introduced that has very low power consumption. It exploits the combination of a common-gate (CG) stage for wideband input matching and a common-source (CS) stage for canceling the noise and distortion of CG stage. Moreover the CS stage used both nMOS and pMOS transistors to improve the IIP2. Simulated in a 90 nm RF CMOS technology, the proposed LNA achieves a noise figure of 2.3 dB to 2.8 dB and input return loss (S11) less than −10 dB over whole the bandwidth while consumes only 6 mW from a 1 V power supply. The average of the power gain (S21) is 12 dB. The achieved IIP3 and IIP2 are about −5 dBm and 20 dBm, respectively.","PeriodicalId":251525,"journal":{"name":"2011 18th IEEE International Conference on Electronics, Circuits, and Systems","volume":"878 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123029457","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-01DOI: 10.1109/ICECS.2011.6122303
Vikas Singal, S. Smaili, Y. Massoud
The theory of compressive sensing has recently been utilized to develop sub-Nyquist communication receivers that can reconstruct the input signal using sub-Nyquist sampling rates. Such samples are acquired randomly by projecting the input signal on random signals. Practically, these random signals can be generated by digital pseudo random signal generators, and the properties of these signals highly affect the reconstruction quality of the receiver. In this paper, we study the performance of the random demodulator, a compressive sampling based receiver, with two types of random sequences that are practical to implement: M-sequences generated by means of a linear feedback shift register, and Kasami sequences. We show that a random demodulator with a Kasami sequence generally outperforms that with an M-sequence in terms of minimum sampling rate and minimum sparsity levels for successful reconstruction.
{"title":"Performance analysis of random demodulators with M-sequences and Kasami sequences","authors":"Vikas Singal, S. Smaili, Y. Massoud","doi":"10.1109/ICECS.2011.6122303","DOIUrl":"https://doi.org/10.1109/ICECS.2011.6122303","url":null,"abstract":"The theory of compressive sensing has recently been utilized to develop sub-Nyquist communication receivers that can reconstruct the input signal using sub-Nyquist sampling rates. Such samples are acquired randomly by projecting the input signal on random signals. Practically, these random signals can be generated by digital pseudo random signal generators, and the properties of these signals highly affect the reconstruction quality of the receiver. In this paper, we study the performance of the random demodulator, a compressive sampling based receiver, with two types of random sequences that are practical to implement: M-sequences generated by means of a linear feedback shift register, and Kasami sequences. We show that a random demodulator with a Kasami sequence generally outperforms that with an M-sequence in terms of minimum sampling rate and minimum sparsity levels for successful reconstruction.","PeriodicalId":251525,"journal":{"name":"2011 18th IEEE International Conference on Electronics, Circuits, and Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128510863","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-01DOI: 10.1109/ICECS.2011.6122386
Nadine Abdallah, Audrey Queudet, M. Chetto, R. H. Chehade
In this paper we study the partitioned EDF scheduling in a homogeneous multiprocessor environment with Quality of Service (QoS) constraints. The system considered here is a real-time multiprocessor system assumed to be powered by rechargeable batteries. We address the issue of how to best partition a set of firm real-time tasks that can occasionally skip one instance according to a predefined QoS threshold. The main goal is to minimize the energy consumption of the system while offering solutions with respect to transient energy starvation situations the system can experiment. The contribution of the paper is twofold. First, we present a schedulability analysis of firm multiprocessor task sets under QoS constraints. Second we propose new partitionning heuristics integrating skips. The evaluation is conducted from several points of view (minimization of the total processor number, maximization of the spare capacity on each processor).
{"title":"Partitioned EDF scheduling in multicore systems with quality of service constraints","authors":"Nadine Abdallah, Audrey Queudet, M. Chetto, R. H. Chehade","doi":"10.1109/ICECS.2011.6122386","DOIUrl":"https://doi.org/10.1109/ICECS.2011.6122386","url":null,"abstract":"In this paper we study the partitioned EDF scheduling in a homogeneous multiprocessor environment with Quality of Service (QoS) constraints. The system considered here is a real-time multiprocessor system assumed to be powered by rechargeable batteries. We address the issue of how to best partition a set of firm real-time tasks that can occasionally skip one instance according to a predefined QoS threshold. The main goal is to minimize the energy consumption of the system while offering solutions with respect to transient energy starvation situations the system can experiment. The contribution of the paper is twofold. First, we present a schedulability analysis of firm multiprocessor task sets under QoS constraints. Second we propose new partitionning heuristics integrating skips. The evaluation is conducted from several points of view (minimization of the total processor number, maximization of the spare capacity on each processor).","PeriodicalId":251525,"journal":{"name":"2011 18th IEEE International Conference on Electronics, Circuits, and Systems","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128723959","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-01DOI: 10.1109/ICECS.2011.6122218
M. Matteis, M. Blasi, G. Cocciolo, A. Baschirotto, M. Sabatini
In this paper a 115μW Programmable Gain Amplifier (PGA) in 90nm CMOS technology is presented. The PGA is embedded in the baseband chain of a low-data-rate UWB PAN receiver. Since a vibration-based energy scavenger powers the receiver, low power consumption is required, while maintaining large dynamic range and wide-band frequency response. Moreover, high input impedance is required from system level constraints and this is achieved with MOS input devices, exploiting dual differential input Opamp. The PGA gain is programmable in the 15dB-to-50dB range with 1dB step. For the maximum gain level (50dB), the Input-Referred-Noise power spectral density is lower than 20nV/√Hz. From a single 1V supply, for the minimum gain level (15dB), a 0.8Vzero-peak output signal is processed with THD=−40dBc.
{"title":"A 1V 115μW 20nV/√Hz 15–50dB-range PGA with 5MHz bandwidth for UWB personal area network","authors":"M. Matteis, M. Blasi, G. Cocciolo, A. Baschirotto, M. Sabatini","doi":"10.1109/ICECS.2011.6122218","DOIUrl":"https://doi.org/10.1109/ICECS.2011.6122218","url":null,"abstract":"In this paper a 115μW Programmable Gain Amplifier (PGA) in 90nm CMOS technology is presented. The PGA is embedded in the baseband chain of a low-data-rate UWB PAN receiver. Since a vibration-based energy scavenger powers the receiver, low power consumption is required, while maintaining large dynamic range and wide-band frequency response. Moreover, high input impedance is required from system level constraints and this is achieved with MOS input devices, exploiting dual differential input Opamp. The PGA gain is programmable in the 15dB-to-50dB range with 1dB step. For the maximum gain level (50dB), the Input-Referred-Noise power spectral density is lower than 20nV/√Hz. From a single 1V supply, for the minimum gain level (15dB), a 0.8Vzero-peak output signal is processed with THD=−40dBc.","PeriodicalId":251525,"journal":{"name":"2011 18th IEEE International Conference on Electronics, Circuits, and Systems","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116985044","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-01DOI: 10.1109/ICECS.2011.6122290
J. Bouloc, L. Nony, C. Loppacher, W. Rahajandraibe, F. Bocquet, Lakhdar Zaïd
A FPGA-based tunable all-digital control system featuring high resolution all-digital PLL is presented. The whole system has been designed under Simulink environment and synthesized with QuartusII. The system can achieve very high frequency resolution (0.1Hz) within a frequency range of 20kHz to 60MHz.
{"title":"FPGA-based programmable digital PLL with very high frequency resolution","authors":"J. Bouloc, L. Nony, C. Loppacher, W. Rahajandraibe, F. Bocquet, Lakhdar Zaïd","doi":"10.1109/ICECS.2011.6122290","DOIUrl":"https://doi.org/10.1109/ICECS.2011.6122290","url":null,"abstract":"A FPGA-based tunable all-digital control system featuring high resolution all-digital PLL is presented. The whole system has been designed under Simulink environment and synthesized with QuartusII. The system can achieve very high frequency resolution (0.1Hz) within a frequency range of 20kHz to 60MHz.","PeriodicalId":251525,"journal":{"name":"2011 18th IEEE International Conference on Electronics, Circuits, and Systems","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114598914","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-01DOI: 10.1109/ICECS.2011.6122228
S. Clerc, F. Abouzeid, F. Argoud, Abhay Kumar, R. Kumar, P. Roche
A low cost Ultra Low Voltage design implemented using standard CAD tools with adapted margins is presented. Critical path replica rings have been measured to ensure models validity at ultra-low voltages, on the 0°C to 50°C temperature range. The observed behavior and mismatch compared to CAD simulations enabled us to define the margins to be used for the standard circuit implementation flow. We then derived a cell library focusing our effort on latches and level shifters. A 10k gates, 1k flip-flops demonstrator was designed and measured. Its functional voltage range is extended by 4× down to 0.24V, reducing the dynamic power by a factor 14× versus nominal. Forward Body Biasing and Temperature effect on minimum voltage for both worst die and die population average are reported.
{"title":"A 240mV 1MHz, 340mV 10MHz, 40nm CMOS, 252 bits frame decoder using ultra-low voltage circuit design platform","authors":"S. Clerc, F. Abouzeid, F. Argoud, Abhay Kumar, R. Kumar, P. Roche","doi":"10.1109/ICECS.2011.6122228","DOIUrl":"https://doi.org/10.1109/ICECS.2011.6122228","url":null,"abstract":"A low cost Ultra Low Voltage design implemented using standard CAD tools with adapted margins is presented. Critical path replica rings have been measured to ensure models validity at ultra-low voltages, on the 0°C to 50°C temperature range. The observed behavior and mismatch compared to CAD simulations enabled us to define the margins to be used for the standard circuit implementation flow. We then derived a cell library focusing our effort on latches and level shifters. A 10k gates, 1k flip-flops demonstrator was designed and measured. Its functional voltage range is extended by 4× down to 0.24V, reducing the dynamic power by a factor 14× versus nominal. Forward Body Biasing and Temperature effect on minimum voltage for both worst die and die population average are reported.","PeriodicalId":251525,"journal":{"name":"2011 18th IEEE International Conference on Electronics, Circuits, and Systems","volume":"67 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115207284","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-01DOI: 10.1109/ICECS.2011.6122230
Islam Seoudi, Karima Amara, F. Gayral, R. D. Molin, A. Amara
Modern pacemakers deliver localized electrical stimuli to the cardiac tissue via electrodes in the stimulation lead. The stimulation lead come either in unipolar or bipolar configuration (1 or 2 electrode). Studies however have shown benefits of a multi-electrode system in rendering therapy for heart diseases like chronic heart failure. In this paper we present the design and implementation of such a multi-electrode system. We discuss and provide solutions as well as the key challenges for such design in a constrained cardiac environment. These challenges are namely, powering of multi-electrode system, the communication protocol and the compliance with the existing standards. Our chip has been fabricated in 0.18 μm technology and occupies 2.25×5.35 mm² area. It enables ultra-low power operation down to 1.8 volts and allows quick configuration. Our design has been tested by simulations and measurements. To the best of our knowledge our study is the first published study of its kind
{"title":"Multi-electrode system for pacemaker applications","authors":"Islam Seoudi, Karima Amara, F. Gayral, R. D. Molin, A. Amara","doi":"10.1109/ICECS.2011.6122230","DOIUrl":"https://doi.org/10.1109/ICECS.2011.6122230","url":null,"abstract":"Modern pacemakers deliver localized electrical stimuli to the cardiac tissue via electrodes in the stimulation lead. The stimulation lead come either in unipolar or bipolar configuration (1 or 2 electrode). Studies however have shown benefits of a multi-electrode system in rendering therapy for heart diseases like chronic heart failure. In this paper we present the design and implementation of such a multi-electrode system. We discuss and provide solutions as well as the key challenges for such design in a constrained cardiac environment. These challenges are namely, powering of multi-electrode system, the communication protocol and the compliance with the existing standards. Our chip has been fabricated in 0.18 μm technology and occupies 2.25×5.35 mm² area. It enables ultra-low power operation down to 1.8 volts and allows quick configuration. Our design has been tested by simulations and measurements. To the best of our knowledge our study is the first published study of its kind","PeriodicalId":251525,"journal":{"name":"2011 18th IEEE International Conference on Electronics, Circuits, and Systems","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116072546","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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