Pub Date : 2009-09-15DOI: 10.1109/MWSCAS.2009.5236080
H. San, Haruo Kobayashi
This paper proposes a new realization technique of image rejection function by noise-coupling architecture, which is used for a complex bandpass ΔΣAD modulator. The complex bandpass ΔΣAD modulator processes just input I and Q signals, not image signals, and the AD conversion can be realized with low power dissipation. It realizes an asymmetric noise-shaped spectra, which is desirable for such low-IF receiver applications. However, the performance of the complex bandpass ΔΣAD modulator suffers from the mismatch between internal analog I and Q paths. I/Q path mismatch causes an image signal, and the quantization noise of the mirror image band aliases into the desired signal band, which degrades the SQNDR (Signal to Quantization Noise and Distortion Ratio) of the modulator. In our proposed modulator architecture, an extra notch for image rejection is realized by noise-coupled topology. We just add some passive capacitors and switches to the modulator; the additional integrator circuit composed of an operation amplifier in the conventional image rejection realization is not necessary. Therefore, the performance of the complex modulator can be effectively raised without additional power dissipation. We have performed simulation with MATLAB to confirm the validity of the proposed architecture. The simulation results show that the proposed architecture can achieve the realization of image-rejection effectively, and improve the SQNDR of the complex bandpass ΔΣAD modulator.
针对复杂带通ΔΣAD调制器，提出了一种利用噪声耦合结构实现图像抑制函数的新技术。复杂带通ΔΣAD调制器只处理输入I和Q信号，不处理图像信号，可以以低功耗实现AD转换。它实现了非对称噪声形光谱，这是这种低中频接收器应用所需要的。然而，复杂带通ΔΣAD调制器的性能受到内部模拟I和Q路径不匹配的影响。I/Q路径失配导致图像信号，镜像频带的量化噪声混叠到期望的信号频带，降低了调制器的SQNDR (signal to quanti量化噪声和失真比)。在我们提出的调制器结构中，一个额外的陷波是通过噪声耦合拓扑来实现的。我们只是在调制器中加入一些无源电容器和开关;在传统的图像抑制实现中，不需要额外的由运算放大器组成的积分器电路。因此，可以有效地提高复合调制器的性能，而无需额外的功耗。我们用MATLAB进行了仿真，以验证所提出架构的有效性。仿真结果表明，该结构能够有效地实现图像抑制，提高了复杂带通ΔΣAD调制器的SQNDR。
{"title":"Complex bandpass ΔΣAD modulator with noise-coupled image rejection","authors":"H. San, Haruo Kobayashi","doi":"10.1109/MWSCAS.2009.5236080","DOIUrl":"https://doi.org/10.1109/MWSCAS.2009.5236080","url":null,"abstract":"This paper proposes a new realization technique of image rejection function by noise-coupling architecture, which is used for a complex bandpass ΔΣAD modulator. The complex bandpass ΔΣAD modulator processes just input I and Q signals, not image signals, and the AD conversion can be realized with low power dissipation. It realizes an asymmetric noise-shaped spectra, which is desirable for such low-IF receiver applications. However, the performance of the complex bandpass ΔΣAD modulator suffers from the mismatch between internal analog I and Q paths. I/Q path mismatch causes an image signal, and the quantization noise of the mirror image band aliases into the desired signal band, which degrades the SQNDR (Signal to Quantization Noise and Distortion Ratio) of the modulator. In our proposed modulator architecture, an extra notch for image rejection is realized by noise-coupled topology. We just add some passive capacitors and switches to the modulator; the additional integrator circuit composed of an operation amplifier in the conventional image rejection realization is not necessary. Therefore, the performance of the complex modulator can be effectively raised without additional power dissipation. We have performed simulation with MATLAB to confirm the validity of the proposed architecture. The simulation results show that the proposed architecture can achieve the realization of image-rejection effectively, and improve the SQNDR of the complex bandpass ΔΣAD modulator.","PeriodicalId":254577,"journal":{"name":"2009 52nd IEEE International Midwest Symposium on Circuits and Systems","volume":"161 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125892792","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-09-15DOI: 10.1109/MWSCAS.2009.5236118
D. Robles-Camarillo, L. Nino-de-Rivera, H. Quiroz-Mercado, M. J. Lopez-Miranda
The present work proposes a portable electronic waveform generator for transcorneal electrical stimulation (TES). The waveform model is generated into a digital processor, and is based on a healthy eye's multi-focal electroretinogram (MF-ERG) response. The stimulation protocol proposed in this paper is qualitatively different from the one reported by others like Inomata et. al. [1, 2]. Results show an improvement in patient's visual acuity and increased electrical B wave response in standard electroretinogram (ERG) tests, when TES is applied in patients suffering low vision (LV) produced by central retinal artery occlusion (CRAO).
{"title":"Portable transcorneal electrical stimulator system, applied on electrotherapy for low vision patients","authors":"D. Robles-Camarillo, L. Nino-de-Rivera, H. Quiroz-Mercado, M. J. Lopez-Miranda","doi":"10.1109/MWSCAS.2009.5236118","DOIUrl":"https://doi.org/10.1109/MWSCAS.2009.5236118","url":null,"abstract":"The present work proposes a portable electronic waveform generator for transcorneal electrical stimulation (TES). The waveform model is generated into a digital processor, and is based on a healthy eye's multi-focal electroretinogram (MF-ERG) response. The stimulation protocol proposed in this paper is qualitatively different from the one reported by others like Inomata et. al. [1, 2]. Results show an improvement in patient's visual acuity and increased electrical B wave response in standard electroretinogram (ERG) tests, when TES is applied in patients suffering low vision (LV) produced by central retinal artery occlusion (CRAO).","PeriodicalId":254577,"journal":{"name":"2009 52nd IEEE International Midwest Symposium on Circuits and Systems","volume":"63 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126284964","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-09-15DOI: 10.1109/MWSCAS.2009.5236077
P. Su, H. Chiueh
This paper presents the design and implementation of a low power sigma-delta modulator (SDM) with a standard 0.18-µm CMOS technology. A current optimization technique is utilized in proposed design to reduce the power of operational trans-conductance amplifier(OTA). Using a chain of Integrators with weighted feed-forward summation (CIFF) structure and optimized single-stage class-A OTA with positive feedback to minimize the power consumption, the second-order SDM achieves a SNR of 64dB that be able to process the signal form DC to 16 KHz. The power consumption is only 18.1 uW from a 1-V supply.
{"title":"The design of low-power CIFF structure second-order sigma-delta modulator","authors":"P. Su, H. Chiueh","doi":"10.1109/MWSCAS.2009.5236077","DOIUrl":"https://doi.org/10.1109/MWSCAS.2009.5236077","url":null,"abstract":"This paper presents the design and implementation of a low power sigma-delta modulator (SDM) with a standard 0.18-µm CMOS technology. A current optimization technique is utilized in proposed design to reduce the power of operational trans-conductance amplifier(OTA). Using a chain of Integrators with weighted feed-forward summation (CIFF) structure and optimized single-stage class-A OTA with positive feedback to minimize the power consumption, the second-order SDM achieves a SNR of 64dB that be able to process the signal form DC to 16 KHz. The power consumption is only 18.1 uW from a 1-V supply.","PeriodicalId":254577,"journal":{"name":"2009 52nd IEEE International Midwest Symposium on Circuits and Systems","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127717089","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-09-15DOI: 10.1109/MWSCAS.2009.5235987
Israel Olguin Carbajal, Enrique Cisneros Sedano, Blanca Alicia Rico Jimenez
This work depicts the development of an electrical energy distribution systems protection microprocessor based digital relay, commercialization viable, first in its kind in Mexico. It is an overcurrent relay with independent protection elements such as ground, phases, negative sequence, low frequency protection, recloser, directional elements, fault locator, oscilography and other auxiliary elements that constitute a first level protection system achieved by Mexican engineers.
{"title":"An electric energy distribution systems protection microprocessor based relay","authors":"Israel Olguin Carbajal, Enrique Cisneros Sedano, Blanca Alicia Rico Jimenez","doi":"10.1109/MWSCAS.2009.5235987","DOIUrl":"https://doi.org/10.1109/MWSCAS.2009.5235987","url":null,"abstract":"This work depicts the development of an electrical energy distribution systems protection microprocessor based digital relay, commercialization viable, first in its kind in Mexico. It is an overcurrent relay with independent protection elements such as ground, phases, negative sequence, low frequency protection, recloser, directional elements, fault locator, oscilography and other auxiliary elements that constitute a first level protection system achieved by Mexican engineers.","PeriodicalId":254577,"journal":{"name":"2009 52nd IEEE International Midwest Symposium on Circuits and Systems","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126757943","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-09-15DOI: 10.1109/MWSCAS.2009.5236034
Yi-Jung Wang, Chih-Chi Chang, Guo-Zua Wu, O. Chen
During decoding the bit stream of a block, only a block type selecting from 4×4, 4×8, 8×4 and 8×8 is employed to do the inverse integer transform of VC-1. Accordingly, the hardware architectures of 4×4, 4×8, 8×4 and 8×8 inverse integer transforms can be integrated to reduce hardware cost. In this work, a low-complexity integrated hardware architecture is proposed to realize these four inverse integer transforms. First, the one-dimensional transform operations associated with 4 and 8 points are analyzed to find out the common parts. Second, the transform multiplications are decomposed into multiple additions and shifting operations due to the fixed transform coefficients. The one-dimensional transform architecture that integrates adders and shifters of 4-point and 8-point operations with multiplexers and registers is developed at a regular data-flow manner. Finally, four 4×4, two 4×8, two 8×4 and one 8x8 transforms can be individually computed in the proposed integrated one-dimensional transform architecture under 16 clock cycles. As compared to the conventional architecture which implements 4-point and 8-point inverse integer transforms separately, the proposed architecture consumes less hardware cost to accomplish the inverse integer transform(s) of a block at a specific throughput rate.
{"title":"Low-complexity integrated architecture of 4×4, 4×8, 8×4 and 8×8 inverse integer transforms of VC-1","authors":"Yi-Jung Wang, Chih-Chi Chang, Guo-Zua Wu, O. Chen","doi":"10.1109/MWSCAS.2009.5236034","DOIUrl":"https://doi.org/10.1109/MWSCAS.2009.5236034","url":null,"abstract":"During decoding the bit stream of a block, only a block type selecting from 4×4, 4×8, 8×4 and 8×8 is employed to do the inverse integer transform of VC-1. Accordingly, the hardware architectures of 4×4, 4×8, 8×4 and 8×8 inverse integer transforms can be integrated to reduce hardware cost. In this work, a low-complexity integrated hardware architecture is proposed to realize these four inverse integer transforms. First, the one-dimensional transform operations associated with 4 and 8 points are analyzed to find out the common parts. Second, the transform multiplications are decomposed into multiple additions and shifting operations due to the fixed transform coefficients. The one-dimensional transform architecture that integrates adders and shifters of 4-point and 8-point operations with multiplexers and registers is developed at a regular data-flow manner. Finally, four 4×4, two 4×8, two 8×4 and one 8x8 transforms can be individually computed in the proposed integrated one-dimensional transform architecture under 16 clock cycles. As compared to the conventional architecture which implements 4-point and 8-point inverse integer transforms separately, the proposed architecture consumes less hardware cost to accomplish the inverse integer transform(s) of a block at a specific throughput rate.","PeriodicalId":254577,"journal":{"name":"2009 52nd IEEE International Midwest Symposium on Circuits and Systems","volume":"33 3","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113981015","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-09-15DOI: 10.1109/MWSCAS.2009.5236120
W. Kao, Chih-Chao Wei, Jen-Jui Liu, Pei-Yung Hsiao
Skilled cardiologists probe heart sounds by electronic stethoscope through human ears, but interpretation of heart sounds is a very special skill which is quite difficult to teach in a structured way. Because of this reason, automatic heart sound analysis in computer systems would be very helpful for medical staff. This paper presents a complete heart sound analysis system covering from the segmentation of beat cycles to the final determination of heart conditions. The kernels of heart beat cycle segmentation and recognition are based on autocorrelation, short-time Fourier transform, and support vector machines. The experiments are done by a public heart sound database released by Texas Heart Institute. A very promising recognition rate has been achieved.
{"title":"Automatic heart sound analysis with short-time Fourier transform and support vector machines","authors":"W. Kao, Chih-Chao Wei, Jen-Jui Liu, Pei-Yung Hsiao","doi":"10.1109/MWSCAS.2009.5236120","DOIUrl":"https://doi.org/10.1109/MWSCAS.2009.5236120","url":null,"abstract":"Skilled cardiologists probe heart sounds by electronic stethoscope through human ears, but interpretation of heart sounds is a very special skill which is quite difficult to teach in a structured way. Because of this reason, automatic heart sound analysis in computer systems would be very helpful for medical staff. This paper presents a complete heart sound analysis system covering from the segmentation of beat cycles to the final determination of heart conditions. The kernels of heart beat cycle segmentation and recognition are based on autocorrelation, short-time Fourier transform, and support vector machines. The experiments are done by a public heart sound database released by Texas Heart Institute. A very promising recognition rate has been achieved.","PeriodicalId":254577,"journal":{"name":"2009 52nd IEEE International Midwest Symposium on Circuits and Systems","volume":"365 7","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114057167","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-09-15DOI: 10.1109/MWSCAS.2009.5236007
Wen-Chih Wu, O. Chen
The problem of multiple-sound-source localization in a reverberant environment is investigated in this work, which is a critical technique in video conference applications and is still a challenging task in audio signal processing. In this study, sound signals are first estimated and separated from the mixtures received by a microphone array under a feedback architecture using the blind source separation algorithm. The parameters of time delay of arrival associated with microphones are calculated from the mixtures and estimated source signals by the time-domain cross correlation technique. Finally, the positions of sound sources are derived by the spatial position determination formulas. Experimental results demonstrate that the proposed scheme can effectively determine the locations of multiple sound sources in a near-field and reverberant environment. The direction prediction using the proposed scheme is very promising.
{"title":"Multiple-sound-source localization scheme based on feedback-architecture source separation","authors":"Wen-Chih Wu, O. Chen","doi":"10.1109/MWSCAS.2009.5236007","DOIUrl":"https://doi.org/10.1109/MWSCAS.2009.5236007","url":null,"abstract":"The problem of multiple-sound-source localization in a reverberant environment is investigated in this work, which is a critical technique in video conference applications and is still a challenging task in audio signal processing. In this study, sound signals are first estimated and separated from the mixtures received by a microphone array under a feedback architecture using the blind source separation algorithm. The parameters of time delay of arrival associated with microphones are calculated from the mixtures and estimated source signals by the time-domain cross correlation technique. Finally, the positions of sound sources are derived by the spatial position determination formulas. Experimental results demonstrate that the proposed scheme can effectively determine the locations of multiple sound sources in a near-field and reverberant environment. The direction prediction using the proposed scheme is very promising.","PeriodicalId":254577,"journal":{"name":"2009 52nd IEEE International Midwest Symposium on Circuits and Systems","volume":"6 10","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120866555","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-09-15DOI: 10.1109/MWSCAS.2009.5236024
V. Zaharov, Ángel Lambertt Lobaina, Jaime L. Rodriguez, Ramon Albandoz Soto
The mutual coupling between antenna array elements degrades the performance of spatial processing algorithm, such as signal-to-interference-plus-noise ratio (SINR) in output of antenna array, antenna gain, and so on. If the mutual coupling matrix (MCM) is known, mutual coupling effect can be mitigated by pre-multiplying the input signal by the inverse of the coupling matrix (assuming that it is invertible). Unfortunately, it requires intensive computational work with the cost of O(N2), where N is a number of antenna elements, especially for large antenna array applications. Taking into account that MCM has the Toeplitz structure, we propose to mitigate the mutual coupling with the cost of O(MlogM) by using fast algorithm that involve circular convolution, where 2N ≤ M < 4N and M is a number of power two. The performance of large adaptive antenna array in the presence of mutual coupling as well as after decoupling is discussed.
{"title":"Fast mutual coupling compensation algorithm for large adaptive antenna array","authors":"V. Zaharov, Ángel Lambertt Lobaina, Jaime L. Rodriguez, Ramon Albandoz Soto","doi":"10.1109/MWSCAS.2009.5236024","DOIUrl":"https://doi.org/10.1109/MWSCAS.2009.5236024","url":null,"abstract":"The mutual coupling between antenna array elements degrades the performance of spatial processing algorithm, such as signal-to-interference-plus-noise ratio (SINR) in output of antenna array, antenna gain, and so on. If the mutual coupling matrix (MCM) is known, mutual coupling effect can be mitigated by pre-multiplying the input signal by the inverse of the coupling matrix (assuming that it is invertible). Unfortunately, it requires intensive computational work with the cost of O(N2), where N is a number of antenna elements, especially for large antenna array applications. Taking into account that MCM has the Toeplitz structure, we propose to mitigate the mutual coupling with the cost of O(MlogM) by using fast algorithm that involve circular convolution, where 2N ≤ M < 4N and M is a number of power two. The performance of large adaptive antenna array in the presence of mutual coupling as well as after decoupling is discussed.","PeriodicalId":254577,"journal":{"name":"2009 52nd IEEE International Midwest Symposium on Circuits and Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130104655","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-09-15DOI: 10.1109/MWSCAS.2009.5236143
E. López-Delgadillo, J. A. Díaz-Méndez, M. A. Garcia-Andrade, M. Magaña, F. Maloberti
A system for self tuning of on-die terminators in current mode off-chip signaling is presented. The proposed method is based on an algorithm that uses the sign of the impedance matching error and the sign of the coupling branch current to perform the self tuning operation. The circuit implementation of the system is described and computer simulations at the transistor level are presented for process, temperature and load impedance variations.
{"title":"A self tuning system for on-die terminators in current mode off-chip signaling","authors":"E. López-Delgadillo, J. A. Díaz-Méndez, M. A. Garcia-Andrade, M. Magaña, F. Maloberti","doi":"10.1109/MWSCAS.2009.5236143","DOIUrl":"https://doi.org/10.1109/MWSCAS.2009.5236143","url":null,"abstract":"A system for self tuning of on-die terminators in current mode off-chip signaling is presented. The proposed method is based on an algorithm that uses the sign of the impedance matching error and the sign of the coupling branch current to perform the self tuning operation. The circuit implementation of the system is described and computer simulations at the transistor level are presented for process, temperature and load impedance variations.","PeriodicalId":254577,"journal":{"name":"2009 52nd IEEE International Midwest Symposium on Circuits and Systems","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127703913","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-09-15DOI: 10.1109/MWSCAS.2009.5235937
V. Honkote, B. Taskin
Resonant clocking technologies have been gaining increased attention due to their superiority of clock frequency, power dissipation, and variation tolerance. Two of the resonant clocking technologies, standing wave and rotary clocking, require specialized clock routing procedures to accommodate grid-type distribution topologies and the tapping of registers onto these grids. The total tapping wirelength for both technologies are significant due to the impacts on power dissipation and routing congestion. A quantitative study is performed to compare the total tapping wirelengths for equivalent implementations of these two resonant clocking technologies. Experiments demonstrate that the standing wave technology (with mobius implementation) requires on average 3.99X less tapping wirelength compared to the rotary resonant clocking technology.
{"title":"Design automation scheme for wirelength analysis of resonant clocking technologies","authors":"V. Honkote, B. Taskin","doi":"10.1109/MWSCAS.2009.5235937","DOIUrl":"https://doi.org/10.1109/MWSCAS.2009.5235937","url":null,"abstract":"Resonant clocking technologies have been gaining increased attention due to their superiority of clock frequency, power dissipation, and variation tolerance. Two of the resonant clocking technologies, standing wave and rotary clocking, require specialized clock routing procedures to accommodate grid-type distribution topologies and the tapping of registers onto these grids. The total tapping wirelength for both technologies are significant due to the impacts on power dissipation and routing congestion. A quantitative study is performed to compare the total tapping wirelengths for equivalent implementations of these two resonant clocking technologies. Experiments demonstrate that the standing wave technology (with mobius implementation) requires on average 3.99X less tapping wirelength compared to the rotary resonant clocking technology.","PeriodicalId":254577,"journal":{"name":"2009 52nd IEEE International Midwest Symposium on Circuits and Systems","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133033948","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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