Pub Date : 2009-09-15DOI: 10.1109/MWSCAS.2009.5236020
V. Golikov, O. Lebedeva, F.J. Miguel Reyes
We investigated the robustness of the linear detector operating in a Gaussian environment in the presence of a mismatch between the design interference covariance matrix and the actual one. We have suggested that the Gaussian environment consists of a known colored clutter, a white noise and a strong unwanted periodical signal with unknown nonstationary power. It has been obtained the asymptotic inverse covariance matrix of the interference when the unwanted signal power tends to infinite. Using this formula we developed the asymptotic likelihood-ratio test (LRT). The performance of the new test statistic is analyzed and compared with well known optimal detector. The effect of the unwanted signal removing on the performance is evaluated for an example scenario.
{"title":"A robust detection in the presence of a strong unwanted periodical signal with unknown nonstationary power","authors":"V. Golikov, O. Lebedeva, F.J. Miguel Reyes","doi":"10.1109/MWSCAS.2009.5236020","DOIUrl":"https://doi.org/10.1109/MWSCAS.2009.5236020","url":null,"abstract":"We investigated the robustness of the linear detector operating in a Gaussian environment in the presence of a mismatch between the design interference covariance matrix and the actual one. We have suggested that the Gaussian environment consists of a known colored clutter, a white noise and a strong unwanted periodical signal with unknown nonstationary power. It has been obtained the asymptotic inverse covariance matrix of the interference when the unwanted signal power tends to infinite. Using this formula we developed the asymptotic likelihood-ratio test (LRT). The performance of the new test statistic is analyzed and compared with well known optimal detector. The effect of the unwanted signal removing on the performance is evaluated for an example scenario.","PeriodicalId":254577,"journal":{"name":"2009 52nd IEEE International Midwest Symposium on Circuits and Systems","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132810355","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-09-15DOI: 10.1109/MWSCAS.2009.5236090
N. E. C. Rodriguez, Jose Ivan Guevara Juarez, Rodrigo Savage, Marcial Roberto Leyva Fernandez
The development of this project has the goal of controlling an android robot that has 17 digital servomotors; the position of each of the servomotors is controlled by pulse width modulation. The android also has a distance sensor that allows the android to turn around when encountered with an object that obstructs its way. To implement the control of the android Max II Micro board card from Altera Company is used.. This board is equipped with an Altera MAX® II EPM2210F324C3 CPLD (Complex Programmable Logic Device).
该项目的开发目标是控制一个拥有17个数字伺服电机的机器人;每个伺服电机的位置由脉宽调制控制。这个机器人还有一个距离传感器，当遇到障碍物时，它可以转身。为了实现对android Max II的控制，使用了Altera公司的微板卡。该板配备Altera MAX®II EPM2210F324C3 CPLD(复杂可编程逻辑器件)。
{"title":"Design and implementation of an android","authors":"N. E. C. Rodriguez, Jose Ivan Guevara Juarez, Rodrigo Savage, Marcial Roberto Leyva Fernandez","doi":"10.1109/MWSCAS.2009.5236090","DOIUrl":"https://doi.org/10.1109/MWSCAS.2009.5236090","url":null,"abstract":"The development of this project has the goal of controlling an android robot that has 17 digital servomotors; the position of each of the servomotors is controlled by pulse width modulation. The android also has a distance sensor that allows the android to turn around when encountered with an object that obstructs its way. To implement the control of the android Max II Micro board card from Altera Company is used.. This board is equipped with an Altera MAX® II EPM2210F324C3 CPLD (Complex Programmable Logic Device).","PeriodicalId":254577,"journal":{"name":"2009 52nd IEEE International Midwest Symposium on Circuits and Systems","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128303054","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-09-15DOI: 10.1109/MWSCAS.2009.5236091
E. G. Hernández-Martínez, E. Aranda-Bricaire
This paper presents a comparison between two non-collision strategies for multi-agent robots formations. The control objective is to coordinate a group of agents, considered as unicycle-type robots, to achieve desired inter-agent distances avoiding collisions. The formation strategy is based on the cyclic pursuit configuration where every agent can detect another agent only. The first non-collision strategy is the standard methodology of repulsive forces obtained as the gradient of Repulsive Potential Functions. The second strategy is a novel Repulsive Vector Field based on a scaled unstable focus. The comparison is carried out both by numerical simulations and over an experimental set-up consisting of three unicycle-type robots.
{"title":"Experimental comparison of non-collision strategies in multi-agent robots formation control","authors":"E. G. Hernández-Martínez, E. Aranda-Bricaire","doi":"10.1109/MWSCAS.2009.5236091","DOIUrl":"https://doi.org/10.1109/MWSCAS.2009.5236091","url":null,"abstract":"This paper presents a comparison between two non-collision strategies for multi-agent robots formations. The control objective is to coordinate a group of agents, considered as unicycle-type robots, to achieve desired inter-agent distances avoiding collisions. The formation strategy is based on the cyclic pursuit configuration where every agent can detect another agent only. The first non-collision strategy is the standard methodology of repulsive forces obtained as the gradient of Repulsive Potential Functions. The second strategy is a novel Repulsive Vector Field based on a scaled unstable focus. The comparison is carried out both by numerical simulations and over an experimental set-up consisting of three unicycle-type robots.","PeriodicalId":254577,"journal":{"name":"2009 52nd IEEE International Midwest Symposium on Circuits and Systems","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128374189","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-09-15DOI: 10.1109/MWSCAS.2009.5235946
S. Amarchinta, H. Kanitkar, D. Kudithipudi
Digital subthreshold circuits are gaining importance because of their ability to serve as an ideal low power solution. In this paper, a methodology to design a performance enhanced subthreshold standard cell library robust to process variations is discussed. Several approaches to design a performance enhanced cell library are discussed and an optimal design choice is made with energy-delay product as a metric. Significant performance improvements of 2X, 8X and 1.5X are achieved for inverter, AND, and OR cells respectively over regular cell library. The variation in delay for the proposed standard cell library with respect to four process corners is studied. A significant reduction of about 75.6% in delay variation across worst case process corners was observed when a normal inverter and inverter from the high performance cell library were simulated.
{"title":"Robust and high performance subthreshold standard cell design","authors":"S. Amarchinta, H. Kanitkar, D. Kudithipudi","doi":"10.1109/MWSCAS.2009.5235946","DOIUrl":"https://doi.org/10.1109/MWSCAS.2009.5235946","url":null,"abstract":"Digital subthreshold circuits are gaining importance because of their ability to serve as an ideal low power solution. In this paper, a methodology to design a performance enhanced subthreshold standard cell library robust to process variations is discussed. Several approaches to design a performance enhanced cell library are discussed and an optimal design choice is made with energy-delay product as a metric. Significant performance improvements of 2X, 8X and 1.5X are achieved for inverter, AND, and OR cells respectively over regular cell library. The variation in delay for the proposed standard cell library with respect to four process corners is studied. A significant reduction of about 75.6% in delay variation across worst case process corners was observed when a normal inverter and inverter from the high performance cell library were simulated.","PeriodicalId":254577,"journal":{"name":"2009 52nd IEEE International Midwest Symposium on Circuits and Systems","volume":"77 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132244274","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-09-15DOI: 10.1109/MWSCAS.2009.5235998
M. Karunaratne, B. Oomann
We applied a BIST soft repair scheme to embedded memories using redundant data columns. We obtained yield and defect data from commercial silicon parts, and explored possible yield improvements with only a single bit repair. We implemented it on a chip with 90 memories and process margins were changed to obtain split lots to validate the repair scheme.
{"title":"Yield gain with memory BISR — a case study","authors":"M. Karunaratne, B. Oomann","doi":"10.1109/MWSCAS.2009.5235998","DOIUrl":"https://doi.org/10.1109/MWSCAS.2009.5235998","url":null,"abstract":"We applied a BIST soft repair scheme to embedded memories using redundant data columns. We obtained yield and defect data from commercial silicon parts, and explored possible yield improvements with only a single bit repair. We implemented it on a chip with 90 memories and process margins were changed to obtain split lots to validate the repair scheme.","PeriodicalId":254577,"journal":{"name":"2009 52nd IEEE International Midwest Symposium on Circuits and Systems","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134152701","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-09-15DOI: 10.1109/MWSCAS.2009.5236097
A. Munoz, Cyrus D. Cantrell
The key problem in a parallel system is how to distribute the work load to the components of the system in order to get optimal resource utilization, maximize throughput, and minimize response time. The sliding-window (SW) switch is a highly parallel architecture that uses an array of memory-modules to store and process data packets in high speed-networks and Internets. In this paper, we study two key aspects in the design of a high-speed router/switch using the SW switch architecture. The effect of the memory-configuration and the memory-bandwidth in the performance of the SW switch architecture is investigated under bursty-traffic conditions.
{"title":"Memory-configuration and memory-bandwidth in the sliding-window (SW) switch architecture","authors":"A. Munoz, Cyrus D. Cantrell","doi":"10.1109/MWSCAS.2009.5236097","DOIUrl":"https://doi.org/10.1109/MWSCAS.2009.5236097","url":null,"abstract":"The key problem in a parallel system is how to distribute the work load to the components of the system in order to get optimal resource utilization, maximize throughput, and minimize response time. The sliding-window (SW) switch is a highly parallel architecture that uses an array of memory-modules to store and process data packets in high speed-networks and Internets. In this paper, we study two key aspects in the design of a high-speed router/switch using the SW switch architecture. The effect of the memory-configuration and the memory-bandwidth in the performance of the SW switch architecture is investigated under bursty-traffic conditions.","PeriodicalId":254577,"journal":{"name":"2009 52nd IEEE International Midwest Symposium on Circuits and Systems","volume":"86 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134417449","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-09-15DOI: 10.1109/MWSCAS.2009.5235937
V. Honkote, B. Taskin
Resonant clocking technologies have been gaining increased attention due to their superiority of clock frequency, power dissipation, and variation tolerance. Two of the resonant clocking technologies, standing wave and rotary clocking, require specialized clock routing procedures to accommodate grid-type distribution topologies and the tapping of registers onto these grids. The total tapping wirelength for both technologies are significant due to the impacts on power dissipation and routing congestion. A quantitative study is performed to compare the total tapping wirelengths for equivalent implementations of these two resonant clocking technologies. Experiments demonstrate that the standing wave technology (with mobius implementation) requires on average 3.99X less tapping wirelength compared to the rotary resonant clocking technology.
{"title":"Design automation scheme for wirelength analysis of resonant clocking technologies","authors":"V. Honkote, B. Taskin","doi":"10.1109/MWSCAS.2009.5235937","DOIUrl":"https://doi.org/10.1109/MWSCAS.2009.5235937","url":null,"abstract":"Resonant clocking technologies have been gaining increased attention due to their superiority of clock frequency, power dissipation, and variation tolerance. Two of the resonant clocking technologies, standing wave and rotary clocking, require specialized clock routing procedures to accommodate grid-type distribution topologies and the tapping of registers onto these grids. The total tapping wirelength for both technologies are significant due to the impacts on power dissipation and routing congestion. A quantitative study is performed to compare the total tapping wirelengths for equivalent implementations of these two resonant clocking technologies. Experiments demonstrate that the standing wave technology (with mobius implementation) requires on average 3.99X less tapping wirelength compared to the rotary resonant clocking technology.","PeriodicalId":254577,"journal":{"name":"2009 52nd IEEE International Midwest Symposium on Circuits and Systems","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133033948","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-09-15DOI: 10.1109/MWSCAS.2009.5236053
Tsan-Jieh Chen, H. Chiueh, H. Tsai, Chin-Fong Chiu
high resolution image combination and processing plays an important role in today's satellites' remote sensing applications. This paper presents an image recombination and processing circuitries (ICAI) for one-dimensional multi-strip CMOS image sensors. The proposed system take advantage of the satellites' linear moving property to control the expose time of CMOS image sensor and provides the realtime ability to continuous generate 12,000 × N high-resolution image for space remote sensing applications. The ICAI chip contains an image sensor control logics, image combiner, and host interface, one-dimensional pixel is combined to form a two-dimensional image by proposed circuitry. A prototype chip of ICAI was designed and fabricated with TSMC 0.18 µm CMOS 1P6M technology. The die size is 2.91 mm by 2.91 mm, and the power consumption is 20 mW operating at 8MHz under a 1.8 V supply voltage.
高分辨率图像的组合与处理在当今卫星遥感应用中发挥着重要作用。提出了一种用于一维多条带CMOS图像传感器的图像重组与处理电路(ICAI)。该系统利用卫星的线性运动特性来控制CMOS图像传感器的曝光时间，为空间遥感应用提供连续生成12000 × N高分辨率图像的实时能力。ICAI芯片包含图像传感器控制逻辑、图像合并器和主机接口，通过所提出的电路将一维像素组合成二维图像。采用台积电0.18µm CMOS 1P6M工艺设计制作了ICAI原型芯片。芯片尺寸为2.91 mm × 2.91 mm，功耗为20mw，工作频率为8MHz，电源电压为1.8 V。
{"title":"An image combiner and acquisition interface for space remote sensing applications","authors":"Tsan-Jieh Chen, H. Chiueh, H. Tsai, Chin-Fong Chiu","doi":"10.1109/MWSCAS.2009.5236053","DOIUrl":"https://doi.org/10.1109/MWSCAS.2009.5236053","url":null,"abstract":"high resolution image combination and processing plays an important role in today's satellites' remote sensing applications. This paper presents an image recombination and processing circuitries (ICAI) for one-dimensional multi-strip CMOS image sensors. The proposed system take advantage of the satellites' linear moving property to control the expose time of CMOS image sensor and provides the realtime ability to continuous generate 12,000 × N high-resolution image for space remote sensing applications. The ICAI chip contains an image sensor control logics, image combiner, and host interface, one-dimensional pixel is combined to form a two-dimensional image by proposed circuitry. A prototype chip of ICAI was designed and fabricated with TSMC 0.18 µm CMOS 1P6M technology. The die size is 2.91 mm by 2.91 mm, and the power consumption is 20 mW operating at 8MHz under a 1.8 V supply voltage.","PeriodicalId":254577,"journal":{"name":"2009 52nd IEEE International Midwest Symposium on Circuits and Systems","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131857048","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-09-15DOI: 10.1109/MWSCAS.2009.5235918
Huey Chian Foong, M. T. Tan, Yuanjin Zheng
This paper presents the design of a supply and process-insensitive 12-bit Digital Pulse Width Modulator (DPWM) for digital DC-DC converters. The DPWM is realized by a counter and a ring oscillator-multiplexer segmented tapped delay line. The ring oscillator of the tapped delay line is made insensitive to supply and process variation by biasing the differential delay cells with a supply-insensitive replica bias circuit. Simulation results show that the variation of the switching frequency of the DPWM at 1.03MHz is 0.4% for supply voltage variation between 1.5V and 2.5V and 0.95% over the temperature range from −40°C to 90°C. Monte-Carlo simulation was also performed to account for the effect of mismatch between the transistors of the ring oscillator. The worst case delay of the delay cells is 0.87% for ±5% (3-σ) mismatch.
{"title":"A supply and process-insensitive 12-bit DPWM for digital DC-DC converters","authors":"Huey Chian Foong, M. T. Tan, Yuanjin Zheng","doi":"10.1109/MWSCAS.2009.5235918","DOIUrl":"https://doi.org/10.1109/MWSCAS.2009.5235918","url":null,"abstract":"This paper presents the design of a supply and process-insensitive 12-bit Digital Pulse Width Modulator (DPWM) for digital DC-DC converters. The DPWM is realized by a counter and a ring oscillator-multiplexer segmented tapped delay line. The ring oscillator of the tapped delay line is made insensitive to supply and process variation by biasing the differential delay cells with a supply-insensitive replica bias circuit. Simulation results show that the variation of the switching frequency of the DPWM at 1.03MHz is 0.4% for supply voltage variation between 1.5V and 2.5V and 0.95% over the temperature range from −40°C to 90°C. Monte-Carlo simulation was also performed to account for the effect of mismatch between the transistors of the ring oscillator. The worst case delay of the delay cells is 0.87% for ±5% (3-σ) mismatch.","PeriodicalId":254577,"journal":{"name":"2009 52nd IEEE International Midwest Symposium on Circuits and Systems","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132156103","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-09-15DOI: 10.1109/MWSCAS.2009.5236009
J. Avalos, Daniel Espinobarro, J. Velazquez, J. Sanchez
In this paper we present an implementation of a digital adaptive filter on the digital signal processor TMS320C6713, using a variant of the LMS algorithm, which consists in error codification, thus the speed of convergence is increased and the complexity of design for its implementation in digital adaptive filters is reduced, because the resulting codified error is composed of integer values. The LMS Algorithm with codified error (ECLMS), was tested in an environmental noise canceller and the results demonstrate an increase in the convergence speed, and a reduction of processing time.
{"title":"Adaptive noise canceller using LMS algorithm with codified error in a DSP","authors":"J. Avalos, Daniel Espinobarro, J. Velazquez, J. Sanchez","doi":"10.1109/MWSCAS.2009.5236009","DOIUrl":"https://doi.org/10.1109/MWSCAS.2009.5236009","url":null,"abstract":"In this paper we present an implementation of a digital adaptive filter on the digital signal processor TMS320C6713, using a variant of the LMS algorithm, which consists in error codification, thus the speed of convergence is increased and the complexity of design for its implementation in digital adaptive filters is reduced, because the resulting codified error is composed of integer values. The LMS Algorithm with codified error (ECLMS), was tested in an environmental noise canceller and the results demonstrate an increase in the convergence speed, and a reduction of processing time.","PeriodicalId":254577,"journal":{"name":"2009 52nd IEEE International Midwest Symposium on Circuits and Systems","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133845453","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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