Pub Date : 2009-09-15DOI: 10.1109/MWSCAS.2009.5236044
Yuji Osaki, T. Hirose, K. Matsumoto, N. Kuroki, M. Numa
In this paper, we propose delay-compensation techniques for subthreshold digital circuits. Delay in digital circuits that are operated in the subthreshold region of a MOSFET changes exponentially with variations in threshold voltage. To mitigate such variations, threshold-voltage monitoring and supply-voltage scaling techniques are adopted. By monitoring the threshold voltage of each LSI chip and exploiting the voltage to supply voltage to subthreshold digital circuits, variations in delay time can be suppressed significantly. Monte Carlo SPICE simulation demonstrates that delay-time distribution can be improved from log-normal to normal. The coefficient of variation for the proposed technique is 31%.
{"title":"Delay-compensation techniques for ultra-low-power subthreshold CMOS digital LSIs","authors":"Yuji Osaki, T. Hirose, K. Matsumoto, N. Kuroki, M. Numa","doi":"10.1109/MWSCAS.2009.5236044","DOIUrl":"https://doi.org/10.1109/MWSCAS.2009.5236044","url":null,"abstract":"In this paper, we propose delay-compensation techniques for subthreshold digital circuits. Delay in digital circuits that are operated in the subthreshold region of a MOSFET changes exponentially with variations in threshold voltage. To mitigate such variations, threshold-voltage monitoring and supply-voltage scaling techniques are adopted. By monitoring the threshold voltage of each LSI chip and exploiting the voltage to supply voltage to subthreshold digital circuits, variations in delay time can be suppressed significantly. Monte Carlo SPICE simulation demonstrates that delay-time distribution can be improved from log-normal to normal. The coefficient of variation for the proposed technique is 31%.","PeriodicalId":254577,"journal":{"name":"2009 52nd IEEE International Midwest Symposium on Circuits and Systems","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122361719","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-09-15DOI: 10.1109/MWSCAS.2009.5235883
S. Vijay, D. Anchit
Full adders are the significant elements which need to be analyzed for low-complexity implementation. Algorithms which minimize the complexity of multiplications of the input image matrix and the DCT matrix focus on reducing the number of full adders (NFAs) needed to implement the multiplication. In this paper, we have successfully proposed a novel technique to reduce considerably the NFAs, and thereby both the power consumption and time delay involved in implementing the image-DCT multiplication. The authors make use of row-column transformations of the input image matrix exploiting the symmetry of the DCT. Design results show that our method gives an average reduction in power of about 10.5% when compared to Differential Pixel Implementation (DPI) [12] and 16.5% when compared to the conventional implementation. The proposed method can also be made recursive, which can further reduce the NFAs for the implementation.
{"title":"Low power implementation of DCT for on-board satellite image processing systems","authors":"S. Vijay, D. Anchit","doi":"10.1109/MWSCAS.2009.5235883","DOIUrl":"https://doi.org/10.1109/MWSCAS.2009.5235883","url":null,"abstract":"Full adders are the significant elements which need to be analyzed for low-complexity implementation. Algorithms which minimize the complexity of multiplications of the input image matrix and the DCT matrix focus on reducing the number of full adders (NFAs) needed to implement the multiplication. In this paper, we have successfully proposed a novel technique to reduce considerably the NFAs, and thereby both the power consumption and time delay involved in implementing the image-DCT multiplication. The authors make use of row-column transformations of the input image matrix exploiting the symmetry of the DCT. Design results show that our method gives an average reduction in power of about 10.5% when compared to Differential Pixel Implementation (DPI) [12] and 16.5% when compared to the conventional implementation. The proposed method can also be made recursive, which can further reduce the NFAs for the implementation.","PeriodicalId":254577,"journal":{"name":"2009 52nd IEEE International Midwest Symposium on Circuits and Systems","volume":"322 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122624393","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-09-15DOI: 10.1109/MWSCAS.2009.5235887
Chenchen Deng, S. Collins
If driven with sufficient force a Duffing resonator has sharp transitions in both amplitude and phase at two critical frequencies which could be exploited to make sensitive sensors. In this paper new results are presented which show that when the resonator is driven hard to enhance the change in amplitude any change in the resonator parameters is followed by a delayed response. Results from numerical simulations and tests of a ‘Duffing’ circuit are then presented that show that this undesirable behaviour can be avoided by carefully selecting the force used to drive the resonator. This proposed driving scheme is expected to give rise to fast, reliable, sensitive mass sensor.
{"title":"The transient response of a Duffing resonator following a parameter change","authors":"Chenchen Deng, S. Collins","doi":"10.1109/MWSCAS.2009.5235887","DOIUrl":"https://doi.org/10.1109/MWSCAS.2009.5235887","url":null,"abstract":"If driven with sufficient force a Duffing resonator has sharp transitions in both amplitude and phase at two critical frequencies which could be exploited to make sensitive sensors. In this paper new results are presented which show that when the resonator is driven hard to enhance the change in amplitude any change in the resonator parameters is followed by a delayed response. Results from numerical simulations and tests of a ‘Duffing’ circuit are then presented that show that this undesirable behaviour can be avoided by carefully selecting the force used to drive the resonator. This proposed driving scheme is expected to give rise to fast, reliable, sensitive mass sensor.","PeriodicalId":254577,"journal":{"name":"2009 52nd IEEE International Midwest Symposium on Circuits and Systems","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123012589","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-09-15DOI: 10.1109/MWSCAS.2009.5235988
E. Guzmán, J. G. Zambrano, A. Orantes, O. Pogrebnyak
Vector quantization is a method, used in the lossy compression of voice and images, which can produce results very near to the theoretical limits; however, its principal disadvantage is that the process of search based its functioning on an algorithm of total search, generating a slow process and of a complexity computacional considerable. The present work proposes the combination of two algorithms in the creation of a new vector quantization scheme. First, an associative network is obtained applying a Learning Algorithm for Multivariate Data Analysis (LAMDA) to a codebook generated by means of the LBG algorithm, the purpose of this network is to establish a relation between the training set and the codebook generated by the LBG algorithm; this associative network is a new codebook (LAMDA-codebook) used by the scheme proposed in this work (VQ-LAMDA). Second, considering the LAMDA-codebook as the central element, we use the classification phase of the LAMDA methodology to obtain a rapid search process; the function of this process is generate the set of the class indexes to which every input vector belongs, completing the vector quantization. Furthermore, it is described how to apply the vector quantization scheme proposed to image compression.
{"title":"A theoretical exposition to apply the lamda methodology to vector quantization","authors":"E. Guzmán, J. G. Zambrano, A. Orantes, O. Pogrebnyak","doi":"10.1109/MWSCAS.2009.5235988","DOIUrl":"https://doi.org/10.1109/MWSCAS.2009.5235988","url":null,"abstract":"Vector quantization is a method, used in the lossy compression of voice and images, which can produce results very near to the theoretical limits; however, its principal disadvantage is that the process of search based its functioning on an algorithm of total search, generating a slow process and of a complexity computacional considerable. The present work proposes the combination of two algorithms in the creation of a new vector quantization scheme. First, an associative network is obtained applying a Learning Algorithm for Multivariate Data Analysis (LAMDA) to a codebook generated by means of the LBG algorithm, the purpose of this network is to establish a relation between the training set and the codebook generated by the LBG algorithm; this associative network is a new codebook (LAMDA-codebook) used by the scheme proposed in this work (VQ-LAMDA). Second, considering the LAMDA-codebook as the central element, we use the classification phase of the LAMDA methodology to obtain a rapid search process; the function of this process is generate the set of the class indexes to which every input vector belongs, completing the vector quantization. Furthermore, it is described how to apply the vector quantization scheme proposed to image compression.","PeriodicalId":254577,"journal":{"name":"2009 52nd IEEE International Midwest Symposium on Circuits and Systems","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123032321","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-09-15DOI: 10.1109/MWSCAS.2009.5236152
Habib Adrang, H. Naeimi
This paper is presented a type III third-order charge pump PLL with transconductor-C (Gm-C) structure to achieve a PLL with fast locking time. To reach this goal, we have used Gm-C structure in the PLL loop. The advantage of this architecture is great loop gain while increases with the ratio Gm/C. As a result, the small signal settling time decreases and then, the locking time is reduced, significantly while the loop stability increases, as well. The performance of this architecture has been verified in an example. The simulation results show that there is almost 70% reduction in the settling time in comparison with the conventional second-order PLLs.
本文提出了一种三阶电荷泵锁相环，该锁相环具有跨导体- c (Gm-C)结构，可实现快速锁相环。为了达到这个目标，我们在锁相环中使用了Gm-C结构。该结构的优点是环路增益大，且随Gm/C的增加而增加。因此，小信号的稳定时间减少，锁定时间明显减少，同时环路的稳定性也提高了。通过实例验证了该体系结构的性能。仿真结果表明，与传统的二阶锁相环相比，该锁相环的稳定时间缩短了近70%。
{"title":"A type III fast locking time PLL with transconductor-C structure","authors":"Habib Adrang, H. Naeimi","doi":"10.1109/MWSCAS.2009.5236152","DOIUrl":"https://doi.org/10.1109/MWSCAS.2009.5236152","url":null,"abstract":"This paper is presented a type III third-order charge pump PLL with transconductor-C (Gm-C) structure to achieve a PLL with fast locking time. To reach this goal, we have used Gm-C structure in the PLL loop. The advantage of this architecture is great loop gain while increases with the ratio Gm/C. As a result, the small signal settling time decreases and then, the locking time is reduced, significantly while the loop stability increases, as well. The performance of this architecture has been verified in an example. The simulation results show that there is almost 70% reduction in the settling time in comparison with the conventional second-order PLLs.","PeriodicalId":254577,"journal":{"name":"2009 52nd IEEE International Midwest Symposium on Circuits and Systems","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128564798","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-09-15DOI: 10.1109/MWSCAS.2009.5236021
A. Shahein, M. Becker, N. Lotze, Y. Manoli
This paper introduces a novel selection criterion to choose between transposed and direct form filters for power efficient FIR polyphase decimators. Less than 5% tolerance between calculated power consumption using the proposed criterion and simulated results is observed. A combined architecture of transposed and direct form filters for power efficient FIR polyphase decimators is proposed. A decimator for a 3rd order low-pass Sigma-Delta modulator with an oversampling ratio of 24 is used as a case study. Different topologies using both transposed and direct form structures have been implemented for power consumption investigation. The designs were synthesized in 0.13µm CMOS technology.
{"title":"Power aware combination of transposed-form and direct-form FIR polyphase decimators for Sigma-Delta ADCs","authors":"A. Shahein, M. Becker, N. Lotze, Y. Manoli","doi":"10.1109/MWSCAS.2009.5236021","DOIUrl":"https://doi.org/10.1109/MWSCAS.2009.5236021","url":null,"abstract":"This paper introduces a novel selection criterion to choose between transposed and direct form filters for power efficient FIR polyphase decimators. Less than 5% tolerance between calculated power consumption using the proposed criterion and simulated results is observed. A combined architecture of transposed and direct form filters for power efficient FIR polyphase decimators is proposed. A decimator for a 3rd order low-pass Sigma-Delta modulator with an oversampling ratio of 24 is used as a case study. Different topologies using both transposed and direct form structures have been implemented for power consumption investigation. The designs were synthesized in 0.13µm CMOS technology.","PeriodicalId":254577,"journal":{"name":"2009 52nd IEEE International Midwest Symposium on Circuits and Systems","volume":"115 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115973311","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-09-15DOI: 10.1109/MWSCAS.2009.5236066
D. Maricic, Z. Ignjatovic, M. Bocko
An image sensor design with pixel-level sigma-delta (ΣΔ) conversion employing four transistors at each pixel where the feedback charge transfer is realized through the parasitic capacitances of an inactive transistor is presented. This architecture is a relatively simple and robust design where the only analog components required outside of the pixel array are shared row comparators and a voltage mode digital-to-analog converter (DAC) to supply the in-pixel charge feedback structures. The photodiode acts as the integrator of the ΣΔ modulator and an in-pixel charge feedback DAC is realized with two PMOS transistors. A third, minimum size PMOS transistor operating in the cut-off region provides capacitive coupling through which a controlled amount of charge is injected to the photodiode. The sensitivity of the image sensor is determined by the size of the feedback charge packets in the ΣΔ modulator. The remainder of the image sensor is all digital, including a decimation filter to convert each pixel's single bit output stream into a multi-bit sample. We fabricated a test pixel structure in the TSMC-0.35µm CMOS technology with 10µm × 10µm pixels and a fill factor of 31%. Experimental results demonstrated a SNR of 60dB and a dynamic range of 83dB.
{"title":"An oversampling digital pixel sensor with a charge transfer DAC employing parasitic capacitances","authors":"D. Maricic, Z. Ignjatovic, M. Bocko","doi":"10.1109/MWSCAS.2009.5236066","DOIUrl":"https://doi.org/10.1109/MWSCAS.2009.5236066","url":null,"abstract":"An image sensor design with pixel-level sigma-delta (ΣΔ) conversion employing four transistors at each pixel where the feedback charge transfer is realized through the parasitic capacitances of an inactive transistor is presented. This architecture is a relatively simple and robust design where the only analog components required outside of the pixel array are shared row comparators and a voltage mode digital-to-analog converter (DAC) to supply the in-pixel charge feedback structures. The photodiode acts as the integrator of the ΣΔ modulator and an in-pixel charge feedback DAC is realized with two PMOS transistors. A third, minimum size PMOS transistor operating in the cut-off region provides capacitive coupling through which a controlled amount of charge is injected to the photodiode. The sensitivity of the image sensor is determined by the size of the feedback charge packets in the ΣΔ modulator. The remainder of the image sensor is all digital, including a decimation filter to convert each pixel's single bit output stream into a multi-bit sample. We fabricated a test pixel structure in the TSMC-0.35µm CMOS technology with 10µm × 10µm pixels and a fill factor of 31%. Experimental results demonstrated a SNR of 60dB and a dynamic range of 83dB.","PeriodicalId":254577,"journal":{"name":"2009 52nd IEEE International Midwest Symposium on Circuits and Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116329217","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-09-15DOI: 10.1109/MWSCAS.2009.5235900
Eleazar Aguirre Anaya, M. Nakano-Miyatake, H. Meana
Forensics science is based on a methodology composed by a group of stages, being the analysis one of them. Analysis is responsible to determine when a data constitutes evidence; and as a consequence it can be presented to a court. When the amount of data in a Network is small, its analysis is relatively simple, but when it is huge the data analysis becomes a challenge for the forensics expert. In this paper a forensics network model is proposed, which allows to obtain the existing evidence in an involved TCP/IP network. This Model uses the Fuzzy Logic and the Artificial Neural Networks to detect the Network flows that realize suspicious activities in the network or hosts, minimizing also the cost and the time to process the information in order to discriminate which are normal network flows and which has been subjected to attacks and intrusions.
{"title":"Network forensics with Neurofuzzy techniques","authors":"Eleazar Aguirre Anaya, M. Nakano-Miyatake, H. Meana","doi":"10.1109/MWSCAS.2009.5235900","DOIUrl":"https://doi.org/10.1109/MWSCAS.2009.5235900","url":null,"abstract":"Forensics science is based on a methodology composed by a group of stages, being the analysis one of them. Analysis is responsible to determine when a data constitutes evidence; and as a consequence it can be presented to a court. When the amount of data in a Network is small, its analysis is relatively simple, but when it is huge the data analysis becomes a challenge for the forensics expert. In this paper a forensics network model is proposed, which allows to obtain the existing evidence in an involved TCP/IP network. This Model uses the Fuzzy Logic and the Artificial Neural Networks to detect the Network flows that realize suspicious activities in the network or hosts, minimizing also the cost and the time to process the information in order to discriminate which are normal network flows and which has been subjected to attacks and intrusions.","PeriodicalId":254577,"journal":{"name":"2009 52nd IEEE International Midwest Symposium on Circuits and Systems","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116330795","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-09-15DOI: 10.1109/MWSCAS.2009.5236087
Y. Pedraza-Beltran, O. Gonzalez-Nagera, B. del Muro-Cuéllar
This paper considers the stabilization problem of linear systems with n + 1 poles and a time delay τ. First, the conditions for the existence of a stabilizing control by static output feedback are done. Subsequently, the conditions for the existence of a predictor scheme are established. Finally, the application of the results are illustrated with three academic examples.
{"title":"Stabilization of high-order systems with delay using a predictor schema","authors":"Y. Pedraza-Beltran, O. Gonzalez-Nagera, B. del Muro-Cuéllar","doi":"10.1109/MWSCAS.2009.5236087","DOIUrl":"https://doi.org/10.1109/MWSCAS.2009.5236087","url":null,"abstract":"This paper considers the stabilization problem of linear systems with n + 1 poles and a time delay τ. First, the conditions for the existence of a stabilizing control by static output feedback are done. Subsequently, the conditions for the existence of a predictor scheme are established. Finally, the application of the results are illustrated with three academic examples.","PeriodicalId":254577,"journal":{"name":"2009 52nd IEEE International Midwest Symposium on Circuits and Systems","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116949106","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-09-15DOI: 10.1109/MWSCAS.2009.5235921
Jungmoon Kim, Hyunho Chu, Chulwoo Kim
This paper describes an integrated current-mode buck converter with reliable hysteretic mode controller and modulators for fast dynamic voltage scaling (DVS). The proposed mode controller and modulators enable the DC-DC buck converter to perform its smooth mode transitions at optimal points. The continuous current-limiting and DCM controls drive the DVS to track the reference at the maximum speed in both PWM and PFM modes. The DC-DC buck converter is implemented in a 90-nm 3.3V CMOS process. The maximum efficiency reaches 94.5%. The hysteretic mode controller keeps its efficiency always at more than 75% for any load conditions. During a mode transition, the output voltage has no overshoots, and it can track the reference voltage instantly.
{"title":"Current-mode DC-DC buck converter with reliable hysteretic-mode control and dual modulator for fast dynamic voltage scaling","authors":"Jungmoon Kim, Hyunho Chu, Chulwoo Kim","doi":"10.1109/MWSCAS.2009.5235921","DOIUrl":"https://doi.org/10.1109/MWSCAS.2009.5235921","url":null,"abstract":"This paper describes an integrated current-mode buck converter with reliable hysteretic mode controller and modulators for fast dynamic voltage scaling (DVS). The proposed mode controller and modulators enable the DC-DC buck converter to perform its smooth mode transitions at optimal points. The continuous current-limiting and DCM controls drive the DVS to track the reference at the maximum speed in both PWM and PFM modes. The DC-DC buck converter is implemented in a 90-nm 3.3V CMOS process. The maximum efficiency reaches 94.5%. The hysteretic mode controller keeps its efficiency always at more than 75% for any load conditions. During a mode transition, the output voltage has no overshoots, and it can track the reference voltage instantly.","PeriodicalId":254577,"journal":{"name":"2009 52nd IEEE International Midwest Symposium on Circuits and Systems","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115545764","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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