M. Blyzniuk, T. Cibáková, E. Gramatová, W. Kuzmicz, M. Lobur, W. Pleskacz, J. Raik, R. Ubar
A new fault model is developed for estimating the coverage of physical defects in digital circuits for given test sets. Based on this model, a new hierarchical defect oriented fault simulation method is proposed. At the higher level simulation we use the functional fault model, at the lower level we use the defect/fault relationships in the form of defect coverage table and the defect probabilities. A description and the experimental data are given about probabilistic analysis of a complex CMOS gate. Analysis of the quality of 100% stuck-at fault test sets for two benchmark circuits in covering physical defects like internal shorts, stuck-opens and stuck-ons. It has been shown that in the worst case a test with 100% stuck-at fault coverage may, have only 50% coverage for internal shorts in complex CMOS gates. It has been shown that classical test coverage calculation based on counting defects without taking into account the defect probabilities may lead to considerable overestimation of results.
{"title":"Hierarchical defect-oriented fault simulation for digital circuits","authors":"M. Blyzniuk, T. Cibáková, E. Gramatová, W. Kuzmicz, M. Lobur, W. Pleskacz, J. Raik, R. Ubar","doi":"10.1109/ETW.2000.873781","DOIUrl":"https://doi.org/10.1109/ETW.2000.873781","url":null,"abstract":"A new fault model is developed for estimating the coverage of physical defects in digital circuits for given test sets. Based on this model, a new hierarchical defect oriented fault simulation method is proposed. At the higher level simulation we use the functional fault model, at the lower level we use the defect/fault relationships in the form of defect coverage table and the defect probabilities. A description and the experimental data are given about probabilistic analysis of a complex CMOS gate. Analysis of the quality of 100% stuck-at fault test sets for two benchmark circuits in covering physical defects like internal shorts, stuck-opens and stuck-ons. It has been shown that in the worst case a test with 100% stuck-at fault coverage may, have only 50% coverage for internal shorts in complex CMOS gates. It has been shown that classical test coverage calculation based on counting defects without taking into account the defect probabilities may lead to considerable overestimation of results.","PeriodicalId":255826,"journal":{"name":"Proceedings IEEE European Test Workshop","volume":"77 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122833622","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The quiescent current (I/sub DDQ/) consumed by a CMOS IC is a good indicator of the presence of a large class of defects. However, the effectiveness of I/sub DDQ/ testing requires appropriate discriminability of defective and defect-free currents, and hence it becomes necessary to estimate the currents involved in order to design the I/sub DDQ/ test. In this work, we present a method to estimate accurately the non-defective I/sub DDQ/ consumption based on a hierarchical approach at electrical (cell) and logic (circuit) levels. This accurate estimator is used in conjunction with an ATPG to obtain vectors having low/high defect-free I/sub DDQ/ currents.
{"title":"LEAP: An accurate defect-free I/sub DDQ/ estimator","authors":"A. Ferré, J. Figueras","doi":"10.1109/ETW.2000.873776","DOIUrl":"https://doi.org/10.1109/ETW.2000.873776","url":null,"abstract":"The quiescent current (I/sub DDQ/) consumed by a CMOS IC is a good indicator of the presence of a large class of defects. However, the effectiveness of I/sub DDQ/ testing requires appropriate discriminability of defective and defect-free currents, and hence it becomes necessary to estimate the currents involved in order to design the I/sub DDQ/ test. In this work, we present a method to estimate accurately the non-defective I/sub DDQ/ consumption based on a hierarchical approach at electrical (cell) and logic (circuit) levels. This accurate estimator is used in conjunction with an ATPG to obtain vectors having low/high defect-free I/sub DDQ/ currents.","PeriodicalId":255826,"journal":{"name":"Proceedings IEEE European Test Workshop","volume":"125 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116850380","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Monica Lobetti Bodoni, A. Benso, S. Chiusano, S. Carlo, G. D. Natale, P. Prinetto
The present paper proposes a solution to the problem of testing a system containing many distributed memories of different sizes. The proposed solution relies in the development of a BIST architecture characterized by a single BIST processor, implemented as a microprogrammable machine and able to execute different test algorithms, a wrapper for each SRAM including standard memory BIST modules, and an interface block to manage the communications between the SRAM and the BIST processor. Both area overhead and routing costs are minimized, and a scan-based approach allows full diagnostic capabilities of the faults possibly detected in the memories under test.
{"title":"An effective distributed BIST architecture for RAMs","authors":"Monica Lobetti Bodoni, A. Benso, S. Chiusano, S. Carlo, G. D. Natale, P. Prinetto","doi":"10.1109/ETW.2000.873788","DOIUrl":"https://doi.org/10.1109/ETW.2000.873788","url":null,"abstract":"The present paper proposes a solution to the problem of testing a system containing many distributed memories of different sizes. The proposed solution relies in the development of a BIST architecture characterized by a single BIST processor, implemented as a microprogrammable machine and able to execute different test algorithms, a wrapper for each SRAM including standard memory BIST modules, and an interface block to manage the communications between the SRAM and the BIST processor. Both area overhead and routing costs are minimized, and a scan-based approach allows full diagnostic capabilities of the faults possibly detected in the memories under test.","PeriodicalId":255826,"journal":{"name":"Proceedings IEEE European Test Workshop","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131045509","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The first time unit where a fault in a synchronous sequential circuit is detected by a given test sequence T/sub 0/ is used by various procedures. One such procedure selects input sequences that are loaded onto an on-chip memory and used as seeds for built-in test pattern generation. Each input sequence is constructed based on a different fault f and is extracted from T/sub 0/ around the first detection time of f. In this work, we extend this procedure to consider multiple time units where every target fault f is detected by T/sub 0/ in order to select a shorter sequence based on f. The result is reduced storage requirements and test application time for this built-in test pattern generation approach.
{"title":"On the use of multiple fault detection times in a method for built-in test pattern generation for synchronous sequential circuits","authors":"I. Pomeranz, S. Reddy","doi":"10.1109/ETW.2000.873792","DOIUrl":"https://doi.org/10.1109/ETW.2000.873792","url":null,"abstract":"The first time unit where a fault in a synchronous sequential circuit is detected by a given test sequence T/sub 0/ is used by various procedures. One such procedure selects input sequences that are loaded onto an on-chip memory and used as seeds for built-in test pattern generation. Each input sequence is constructed based on a different fault f and is extracted from T/sub 0/ around the first detection time of f. In this work, we extend this procedure to consider multiple time units where every target fault f is detected by T/sub 0/ in order to select a shorter sequence based on f. The result is reduced storage requirements and test application time for this built-in test pattern generation approach.","PeriodicalId":255826,"journal":{"name":"Proceedings IEEE European Test Workshop","volume":"109 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134534100","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
We present the concept of a multiple-valued logic simulator that is able to more accurately determine the possible behavior of a circuit in the presence of bridging faults. By a user defined mapping of a range of voltages to a logic value the simulator takes care of certain voltages more closely than common bridge fault simulators that map all voltages to either logic 1 or 0. Experimental results are given to demonstrate the improved fault detection possibilities.
{"title":"A parameterizable fault simulator for bridging faults","authors":"P. Engelke, B. Becker, Martin Keim","doi":"10.1109/ETW.2000.873780","DOIUrl":"https://doi.org/10.1109/ETW.2000.873780","url":null,"abstract":"We present the concept of a multiple-valued logic simulator that is able to more accurately determine the possible behavior of a circuit in the presence of bridging faults. By a user defined mapping of a range of voltages to a logic value the simulator takes care of certain voltages more closely than common bridge fault simulators that map all voltages to either logic 1 or 0. Experimental results are given to demonstrate the improved fault detection possibilities.","PeriodicalId":255826,"journal":{"name":"Proceedings IEEE European Test Workshop","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133723019","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The industrial default to test random logic is based on stuck-at fault test patterns applied via scan-chains. This test-method can be described as static voltage testing. A second well-known method is I/sub DDQ/ resting, which can be described as static current testing. This second method is especially suited for detecting resistive shorts. For deep sub-micron technologies new defect mechanisms start to become important. Especially, opens are a much feared type of defect since static test methods are less suited to detect these defects. Dynamic test methods such as delay-fault testing and transient current testing could fill this gap in the test suite. The paper gives an overview of the aforementioned test-methods including some of the new current-based test methods necessary for deep submicron technologies and their defect detection capabilities.
{"title":"Comparison of defect detection capabilities of current-based and voltage-based test methods","authors":"B. Kruseman","doi":"10.1109/ETW.2000.873796","DOIUrl":"https://doi.org/10.1109/ETW.2000.873796","url":null,"abstract":"The industrial default to test random logic is based on stuck-at fault test patterns applied via scan-chains. This test-method can be described as static voltage testing. A second well-known method is I/sub DDQ/ resting, which can be described as static current testing. This second method is especially suited for detecting resistive shorts. For deep sub-micron technologies new defect mechanisms start to become important. Especially, opens are a much feared type of defect since static test methods are less suited to detect these defects. Dynamic test methods such as delay-fault testing and transient current testing could fill this gap in the test suite. The paper gives an overview of the aforementioned test-methods including some of the new current-based test methods necessary for deep submicron technologies and their defect detection capabilities.","PeriodicalId":255826,"journal":{"name":"Proceedings IEEE European Test Workshop","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129540786","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
M. Lajolo, M. Rebaudengo, M. Reorda, M. Violante, L. Lavagno
Co-design tools represent an effective solution for reducing costs and shortening time-to-market, when System-on-Chip design is considered. In a top-down design flow, designers would greatly benefit from the availability of tools able to automatically generate test benches, which can be used during every design step, from the system-level specification to the gate-level description. This would significantly increase the chance of identifying design bugs early in the design flow, thus reducing the costs and increasing the final product quality. The paper proposes an approach for integrating the ability to generate test benches into an existing co-design tool. Suitable metrics are proposed to guide the generation, and preliminary experimental results are reported, assessing the effectiveness of the proposed technique.
{"title":"System-level test bench generation in a co-design framework","authors":"M. Lajolo, M. Rebaudengo, M. Reorda, M. Violante, L. Lavagno","doi":"10.1109/ETW.2000.873775","DOIUrl":"https://doi.org/10.1109/ETW.2000.873775","url":null,"abstract":"Co-design tools represent an effective solution for reducing costs and shortening time-to-market, when System-on-Chip design is considered. In a top-down design flow, designers would greatly benefit from the availability of tools able to automatically generate test benches, which can be used during every design step, from the system-level specification to the gate-level description. This would significantly increase the chance of identifying design bugs early in the design flow, thus reducing the costs and increasing the final product quality. The paper proposes an approach for integrating the ability to generate test benches into an existing co-design tool. Suitable metrics are proposed to guide the generation, and preliminary experimental results are reported, assessing the effectiveness of the proposed technique.","PeriodicalId":255826,"journal":{"name":"Proceedings IEEE European Test Workshop","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131583894","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
M. Renovell, J. Portal, P. Faure, J. Figueras, Y. Zorian
The objective of this paper is to generate an application-oriented test procedure to be used by a FPGA user in a given application. General definitions concerning the specific problem of testing RAM-based FPGAs are first given such as the important concept of 'AC-non-redundant fault'. Using a set of circuits implemented on a XILINX 4000E, it is shown that a classical test pattern generation performed on the circuit netlist gives a low AC-non-redundant fault coverage and it is pointed out that test pattern generation performed on a FPGA representation is required. It is then demonstrated that test pattern generation performed on the FPGA representation can be significantly accelerated by removing most of the AC-redundant faults. Finally, a technique is proposed to even more accelerate the test pattern generation process by using a reduced FPGA description.
{"title":"Analyzing the test generation problem for an application-oriented test of FPGAs","authors":"M. Renovell, J. Portal, P. Faure, J. Figueras, Y. Zorian","doi":"10.1109/ETW.2000.873782","DOIUrl":"https://doi.org/10.1109/ETW.2000.873782","url":null,"abstract":"The objective of this paper is to generate an application-oriented test procedure to be used by a FPGA user in a given application. General definitions concerning the specific problem of testing RAM-based FPGAs are first given such as the important concept of 'AC-non-redundant fault'. Using a set of circuits implemented on a XILINX 4000E, it is shown that a classical test pattern generation performed on the circuit netlist gives a low AC-non-redundant fault coverage and it is pointed out that test pattern generation performed on a FPGA representation is required. It is then demonstrated that test pattern generation performed on the FPGA representation can be significantly accelerated by removing most of the AC-redundant faults. Finally, a technique is proposed to even more accelerate the test pattern generation process by using a reduced FPGA description.","PeriodicalId":255826,"journal":{"name":"Proceedings IEEE European Test Workshop","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131966796","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A design-for-testability implementation to achieve high fault coverages in the analogue functional blocks of mixed circuit ASICs is presented in this feasibility study. To this end existing op amps or OTAs are converted into clocked comparators with hysteresis and variable reference levels. The resulting two-mode comparators are connected to specific internal nodes. Depending on the mode this node can be either statically and/or dynamically evaluated on-chip without the need to bring an analogue signal off-chip. Results from first simulations and measurements on a test circuit realised in 0.35 /spl mu/m technology are presented.
{"title":"Static and dynamic on-chip test response evaluation using a two-mode comparator","authors":"D. Venuto, M. Ohletz, G. Matarrese","doi":"10.1109/ETW.2000.873778","DOIUrl":"https://doi.org/10.1109/ETW.2000.873778","url":null,"abstract":"A design-for-testability implementation to achieve high fault coverages in the analogue functional blocks of mixed circuit ASICs is presented in this feasibility study. To this end existing op amps or OTAs are converted into clocked comparators with hysteresis and variable reference levels. The resulting two-mode comparators are connected to specific internal nodes. Depending on the mode this node can be either statically and/or dynamically evaluated on-chip without the need to bring an analogue signal off-chip. Results from first simulations and measurements on a test circuit realised in 0.35 /spl mu/m technology are presented.","PeriodicalId":255826,"journal":{"name":"Proceedings IEEE European Test Workshop","volume":"116 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123635129","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A. Burdass, G. Campbell, R. Grisenthwaite, D. Gwilt, P. Harrod, R. York
This paper compares and contrast two very different approaches to testing cached CPU macrocells that are typically embedded in a System on Chip (SoC). One uses a test bus to apply functional vectors, while the other uses a combination of scan insertion, memory BIST and test collars. IP protection issues and nonintrusive tracing are also discussed.
{"title":"Microprocessor cores","authors":"A. Burdass, G. Campbell, R. Grisenthwaite, D. Gwilt, P. Harrod, R. York","doi":"10.1109/ETW.2000.873774","DOIUrl":"https://doi.org/10.1109/ETW.2000.873774","url":null,"abstract":"This paper compares and contrast two very different approaches to testing cached CPU macrocells that are typically embedded in a System on Chip (SoC). One uses a test bus to apply functional vectors, while the other uses a combination of scan insertion, memory BIST and test collars. IP protection issues and nonintrusive tracing are also discussed.","PeriodicalId":255826,"journal":{"name":"Proceedings IEEE European Test Workshop","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124974556","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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