Pub Date : 2007-08-01DOI: 10.1109/MWSCAS.2007.4488546
P. Sinha, M. Swamy, P. Meher
This paper presents a fully-pipelined CORDIC architecture for the simultaneous diagonalization of the covariance matrices. As an example, the problem of speech enhancement in a subspace based approach is considered, where in the covariance matrices of speech and noise are diagonalized concurrently. In order to compare the system performance of the proposed algorithm, objective measurements of speech enhancement are shown in terms of the signal to noise ratio and mean bark spectral distortion at various noise levels. In addition, the resource utilization of the proposed architecture on a Xilinx FPGA is studied.
{"title":"Fully-pipelined CORDIC implementation of subspace-based speech enhancement","authors":"P. Sinha, M. Swamy, P. Meher","doi":"10.1109/MWSCAS.2007.4488546","DOIUrl":"https://doi.org/10.1109/MWSCAS.2007.4488546","url":null,"abstract":"This paper presents a fully-pipelined CORDIC architecture for the simultaneous diagonalization of the covariance matrices. As an example, the problem of speech enhancement in a subspace based approach is considered, where in the covariance matrices of speech and noise are diagonalized concurrently. In order to compare the system performance of the proposed algorithm, objective measurements of speech enhancement are shown in terms of the signal to noise ratio and mean bark spectral distortion at various noise levels. In addition, the resource utilization of the proposed architecture on a Xilinx FPGA is studied.","PeriodicalId":256061,"journal":{"name":"2007 50th Midwest Symposium on Circuits and Systems","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126545360","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-08-01DOI: 10.1109/MWSCAS.2007.4488790
Teahyung Lee, Leung Kin Chiu, D.V. Anderson, R. Robucci, P. Hasler
An algorithm verification methodology for cooperative analog-digital signal processing imaging system is presented, and a simulation tool for software and hardware co-verification is developed for rapid algorithm verification. Unlike traditional behavioral simulation, the behavior of the architectural structure includes the characteristics of sensor and circuit mismatch and parasitic effects so that algorithm-level simulation can predict the performance of a true physical system. A case study of gradient- based optical flow estimation algorithm is demonstrated.
{"title":"Rapid algorithm verification for cooperative analog-digital imaging systems","authors":"Teahyung Lee, Leung Kin Chiu, D.V. Anderson, R. Robucci, P. Hasler","doi":"10.1109/MWSCAS.2007.4488790","DOIUrl":"https://doi.org/10.1109/MWSCAS.2007.4488790","url":null,"abstract":"An algorithm verification methodology for cooperative analog-digital signal processing imaging system is presented, and a simulation tool for software and hardware co-verification is developed for rapid algorithm verification. Unlike traditional behavioral simulation, the behavior of the architectural structure includes the characteristics of sensor and circuit mismatch and parasitic effects so that algorithm-level simulation can predict the performance of a true physical system. A case study of gradient- based optical flow estimation algorithm is demonstrated.","PeriodicalId":256061,"journal":{"name":"2007 50th Midwest Symposium on Circuits and Systems","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126547923","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-08-01DOI: 10.1109/MWSCAS.2007.4488607
Lee-Pierre Belley, M. Gabrea, C. Gargour
Separation of convolutive mixtures of speech sources is considered in this paper. Several approaches have been reported in the literature using statistical methods as well as transforms such as the short time Fourier transform (STFT) and the Paquet wavelet transform (PWT). In this paper we propose a new source separation method based on the independent component analysis (ICA) and utilizing the continuous wavelet transform (CWT). The experimental results obtained by our method have been investigated and compared with those generated by other approaches.
{"title":"Continuous wavelet transform based source separation","authors":"Lee-Pierre Belley, M. Gabrea, C. Gargour","doi":"10.1109/MWSCAS.2007.4488607","DOIUrl":"https://doi.org/10.1109/MWSCAS.2007.4488607","url":null,"abstract":"Separation of convolutive mixtures of speech sources is considered in this paper. Several approaches have been reported in the literature using statistical methods as well as transforms such as the short time Fourier transform (STFT) and the Paquet wavelet transform (PWT). In this paper we propose a new source separation method based on the independent component analysis (ICA) and utilizing the continuous wavelet transform (CWT). The experimental results obtained by our method have been investigated and compared with those generated by other approaches.","PeriodicalId":256061,"journal":{"name":"2007 50th Midwest Symposium on Circuits and Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125812752","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-08-01DOI: 10.1109/MWSCAS.2007.4488641
B. Maundy, S. Gift, P. Aronhime
Generalized voltage mode filters that employ two current feedback amplifiers are proposed in this paper. The new biquads are attractive because they offer improved gain sensitivities compared to single current feedback amplifier biquads. Also they do not employ the Z node and so a wide range range of commercial current feedback amplifiers can be used in their implementation. Theoretical results as well as experimental results are presented using AD844s in which the accessible Z node is not used.
{"title":"Generalized CFA filter topology based on gain blocks","authors":"B. Maundy, S. Gift, P. Aronhime","doi":"10.1109/MWSCAS.2007.4488641","DOIUrl":"https://doi.org/10.1109/MWSCAS.2007.4488641","url":null,"abstract":"Generalized voltage mode filters that employ two current feedback amplifiers are proposed in this paper. The new biquads are attractive because they offer improved gain sensitivities compared to single current feedback amplifier biquads. Also they do not employ the Z node and so a wide range range of commercial current feedback amplifiers can be used in their implementation. Theoretical results as well as experimental results are presented using AD844s in which the accessible Z node is not used.","PeriodicalId":256061,"journal":{"name":"2007 50th Midwest Symposium on Circuits and Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130931346","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-08-01DOI: 10.1109/MWSCAS.2007.4488769
C. Isert, M. McCoy, D. Jackson, J. Naber
Digital and mixed-signal circuits have been developed for use in an inductively-coupled RFID telemetry system that can interface with a sensor. The cells developed include a turn-on/brown-out detector, clock recovery circuit, a cyclic-redundancy code (CRC) generator, and a frequency-shift keying (FSK) modulator. These cells were designed for use in an RFID tag that also uses a novel approach to performing analog-to-digital conversion. The circuits were fabricated using the AMI 1.5 um CMOS process and tested using LabVIEWtrade. A key feature of these cells is their low current consumption of only 1-2 uA for the CRC generator and 5 uA for the clock recovery circuit.
数字和混合信号电路已经开发用于电感耦合RFID遥测系统，可以与传感器接口。开发的单元包括一个开/断电检测器、时钟恢复电路、一个循环冗余码(CRC)发生器和一个频移键控(FSK)调制器。这些单元被设计用于RFID标签，该标签也使用了一种新颖的方法来执行模数转换。电路采用AMI 1.5 um CMOS工艺制作，并使用LabVIEWtrade进行测试。这些电池的一个关键特征是它们的低电流消耗只有1-2 uA的CRC发生器和5 uA的时钟恢复电路。
{"title":"Digital and mixed-signal integrated circuits for an RFID telemetry system","authors":"C. Isert, M. McCoy, D. Jackson, J. Naber","doi":"10.1109/MWSCAS.2007.4488769","DOIUrl":"https://doi.org/10.1109/MWSCAS.2007.4488769","url":null,"abstract":"Digital and mixed-signal circuits have been developed for use in an inductively-coupled RFID telemetry system that can interface with a sensor. The cells developed include a turn-on/brown-out detector, clock recovery circuit, a cyclic-redundancy code (CRC) generator, and a frequency-shift keying (FSK) modulator. These cells were designed for use in an RFID tag that also uses a novel approach to performing analog-to-digital conversion. The circuits were fabricated using the AMI 1.5 um CMOS process and tested using LabVIEWtrade. A key feature of these cells is their low current consumption of only 1-2 uA for the CRC generator and 5 uA for the clock recovery circuit.","PeriodicalId":256061,"journal":{"name":"2007 50th Midwest Symposium on Circuits and Systems","volume":"2229 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130186735","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-08-01DOI: 10.1109/MWSCAS.2007.4488792
J. Ravindra, M. Srinivas
In high speed digital integrated circuits, inductive- coupling effects in interconnects can be significant and should be included for accurate delay-noise analysis. In this paper, an analytical framework to model delay and slew metrics in coupled RLC interconnects is presented. The proposed models are based on difference model approach which involves the dynamic part of system transfer function. The models are generic in nature and can be applied to symmetric driver-and-line configurations for aggressor and victim wires. The model is compared against SPICE simulations and is shown to capture delay and slew accurately. Over a large set of random test cases, the average error in delay and slew estimation is approximately 1.8% and 3.2% respectively. A key feature of the new model is that its derivation and form enables an insight into the inductively coupled noise-waveform. Due to its simplicity and physical nature, the proposed model can be applied to asymmetric transmission lines. The obtained results indicate that common (capacitive) noise-avoidance techniques can behave quite differently when capacitive and inductive coupling are considered together.
{"title":"Delay and slew analysis of VLSI interconnects using difference model approach","authors":"J. Ravindra, M. Srinivas","doi":"10.1109/MWSCAS.2007.4488792","DOIUrl":"https://doi.org/10.1109/MWSCAS.2007.4488792","url":null,"abstract":"In high speed digital integrated circuits, inductive- coupling effects in interconnects can be significant and should be included for accurate delay-noise analysis. In this paper, an analytical framework to model delay and slew metrics in coupled RLC interconnects is presented. The proposed models are based on difference model approach which involves the dynamic part of system transfer function. The models are generic in nature and can be applied to symmetric driver-and-line configurations for aggressor and victim wires. The model is compared against SPICE simulations and is shown to capture delay and slew accurately. Over a large set of random test cases, the average error in delay and slew estimation is approximately 1.8% and 3.2% respectively. A key feature of the new model is that its derivation and form enables an insight into the inductively coupled noise-waveform. Due to its simplicity and physical nature, the proposed model can be applied to asymmetric transmission lines. The obtained results indicate that common (capacitive) noise-avoidance techniques can behave quite differently when capacitive and inductive coupling are considered together.","PeriodicalId":256061,"journal":{"name":"2007 50th Midwest Symposium on Circuits and Systems","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116176637","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-08-01DOI: 10.1109/MWSCAS.2007.4488754
B. Pontikakis, F. Boyer, Y. Savaria, H. Bui
This paper proposes an all-digital, automated, clock generator based on a free-running oscillator that can generate arbitrarily precise frequencies. The entire system can be implemented using standard cells and even has a compensation system to mitigate the effects of environmental variations on frequency. The design is implemented in VHDL and synthesized using Artisan standard-cells in TSMC's 180 nm CMOS technology. Post-layout timing analysis shows that the proposed free-running period synthesizer (FPRS) can operate at a frequency of up to 175 MHz. The architecture was also validated with an implementation on a Xilinx's Spartan 3 FPGA that works at 80 MHz. In both implementations, the worst case peak to peak jitter of the output clock is equal to one period of the free-running oscillator.
{"title":"Precise free-running period synthesizer (FRPS) with process and temperature compensation","authors":"B. Pontikakis, F. Boyer, Y. Savaria, H. Bui","doi":"10.1109/MWSCAS.2007.4488754","DOIUrl":"https://doi.org/10.1109/MWSCAS.2007.4488754","url":null,"abstract":"This paper proposes an all-digital, automated, clock generator based on a free-running oscillator that can generate arbitrarily precise frequencies. The entire system can be implemented using standard cells and even has a compensation system to mitigate the effects of environmental variations on frequency. The design is implemented in VHDL and synthesized using Artisan standard-cells in TSMC's 180 nm CMOS technology. Post-layout timing analysis shows that the proposed free-running period synthesizer (FPRS) can operate at a frequency of up to 175 MHz. The architecture was also validated with an implementation on a Xilinx's Spartan 3 FPGA that works at 80 MHz. In both implementations, the worst case peak to peak jitter of the output clock is equal to one period of the free-running oscillator.","PeriodicalId":256061,"journal":{"name":"2007 50th Midwest Symposium on Circuits and Systems","volume":"303 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116219051","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-08-01DOI: 10.1109/MWSCAS.2007.4488666
J. Colomer, P. Miribel, A. Saiz-Vela, J. Brufau, J. Maa, M. Puig-Vidal, J. Samitier
Nowadays, there is an important interest in smart wireless sensors. A key point in their development is the way they are powered. Piezoelectric energy conversion can be used for such purpose. In this paper, a novel architecture that combines in a single integrated circuit the power conditioning circuitry needed to use piezoelectric energy conversion and an embedded temperature sensor is presented.
{"title":"SiP power management unit with embedded temperature sensor powered by piezoelectric vibration energy harvesting","authors":"J. Colomer, P. Miribel, A. Saiz-Vela, J. Brufau, J. Maa, M. Puig-Vidal, J. Samitier","doi":"10.1109/MWSCAS.2007.4488666","DOIUrl":"https://doi.org/10.1109/MWSCAS.2007.4488666","url":null,"abstract":"Nowadays, there is an important interest in smart wireless sensors. A key point in their development is the way they are powered. Piezoelectric energy conversion can be used for such purpose. In this paper, a novel architecture that combines in a single integrated circuit the power conditioning circuitry needed to use piezoelectric energy conversion and an embedded temperature sensor is presented.","PeriodicalId":256061,"journal":{"name":"2007 50th Midwest Symposium on Circuits and Systems","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116247630","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-08-01DOI: 10.1109/MWSCAS.2007.4488757
Rong Luo, Peng Sun
In this paper, we present an advanced placement which aims at both flattening the temperature and decreasing the area in SoC floorplanning. The placement process is ingeniously converted into a quasi TSP problem and is solved by ant colony optimization (ACO) algorithm. Compared to traditional algorithms based on O-tree and B*-tree optimization, our results show great improvement in calculating speed while promising satisfying accuracy.
{"title":"An advanced placement method for SoC floorplanning based on ACO algorithm","authors":"Rong Luo, Peng Sun","doi":"10.1109/MWSCAS.2007.4488757","DOIUrl":"https://doi.org/10.1109/MWSCAS.2007.4488757","url":null,"abstract":"In this paper, we present an advanced placement which aims at both flattening the temperature and decreasing the area in SoC floorplanning. The placement process is ingeniously converted into a quasi TSP problem and is solved by ant colony optimization (ACO) algorithm. Compared to traditional algorithms based on O-tree and B*-tree optimization, our results show great improvement in calculating speed while promising satisfying accuracy.","PeriodicalId":256061,"journal":{"name":"2007 50th Midwest Symposium on Circuits and Systems","volume":"75 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116437035","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-08-01DOI: 10.1109/MWSCAS.2007.4488540
H. Okazaki, T. Shidara, Y. Okubo
The purpose of this paper is to present an explicit analytical representation for piecewise polynomial functions and to illustrate the application of this representation in cognitive processing in computer vision.
本文的目的是提出分段多项式函数的显式解析表示法，并举例说明这种表示法在计算机视觉认知处理中的应用。
{"title":"A piecewise polynomial canonical representing function and its application to image edge processing","authors":"H. Okazaki, T. Shidara, Y. Okubo","doi":"10.1109/MWSCAS.2007.4488540","DOIUrl":"https://doi.org/10.1109/MWSCAS.2007.4488540","url":null,"abstract":"The purpose of this paper is to present an explicit analytical representation for piecewise polynomial functions and to illustrate the application of this representation in cognitive processing in computer vision.","PeriodicalId":256061,"journal":{"name":"2007 50th Midwest Symposium on Circuits and Systems","volume":"99 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127093122","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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