Pub Date : 2007-08-01DOI: 10.1109/MWSCAS.2007.4488633
S. Vatti, C. Papavassiliou
A novel bias and tuning scheme for capacitively cross-coupled inductance-capacitance (LC) oscillators is presented. This scheme allows more flexibility in defining the operating point of the cross-coupled transistors, together with wide frequency tunability. A capacitively coupled LC oscillator at 5 GHz has been designed in CMOS UMC 0.18 mum technology. The bias network is realized with an all-transistor voltage reference. The oscillator is tunable in the 5 GHz-9 GHz frequency range. Phase noise performance is maintained over the entire frequency range, with -58 dBc/Hz at 100 kHz offset and -116 dBc/Hz at 1 MHz.
{"title":"A capacitively-coupled 5GHz CMOS LC oscillator with bias tuning capability","authors":"S. Vatti, C. Papavassiliou","doi":"10.1109/MWSCAS.2007.4488633","DOIUrl":"https://doi.org/10.1109/MWSCAS.2007.4488633","url":null,"abstract":"A novel bias and tuning scheme for capacitively cross-coupled inductance-capacitance (LC) oscillators is presented. This scheme allows more flexibility in defining the operating point of the cross-coupled transistors, together with wide frequency tunability. A capacitively coupled LC oscillator at 5 GHz has been designed in CMOS UMC 0.18 mum technology. The bias network is realized with an all-transistor voltage reference. The oscillator is tunable in the 5 GHz-9 GHz frequency range. Phase noise performance is maintained over the entire frequency range, with -58 dBc/Hz at 100 kHz offset and -116 dBc/Hz at 1 MHz.","PeriodicalId":256061,"journal":{"name":"2007 50th Midwest Symposium on Circuits and Systems","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123721975","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-08-01DOI: 10.1109/MWSCAS.2007.4488684
Yanjie Wang, S. Kilambi, K. Iniewski, V. Gaudet
A fully integrated CMOS impulse-based transmitter with on-off keying (OOK) modulation scheme, for ultra- wideband (UWB) impulse radio (IR) system has been designed in a standard TSMC 0.18 mum CMOS technology. A novel Gaussian mono-pulse generator using simple and robust design method has been presented. On-chip pulse shaping using LC Band-Pass Filter (BPF) is developed to meet the Federal Communications Commission (FCC) spectrum requirement. The proposed UWB transmitter has been laid out and post-layout simulation results are analyzed. A Gaussian mono-pulse of less than 100 ps falling/rising time with a 130 mVpp amplitude was observed, at a clock frequency of 500 MHz. The total power dissipation of the transmitter is 1.2 mW with only 316 muW consumed by impulse generator. The output of the transmitter is 48 mVpp under a 1.2 V power supply.
{"title":"A fully integrated CMOS transmitter design for IR-UWB communication systems","authors":"Yanjie Wang, S. Kilambi, K. Iniewski, V. Gaudet","doi":"10.1109/MWSCAS.2007.4488684","DOIUrl":"https://doi.org/10.1109/MWSCAS.2007.4488684","url":null,"abstract":"A fully integrated CMOS impulse-based transmitter with on-off keying (OOK) modulation scheme, for ultra- wideband (UWB) impulse radio (IR) system has been designed in a standard TSMC 0.18 mum CMOS technology. A novel Gaussian mono-pulse generator using simple and robust design method has been presented. On-chip pulse shaping using LC Band-Pass Filter (BPF) is developed to meet the Federal Communications Commission (FCC) spectrum requirement. The proposed UWB transmitter has been laid out and post-layout simulation results are analyzed. A Gaussian mono-pulse of less than 100 ps falling/rising time with a 130 mVpp amplitude was observed, at a clock frequency of 500 MHz. The total power dissipation of the transmitter is 1.2 mW with only 316 muW consumed by impulse generator. The output of the transmitter is 48 mVpp under a 1.2 V power supply.","PeriodicalId":256061,"journal":{"name":"2007 50th Midwest Symposium on Circuits and Systems","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124906266","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-08-01DOI: 10.1109/MWSCAS.2007.4488740
Heather A. Wake, Martin A. Brooke
Electrophoresis is a valuable technique for the separation and analysis of chemical and biological specimens. Typically, an electric field is established between two electrodes that induces charged particles to move and separate. Instead of using only one electrode at each end of the separation area, this paper presents a very small, low voltage system that utilizes electrodes beneath the entire separation area, enabling better control of high electric fields using very small voltages over small areas. By employing multiple electrodes, strong electric fields can be established using very low voltages (less than 5 V) over small distances. The electrodes are also used to sense sample locations and concentrations using amperometric detection, and integrated electronics allow precise control over the fields. The system presented here includes 100 individually addressable electrodes and their corresponding circuitry on a 2 mm by 2 mm chip and is designed using the AMI 1.5 mum CMOS process available through MOSIS.
电泳是一种有价值的分离和分析化学和生物样品的技术。通常，在两个电极之间建立电场，诱导带电粒子移动和分离。本文提出了一种非常小的低压系统，该系统利用整个分离区域下方的电极，而不是在分离区域的每一端只使用一个电极，从而可以在小区域上使用非常小的电压来更好地控制高电场。通过使用多个电极，可以在很小的距离上使用非常低的电压(小于5 V)建立强电场。电极也用于感应样品的位置和浓度使用安培检测，集成电子允许精确控制领域。该系统包括100个可单独寻址的电极及其在2mm × 2mm芯片上的相应电路，并采用MOSIS提供的AMI 1.5 μ m CMOS工艺设计。
{"title":"Low voltage electrophoresis on a CMOS chip","authors":"Heather A. Wake, Martin A. Brooke","doi":"10.1109/MWSCAS.2007.4488740","DOIUrl":"https://doi.org/10.1109/MWSCAS.2007.4488740","url":null,"abstract":"Electrophoresis is a valuable technique for the separation and analysis of chemical and biological specimens. Typically, an electric field is established between two electrodes that induces charged particles to move and separate. Instead of using only one electrode at each end of the separation area, this paper presents a very small, low voltage system that utilizes electrodes beneath the entire separation area, enabling better control of high electric fields using very small voltages over small areas. By employing multiple electrodes, strong electric fields can be established using very low voltages (less than 5 V) over small distances. The electrodes are also used to sense sample locations and concentrations using amperometric detection, and integrated electronics allow precise control over the fields. The system presented here includes 100 individually addressable electrodes and their corresponding circuitry on a 2 mm by 2 mm chip and is designed using the AMI 1.5 mum CMOS process available through MOSIS.","PeriodicalId":256061,"journal":{"name":"2007 50th Midwest Symposium on Circuits and Systems","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125071421","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-08-01DOI: 10.1109/MWSCAS.2007.4488784
Yunsi Fei, Hai Lin, Xuan Guan
Application-specific instruction set processor (ASIP) has emerged as an important design choice for embedded systems. It can achieve both high flexibility offered by the base processor core and high performance and energy-efficiency offered by the dedicated hardware extensions. Although a lot of efforts have been devoted to computation acceleration (e.g., automatic custom instruction identification and synthesis), the limited on-chip data storage elements, including the register file and data cache, have become a potential performance bottleneck. In this paper, we propose a hardware/software cooperative approach to utilize the custom registers for reducing the data traffic between the processor and memory through efficient communications between the base processor core and custom hardware extensions. Our experimental results demonstrate that promising performance improvements can be achieved.
{"title":"A hardware/software cooperative approach for reducing memory traffic in application-specific instruction set processors","authors":"Yunsi Fei, Hai Lin, Xuan Guan","doi":"10.1109/MWSCAS.2007.4488784","DOIUrl":"https://doi.org/10.1109/MWSCAS.2007.4488784","url":null,"abstract":"Application-specific instruction set processor (ASIP) has emerged as an important design choice for embedded systems. It can achieve both high flexibility offered by the base processor core and high performance and energy-efficiency offered by the dedicated hardware extensions. Although a lot of efforts have been devoted to computation acceleration (e.g., automatic custom instruction identification and synthesis), the limited on-chip data storage elements, including the register file and data cache, have become a potential performance bottleneck. In this paper, we propose a hardware/software cooperative approach to utilize the custom registers for reducing the data traffic between the processor and memory through efficient communications between the base processor core and custom hardware extensions. Our experimental results demonstrate that promising performance improvements can be achieved.","PeriodicalId":256061,"journal":{"name":"2007 50th Midwest Symposium on Circuits and Systems","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121524740","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-08-01DOI: 10.1109/MWSCAS.2007.4488724
M. A. Turi, J. Delgado-Frías
Two novel memory decoder designs for reducing energy consumption and delay are presented in this paper. These two decoding schemes are compared to the conventional NOR decoder. Fewer word lines are charged and discharged by the proposed schemes which leads to less energy dissipation. Energy, delay, and area calculations are provided for all three designs under analysis. The two novel decoder schemes range from dissipating 3.9% to 23.6% of the energy dissipated by the conventional decoder. The delays of these designs are 80.8% of the conventional decoder delay. Simulations of the three decoders are performed using a 90 nm CMOS technology.
{"title":"Reducing power in memory decoders by means of selective precharge schemes","authors":"M. A. Turi, J. Delgado-Frías","doi":"10.1109/MWSCAS.2007.4488724","DOIUrl":"https://doi.org/10.1109/MWSCAS.2007.4488724","url":null,"abstract":"Two novel memory decoder designs for reducing energy consumption and delay are presented in this paper. These two decoding schemes are compared to the conventional NOR decoder. Fewer word lines are charged and discharged by the proposed schemes which leads to less energy dissipation. Energy, delay, and area calculations are provided for all three designs under analysis. The two novel decoder schemes range from dissipating 3.9% to 23.6% of the energy dissipated by the conventional decoder. The delays of these designs are 80.8% of the conventional decoder delay. Simulations of the three decoders are performed using a 90 nm CMOS technology.","PeriodicalId":256061,"journal":{"name":"2007 50th Midwest Symposium on Circuits and Systems","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123927526","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A compact size and high efficient single-inductor dual-output (SIDO) DC-DC converter is proposed. Generally speaking, it is important to implement DC-DC converters with minimized components and small footprint area. However, large external compensated resistors and capacitors are required to stabilize DC-DC converters. The proposed SIDO DC-DC converter not only provides dual output sources but also has minimized cross regulation without using any external compensated components. Importantly, our proposed mode-switch technique corrects the mistakes in the previous design [1], which didn't mention the unstable condition. Besides, owing to dynamically adjusting DC current level like CCM operation, the SIDO DC-DC converter achieves high conversion efficiency. Experimental results show a high efficiency from 85% at light load condition to 94% at heavy load condition.
{"title":"Single-inductor dual-output (SIDO) DC-DC converters for minimized cross regulation and high efficiency in SoC supplying systems","authors":"Ming-Hsin Huang, Hong-Wei Huang, Jiun-Yan Peng, Tzung-Ling Tsai, Min-Chin Lee, Ching-Sung Wang, Ke-Horng Chen","doi":"10.1109/MWSCAS.2007.4488644","DOIUrl":"https://doi.org/10.1109/MWSCAS.2007.4488644","url":null,"abstract":"A compact size and high efficient single-inductor dual-output (SIDO) DC-DC converter is proposed. Generally speaking, it is important to implement DC-DC converters with minimized components and small footprint area. However, large external compensated resistors and capacitors are required to stabilize DC-DC converters. The proposed SIDO DC-DC converter not only provides dual output sources but also has minimized cross regulation without using any external compensated components. Importantly, our proposed mode-switch technique corrects the mistakes in the previous design [1], which didn't mention the unstable condition. Besides, owing to dynamically adjusting DC current level like CCM operation, the SIDO DC-DC converter achieves high conversion efficiency. Experimental results show a high efficiency from 85% at light load condition to 94% at heavy load condition.","PeriodicalId":256061,"journal":{"name":"2007 50th Midwest Symposium on Circuits and Systems","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122683369","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-08-01DOI: 10.1109/MWSCAS.2007.4488606
R. Ranganathan, Thomas T. Yang, W. Mikhael
This paper presents a novel realization of the complex block adaptive independent component analysis algorithm. The algorithm optimally updates the real and imaginary components of the weight vector independently. The new implementation is employed for the separation of complex signals with known source distributions, a scenario frequently encountered in practice. Under time-varying channel conditions, the performance of the proposed method is compared with the widely known Complex Fast-ICA. Simulation results show that this new technique exhibits superior performance in time varying channel conditions in terms of convergence speed. In addition, the performance of the proposed method is independent of the processing block length and is achieved without any additional cost in computational complexity.
{"title":"Separation of complex signals with known source distributions in time-varying channels using optimum complex block adaptive ICA","authors":"R. Ranganathan, Thomas T. Yang, W. Mikhael","doi":"10.1109/MWSCAS.2007.4488606","DOIUrl":"https://doi.org/10.1109/MWSCAS.2007.4488606","url":null,"abstract":"This paper presents a novel realization of the complex block adaptive independent component analysis algorithm. The algorithm optimally updates the real and imaginary components of the weight vector independently. The new implementation is employed for the separation of complex signals with known source distributions, a scenario frequently encountered in practice. Under time-varying channel conditions, the performance of the proposed method is compared with the widely known Complex Fast-ICA. Simulation results show that this new technique exhibits superior performance in time varying channel conditions in terms of convergence speed. In addition, the performance of the proposed method is independent of the processing block length and is achieved without any additional cost in computational complexity.","PeriodicalId":256061,"journal":{"name":"2007 50th Midwest Symposium on Circuits and Systems","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127915745","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-08-01DOI: 10.1109/MWSCAS.2007.4488641
B. Maundy, S. Gift, P. Aronhime
Generalized voltage mode filters that employ two current feedback amplifiers are proposed in this paper. The new biquads are attractive because they offer improved gain sensitivities compared to single current feedback amplifier biquads. Also they do not employ the Z node and so a wide range range of commercial current feedback amplifiers can be used in their implementation. Theoretical results as well as experimental results are presented using AD844s in which the accessible Z node is not used.
{"title":"Generalized CFA filter topology based on gain blocks","authors":"B. Maundy, S. Gift, P. Aronhime","doi":"10.1109/MWSCAS.2007.4488641","DOIUrl":"https://doi.org/10.1109/MWSCAS.2007.4488641","url":null,"abstract":"Generalized voltage mode filters that employ two current feedback amplifiers are proposed in this paper. The new biquads are attractive because they offer improved gain sensitivities compared to single current feedback amplifier biquads. Also they do not employ the Z node and so a wide range range of commercial current feedback amplifiers can be used in their implementation. Theoretical results as well as experimental results are presented using AD844s in which the accessible Z node is not used.","PeriodicalId":256061,"journal":{"name":"2007 50th Midwest Symposium on Circuits and Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130931346","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-08-01DOI: 10.1109/MWSCAS.2007.4488769
C. Isert, M. McCoy, D. Jackson, J. Naber
Digital and mixed-signal circuits have been developed for use in an inductively-coupled RFID telemetry system that can interface with a sensor. The cells developed include a turn-on/brown-out detector, clock recovery circuit, a cyclic-redundancy code (CRC) generator, and a frequency-shift keying (FSK) modulator. These cells were designed for use in an RFID tag that also uses a novel approach to performing analog-to-digital conversion. The circuits were fabricated using the AMI 1.5 um CMOS process and tested using LabVIEWtrade. A key feature of these cells is their low current consumption of only 1-2 uA for the CRC generator and 5 uA for the clock recovery circuit.
数字和混合信号电路已经开发用于电感耦合RFID遥测系统，可以与传感器接口。开发的单元包括一个开/断电检测器、时钟恢复电路、一个循环冗余码(CRC)发生器和一个频移键控(FSK)调制器。这些单元被设计用于RFID标签，该标签也使用了一种新颖的方法来执行模数转换。电路采用AMI 1.5 um CMOS工艺制作，并使用LabVIEWtrade进行测试。这些电池的一个关键特征是它们的低电流消耗只有1-2 uA的CRC发生器和5 uA的时钟恢复电路。
{"title":"Digital and mixed-signal integrated circuits for an RFID telemetry system","authors":"C. Isert, M. McCoy, D. Jackson, J. Naber","doi":"10.1109/MWSCAS.2007.4488769","DOIUrl":"https://doi.org/10.1109/MWSCAS.2007.4488769","url":null,"abstract":"Digital and mixed-signal circuits have been developed for use in an inductively-coupled RFID telemetry system that can interface with a sensor. The cells developed include a turn-on/brown-out detector, clock recovery circuit, a cyclic-redundancy code (CRC) generator, and a frequency-shift keying (FSK) modulator. These cells were designed for use in an RFID tag that also uses a novel approach to performing analog-to-digital conversion. The circuits were fabricated using the AMI 1.5 um CMOS process and tested using LabVIEWtrade. A key feature of these cells is their low current consumption of only 1-2 uA for the CRC generator and 5 uA for the clock recovery circuit.","PeriodicalId":256061,"journal":{"name":"2007 50th Midwest Symposium on Circuits and Systems","volume":"2229 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130186735","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-08-01DOI: 10.1109/MWSCAS.2007.4488822
N. Beilleau, C. Ouffoue, H. Aboushady
In this paper, we present a systematic technique to design bandpass LC Sigma Delta modulators with sinusoidal feedback DACs. The output resistance of the DAC degrades the quality factor of the LC resonator and the DAC output capacitance modifies its resonance frequency. It is shown that the DAC output resistance should be taken into account while designing the Q enhancement circuit of the integrated LC resonator. The resonance frequency is adjusted by modifiying the parallel capacitor of the LC resonator. Using the proposed method, different sinusoidal 3.256 GHz DACs are designed in a CMOS 0.13 mum process. Simulation results are presented to compare their performances in the context of an undersampled LC SigmaDelta modulator.
{"title":"Sinusoidal RF DACs for undersampled LC bandpass ∑Δ modulabrs","authors":"N. Beilleau, C. Ouffoue, H. Aboushady","doi":"10.1109/MWSCAS.2007.4488822","DOIUrl":"https://doi.org/10.1109/MWSCAS.2007.4488822","url":null,"abstract":"In this paper, we present a systematic technique to design bandpass LC Sigma Delta modulators with sinusoidal feedback DACs. The output resistance of the DAC degrades the quality factor of the LC resonator and the DAC output capacitance modifies its resonance frequency. It is shown that the DAC output resistance should be taken into account while designing the Q enhancement circuit of the integrated LC resonator. The resonance frequency is adjusted by modifiying the parallel capacitor of the LC resonator. Using the proposed method, different sinusoidal 3.256 GHz DACs are designed in a CMOS 0.13 mum process. Simulation results are presented to compare their performances in the context of an undersampled LC SigmaDelta modulator.","PeriodicalId":256061,"journal":{"name":"2007 50th Midwest Symposium on Circuits and Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130761914","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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