Pub Date : 2007-08-01DOI: 10.1109/MWSCAS.2007.4488796
Hua Tang, T. Kwon, Yi Zheng, Hairong Chang
It is well known that vehicle tracking processes are very computationally intensive. Traditionally, vehicle tracking algorithms have been implemented using software approaches. The goal of this paper is to investigate the feasibility of developing a hardware-based tracking system. We propose a tracking algorithm with vehicle motion detection based on block matching algorithm, which is well suited to customized hardware implementation. The proposed tracking algorithm is first simulated in MATLAB and the CMOS circuit design was simulated in Cadence. When tested on traffic images captured from an intersection, it is found that vehicle movements can be accurately identified in spite of some noisy motion. Also, the estimated computational time for the hardware based tracking system is much reduced compared to traditional software-based tracking system.
{"title":"Designing CMOS hardware processor for vehicle tracking","authors":"Hua Tang, T. Kwon, Yi Zheng, Hairong Chang","doi":"10.1109/MWSCAS.2007.4488796","DOIUrl":"https://doi.org/10.1109/MWSCAS.2007.4488796","url":null,"abstract":"It is well known that vehicle tracking processes are very computationally intensive. Traditionally, vehicle tracking algorithms have been implemented using software approaches. The goal of this paper is to investigate the feasibility of developing a hardware-based tracking system. We propose a tracking algorithm with vehicle motion detection based on block matching algorithm, which is well suited to customized hardware implementation. The proposed tracking algorithm is first simulated in MATLAB and the CMOS circuit design was simulated in Cadence. When tested on traffic images captured from an intersection, it is found that vehicle movements can be accurately identified in spite of some noisy motion. Also, the estimated computational time for the hardware based tracking system is much reduced compared to traditional software-based tracking system.","PeriodicalId":256061,"journal":{"name":"2007 50th Midwest Symposium on Circuits and Systems","volume":"1 3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123178010","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-08-01DOI: 10.1109/MWSCAS.2007.4488702
O. Alonso, R. Casanova, A. Sanuy, A. Arbat, J. Canals, Á. Diéguez, J. Samitier
In this paper a low power transceiver for short-range IR-communications between robots is described. The mm3- sized robots will be deployed in an arena of A4 sheet size with controlled illumination conditions. The transceiver can manage variations of background light from point to point in the arena, interferences induced by other robots and deals with the inter-robot distance, i.e., the amplitude of the signal to be detected.
{"title":"A low power IC to enable optical communications in a robotic swarm","authors":"O. Alonso, R. Casanova, A. Sanuy, A. Arbat, J. Canals, Á. Diéguez, J. Samitier","doi":"10.1109/MWSCAS.2007.4488702","DOIUrl":"https://doi.org/10.1109/MWSCAS.2007.4488702","url":null,"abstract":"In this paper a low power transceiver for short-range IR-communications between robots is described. The mm3- sized robots will be deployed in an arena of A4 sheet size with controlled illumination conditions. The transceiver can manage variations of background light from point to point in the arena, interferences induced by other robots and deals with the inter-robot distance, i.e., the amplitude of the signal to be detected.","PeriodicalId":256061,"journal":{"name":"2007 50th Midwest Symposium on Circuits and Systems","volume":"204 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134299252","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-08-01DOI: 10.1109/MWSCAS.2007.4488611
C. Shahnaz, W. Zhu, M. Ahmad
In this paper, a robust pitch detection algorithm is proposed for speech signals severely corrupted by a non-stationary noise. Using low-frequency band of noisy speech, an effective noise reduction approach is first formulated for power spectral subtraction to track the time-variation of the non-stationary noise prior to pitch detection. Then, a new normalized circular difference function of the enhanced speech, which almost conquers the constraint of overlapping between the first formant and the pitch, is proposed. Simulation results using the Keele reference database demonstrate a better efficacy of the proposed algorithm relative to some of the existing methods in a practical multi-talker babble noise environment.
{"title":"A robust pitch detection algorithm for speech signals in a practical noisy environment","authors":"C. Shahnaz, W. Zhu, M. Ahmad","doi":"10.1109/MWSCAS.2007.4488611","DOIUrl":"https://doi.org/10.1109/MWSCAS.2007.4488611","url":null,"abstract":"In this paper, a robust pitch detection algorithm is proposed for speech signals severely corrupted by a non-stationary noise. Using low-frequency band of noisy speech, an effective noise reduction approach is first formulated for power spectral subtraction to track the time-variation of the non-stationary noise prior to pitch detection. Then, a new normalized circular difference function of the enhanced speech, which almost conquers the constraint of overlapping between the first formant and the pitch, is proposed. Simulation results using the Keele reference database demonstrate a better efficacy of the proposed algorithm relative to some of the existing methods in a practical multi-talker babble noise environment.","PeriodicalId":256061,"journal":{"name":"2007 50th Midwest Symposium on Circuits and Systems","volume":"52 24","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131639237","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-08-01DOI: 10.1109/MWSCAS.2007.4488819
Y. Kang, J. Draper
Memory latency is a critical issue for conventional high-speed computing platforms, and it is becoming a common problem in embedded and CMP (chip multiprocessing) systems as well. Conventional processors typically adopt caches and a load/store queue (LSQ) to address the processor-to-memory bottleneck. However, the conventional LSQ design, which has a large number of entries, is not appropriate for embedded systems due to its area and power hungry out-of- order speculation. A compact, low-power load/store buffer that also provides significant performance improvement is essential for such systems. In this paper, we propose an area-efficient wideword load/store buffer (WLSB) which supports both WideWord (256-bit) and scalar (32-bit) load/store instructions for a recently fabricated PIM (processing-in-memory) device. Given its small size, the 4 entry WLSB yields a 57.33% load hit rate on SPEC2K benchmarks. This result is 5.72% better as compared to a less area-efficient 32-entry fully associative scalar load/store buffer (SLSB). The WLSB was synthesized in IBM 90 nm technology, and the resulting implementation occupies less than a seventh of a square mm and is projected to run at 1.6 ns cycle time with 15.72 mW of dynamic power dissipation. This paper demonstrates how this very small-entry buffer can affect the load hit rate and quantifies the design trade-offs between wide small-entry and narrow large-entry buffers with respect to size, power, load hit ratio and clock speed. Although this WLSB has been specifically designed to benefit a PIM architecture, it is expected to be useful for other embedded processing platforms and CMPs due to emphasized area/power constraints.
{"title":"Design trade-offs for load/store buffers in embedded processing environments","authors":"Y. Kang, J. Draper","doi":"10.1109/MWSCAS.2007.4488819","DOIUrl":"https://doi.org/10.1109/MWSCAS.2007.4488819","url":null,"abstract":"Memory latency is a critical issue for conventional high-speed computing platforms, and it is becoming a common problem in embedded and CMP (chip multiprocessing) systems as well. Conventional processors typically adopt caches and a load/store queue (LSQ) to address the processor-to-memory bottleneck. However, the conventional LSQ design, which has a large number of entries, is not appropriate for embedded systems due to its area and power hungry out-of- order speculation. A compact, low-power load/store buffer that also provides significant performance improvement is essential for such systems. In this paper, we propose an area-efficient wideword load/store buffer (WLSB) which supports both WideWord (256-bit) and scalar (32-bit) load/store instructions for a recently fabricated PIM (processing-in-memory) device. Given its small size, the 4 entry WLSB yields a 57.33% load hit rate on SPEC2K benchmarks. This result is 5.72% better as compared to a less area-efficient 32-entry fully associative scalar load/store buffer (SLSB). The WLSB was synthesized in IBM 90 nm technology, and the resulting implementation occupies less than a seventh of a square mm and is projected to run at 1.6 ns cycle time with 15.72 mW of dynamic power dissipation. This paper demonstrates how this very small-entry buffer can affect the load hit rate and quantifies the design trade-offs between wide small-entry and narrow large-entry buffers with respect to size, power, load hit ratio and clock speed. Although this WLSB has been specifically designed to benefit a PIM architecture, it is expected to be useful for other embedded processing platforms and CMPs due to emphasized area/power constraints.","PeriodicalId":256061,"journal":{"name":"2007 50th Midwest Symposium on Circuits and Systems","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129076283","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-08-01DOI: 10.1109/MWSCAS.2007.4488621
E. Eschenko, M. S. Candidate, K. Entesari
A state of the art 16/17 prescaler using current mode logic (CML) D-Flip Flops, CMOS inverters, and transmission gates for the .18mu TSMC process with a 1.8 V supply voltage is presented. The prescaler consists of a 4/5 synchronous core and a feedback loop which modulates the 4/5 core to produce a division ratio of 16/17. Instead of employing power hungry CML, the feedback circuit takes advantage of low power NOR and AND gates realized in transmission gate logic (TGL) to reduce the power consumption. To the best of our knowledge, this technique has never been used in a high frequency prescaler before. Additionally, this work will serve as a comprehensive description of the numerous considerations of prescaler design including explanation of gate-level design and transistor level optimization. Furthermore, digital circuit output is efficiently buffered with CMOS inverters for rail- to-rail operation, maximizing slew rate which minimizes phase noise. The simulated phase noise is -150 dBc/Hz @ 1 MHz and the input bandwidth is 2 GHz (11 GHz and 13 GHz). The power consumption of the entire prescaler is 18.5 mW. All of the above results were obtained from post-layout simulations. Circuit layout has been completed and sent for fabrication.
{"title":"A low noise 13 GHz power efficient 16/17 prescaler with rail to rail output amplitude","authors":"E. Eschenko, M. S. Candidate, K. Entesari","doi":"10.1109/MWSCAS.2007.4488621","DOIUrl":"https://doi.org/10.1109/MWSCAS.2007.4488621","url":null,"abstract":"A state of the art 16/17 prescaler using current mode logic (CML) D-Flip Flops, CMOS inverters, and transmission gates for the .18mu TSMC process with a 1.8 V supply voltage is presented. The prescaler consists of a 4/5 synchronous core and a feedback loop which modulates the 4/5 core to produce a division ratio of 16/17. Instead of employing power hungry CML, the feedback circuit takes advantage of low power NOR and AND gates realized in transmission gate logic (TGL) to reduce the power consumption. To the best of our knowledge, this technique has never been used in a high frequency prescaler before. Additionally, this work will serve as a comprehensive description of the numerous considerations of prescaler design including explanation of gate-level design and transistor level optimization. Furthermore, digital circuit output is efficiently buffered with CMOS inverters for rail- to-rail operation, maximizing slew rate which minimizes phase noise. The simulated phase noise is -150 dBc/Hz @ 1 MHz and the input bandwidth is 2 GHz (11 GHz and 13 GHz). The power consumption of the entire prescaler is 18.5 mW. All of the above results were obtained from post-layout simulations. Circuit layout has been completed and sent for fabrication.","PeriodicalId":256061,"journal":{"name":"2007 50th Midwest Symposium on Circuits and Systems","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133650212","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-08-01DOI: 10.1109/MWSCAS.2007.4488754
B. Pontikakis, F. Boyer, Y. Savaria, H. Bui
This paper proposes an all-digital, automated, clock generator based on a free-running oscillator that can generate arbitrarily precise frequencies. The entire system can be implemented using standard cells and even has a compensation system to mitigate the effects of environmental variations on frequency. The design is implemented in VHDL and synthesized using Artisan standard-cells in TSMC's 180 nm CMOS technology. Post-layout timing analysis shows that the proposed free-running period synthesizer (FPRS) can operate at a frequency of up to 175 MHz. The architecture was also validated with an implementation on a Xilinx's Spartan 3 FPGA that works at 80 MHz. In both implementations, the worst case peak to peak jitter of the output clock is equal to one period of the free-running oscillator.
{"title":"Precise free-running period synthesizer (FRPS) with process and temperature compensation","authors":"B. Pontikakis, F. Boyer, Y. Savaria, H. Bui","doi":"10.1109/MWSCAS.2007.4488754","DOIUrl":"https://doi.org/10.1109/MWSCAS.2007.4488754","url":null,"abstract":"This paper proposes an all-digital, automated, clock generator based on a free-running oscillator that can generate arbitrarily precise frequencies. The entire system can be implemented using standard cells and even has a compensation system to mitigate the effects of environmental variations on frequency. The design is implemented in VHDL and synthesized using Artisan standard-cells in TSMC's 180 nm CMOS technology. Post-layout timing analysis shows that the proposed free-running period synthesizer (FPRS) can operate at a frequency of up to 175 MHz. The architecture was also validated with an implementation on a Xilinx's Spartan 3 FPGA that works at 80 MHz. In both implementations, the worst case peak to peak jitter of the output clock is equal to one period of the free-running oscillator.","PeriodicalId":256061,"journal":{"name":"2007 50th Midwest Symposium on Circuits and Systems","volume":"303 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116219051","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-08-01DOI: 10.1109/MWSCAS.2007.4488792
J. Ravindra, M. Srinivas
In high speed digital integrated circuits, inductive- coupling effects in interconnects can be significant and should be included for accurate delay-noise analysis. In this paper, an analytical framework to model delay and slew metrics in coupled RLC interconnects is presented. The proposed models are based on difference model approach which involves the dynamic part of system transfer function. The models are generic in nature and can be applied to symmetric driver-and-line configurations for aggressor and victim wires. The model is compared against SPICE simulations and is shown to capture delay and slew accurately. Over a large set of random test cases, the average error in delay and slew estimation is approximately 1.8% and 3.2% respectively. A key feature of the new model is that its derivation and form enables an insight into the inductively coupled noise-waveform. Due to its simplicity and physical nature, the proposed model can be applied to asymmetric transmission lines. The obtained results indicate that common (capacitive) noise-avoidance techniques can behave quite differently when capacitive and inductive coupling are considered together.
{"title":"Delay and slew analysis of VLSI interconnects using difference model approach","authors":"J. Ravindra, M. Srinivas","doi":"10.1109/MWSCAS.2007.4488792","DOIUrl":"https://doi.org/10.1109/MWSCAS.2007.4488792","url":null,"abstract":"In high speed digital integrated circuits, inductive- coupling effects in interconnects can be significant and should be included for accurate delay-noise analysis. In this paper, an analytical framework to model delay and slew metrics in coupled RLC interconnects is presented. The proposed models are based on difference model approach which involves the dynamic part of system transfer function. The models are generic in nature and can be applied to symmetric driver-and-line configurations for aggressor and victim wires. The model is compared against SPICE simulations and is shown to capture delay and slew accurately. Over a large set of random test cases, the average error in delay and slew estimation is approximately 1.8% and 3.2% respectively. A key feature of the new model is that its derivation and form enables an insight into the inductively coupled noise-waveform. Due to its simplicity and physical nature, the proposed model can be applied to asymmetric transmission lines. The obtained results indicate that common (capacitive) noise-avoidance techniques can behave quite differently when capacitive and inductive coupling are considered together.","PeriodicalId":256061,"journal":{"name":"2007 50th Midwest Symposium on Circuits and Systems","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116176637","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-08-01DOI: 10.1109/MWSCAS.2007.4488757
Rong Luo, Peng Sun
In this paper, we present an advanced placement which aims at both flattening the temperature and decreasing the area in SoC floorplanning. The placement process is ingeniously converted into a quasi TSP problem and is solved by ant colony optimization (ACO) algorithm. Compared to traditional algorithms based on O-tree and B*-tree optimization, our results show great improvement in calculating speed while promising satisfying accuracy.
{"title":"An advanced placement method for SoC floorplanning based on ACO algorithm","authors":"Rong Luo, Peng Sun","doi":"10.1109/MWSCAS.2007.4488757","DOIUrl":"https://doi.org/10.1109/MWSCAS.2007.4488757","url":null,"abstract":"In this paper, we present an advanced placement which aims at both flattening the temperature and decreasing the area in SoC floorplanning. The placement process is ingeniously converted into a quasi TSP problem and is solved by ant colony optimization (ACO) algorithm. Compared to traditional algorithms based on O-tree and B*-tree optimization, our results show great improvement in calculating speed while promising satisfying accuracy.","PeriodicalId":256061,"journal":{"name":"2007 50th Midwest Symposium on Circuits and Systems","volume":"75 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116437035","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-08-01DOI: 10.1109/MWSCAS.2007.4488543
V. Frick, J. Pascal, L. Hébrard, J. Blonde, J. Felblinger
This paper reports on a standard CMOS integrated system for monitoring the magnetic fields in MRI environments. The sub-micron technology circuit features three horizontal hall devices and their associated electronics that form instrumental chains. Two of them are dedicated to millitesla range magnetic pulse and gradient measurement whereas the third one is for monitoring the strong static field of the MRI setup. The 0.35 mum technology prototype performs 130 muT gradient measurement with 20 muT resolution and can also map static fields as high as 1.5T.
{"title":"CMOS integrated system for magnetic field monitoring and gradient measurement in MRI environment","authors":"V. Frick, J. Pascal, L. Hébrard, J. Blonde, J. Felblinger","doi":"10.1109/MWSCAS.2007.4488543","DOIUrl":"https://doi.org/10.1109/MWSCAS.2007.4488543","url":null,"abstract":"This paper reports on a standard CMOS integrated system for monitoring the magnetic fields in MRI environments. The sub-micron technology circuit features three horizontal hall devices and their associated electronics that form instrumental chains. Two of them are dedicated to millitesla range magnetic pulse and gradient measurement whereas the third one is for monitoring the strong static field of the MRI setup. The 0.35 mum technology prototype performs 130 muT gradient measurement with 20 muT resolution and can also map static fields as high as 1.5T.","PeriodicalId":256061,"journal":{"name":"2007 50th Midwest Symposium on Circuits and Systems","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117102835","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-08-01DOI: 10.1109/MWSCAS.2007.4488666
J. Colomer, P. Miribel, A. Saiz-Vela, J. Brufau, J. Maa, M. Puig-Vidal, J. Samitier
Nowadays, there is an important interest in smart wireless sensors. A key point in their development is the way they are powered. Piezoelectric energy conversion can be used for such purpose. In this paper, a novel architecture that combines in a single integrated circuit the power conditioning circuitry needed to use piezoelectric energy conversion and an embedded temperature sensor is presented.
{"title":"SiP power management unit with embedded temperature sensor powered by piezoelectric vibration energy harvesting","authors":"J. Colomer, P. Miribel, A. Saiz-Vela, J. Brufau, J. Maa, M. Puig-Vidal, J. Samitier","doi":"10.1109/MWSCAS.2007.4488666","DOIUrl":"https://doi.org/10.1109/MWSCAS.2007.4488666","url":null,"abstract":"Nowadays, there is an important interest in smart wireless sensors. A key point in their development is the way they are powered. Piezoelectric energy conversion can be used for such purpose. In this paper, a novel architecture that combines in a single integrated circuit the power conditioning circuitry needed to use piezoelectric energy conversion and an embedded temperature sensor is presented.","PeriodicalId":256061,"journal":{"name":"2007 50th Midwest Symposium on Circuits and Systems","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116247630","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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