Pub Date : 2007-08-01DOI: 10.1109/MWSCAS.2007.4488745
S.I. Ahmed, T. Kwasniewski
Clock and data recovery (CDR) Circuits are being increasingly marketed as intellectual property (IP) blocks for complex system-on-chip (SoC) and network-on-chip (NoC) products. As part of the mixed-signal design flow, an early estimation of system-level performance requires efficient simulation techniques and models to establish design requirements. In this paper we present some of the challenges associated with and efficient methods to estimate the jitter tolerance of an all-digital data recovery circuit. The key insight is that since it is the maximum slope of the phase-modulating sinusoid that causes transient bit errors, an arbitrary waveform with the same maximum slope can be used for a shorter simulation study. We also present known limitations associated with the general usage of this newly proposed method.
{"title":"Efficient simulation of jitter tolerance for all-digital data recovery circuits","authors":"S.I. Ahmed, T. Kwasniewski","doi":"10.1109/MWSCAS.2007.4488745","DOIUrl":"https://doi.org/10.1109/MWSCAS.2007.4488745","url":null,"abstract":"Clock and data recovery (CDR) Circuits are being increasingly marketed as intellectual property (IP) blocks for complex system-on-chip (SoC) and network-on-chip (NoC) products. As part of the mixed-signal design flow, an early estimation of system-level performance requires efficient simulation techniques and models to establish design requirements. In this paper we present some of the challenges associated with and efficient methods to estimate the jitter tolerance of an all-digital data recovery circuit. The key insight is that since it is the maximum slope of the phase-modulating sinusoid that causes transient bit errors, an arbitrary waveform with the same maximum slope can be used for a shorter simulation study. We also present known limitations associated with the general usage of this newly proposed method.","PeriodicalId":256061,"journal":{"name":"2007 50th Midwest Symposium on Circuits and Systems","volume":"317 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114064266","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-08-01DOI: 10.1109/MWSCAS.2007.4488543
V. Frick, J. Pascal, L. Hébrard, J. Blonde, J. Felblinger
This paper reports on a standard CMOS integrated system for monitoring the magnetic fields in MRI environments. The sub-micron technology circuit features three horizontal hall devices and their associated electronics that form instrumental chains. Two of them are dedicated to millitesla range magnetic pulse and gradient measurement whereas the third one is for monitoring the strong static field of the MRI setup. The 0.35 mum technology prototype performs 130 muT gradient measurement with 20 muT resolution and can also map static fields as high as 1.5T.
{"title":"CMOS integrated system for magnetic field monitoring and gradient measurement in MRI environment","authors":"V. Frick, J. Pascal, L. Hébrard, J. Blonde, J. Felblinger","doi":"10.1109/MWSCAS.2007.4488543","DOIUrl":"https://doi.org/10.1109/MWSCAS.2007.4488543","url":null,"abstract":"This paper reports on a standard CMOS integrated system for monitoring the magnetic fields in MRI environments. The sub-micron technology circuit features three horizontal hall devices and their associated electronics that form instrumental chains. Two of them are dedicated to millitesla range magnetic pulse and gradient measurement whereas the third one is for monitoring the strong static field of the MRI setup. The 0.35 mum technology prototype performs 130 muT gradient measurement with 20 muT resolution and can also map static fields as high as 1.5T.","PeriodicalId":256061,"journal":{"name":"2007 50th Midwest Symposium on Circuits and Systems","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117102835","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-08-01DOI: 10.1109/MWSCAS.2007.4488796
Hua Tang, T. Kwon, Yi Zheng, Hairong Chang
It is well known that vehicle tracking processes are very computationally intensive. Traditionally, vehicle tracking algorithms have been implemented using software approaches. The goal of this paper is to investigate the feasibility of developing a hardware-based tracking system. We propose a tracking algorithm with vehicle motion detection based on block matching algorithm, which is well suited to customized hardware implementation. The proposed tracking algorithm is first simulated in MATLAB and the CMOS circuit design was simulated in Cadence. When tested on traffic images captured from an intersection, it is found that vehicle movements can be accurately identified in spite of some noisy motion. Also, the estimated computational time for the hardware based tracking system is much reduced compared to traditional software-based tracking system.
{"title":"Designing CMOS hardware processor for vehicle tracking","authors":"Hua Tang, T. Kwon, Yi Zheng, Hairong Chang","doi":"10.1109/MWSCAS.2007.4488796","DOIUrl":"https://doi.org/10.1109/MWSCAS.2007.4488796","url":null,"abstract":"It is well known that vehicle tracking processes are very computationally intensive. Traditionally, vehicle tracking algorithms have been implemented using software approaches. The goal of this paper is to investigate the feasibility of developing a hardware-based tracking system. We propose a tracking algorithm with vehicle motion detection based on block matching algorithm, which is well suited to customized hardware implementation. The proposed tracking algorithm is first simulated in MATLAB and the CMOS circuit design was simulated in Cadence. When tested on traffic images captured from an intersection, it is found that vehicle movements can be accurately identified in spite of some noisy motion. Also, the estimated computational time for the hardware based tracking system is much reduced compared to traditional software-based tracking system.","PeriodicalId":256061,"journal":{"name":"2007 50th Midwest Symposium on Circuits and Systems","volume":"1 3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123178010","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-08-01DOI: 10.1109/MWSCAS.2007.4488684
Yanjie Wang, S. Kilambi, K. Iniewski, V. Gaudet
A fully integrated CMOS impulse-based transmitter with on-off keying (OOK) modulation scheme, for ultra- wideband (UWB) impulse radio (IR) system has been designed in a standard TSMC 0.18 mum CMOS technology. A novel Gaussian mono-pulse generator using simple and robust design method has been presented. On-chip pulse shaping using LC Band-Pass Filter (BPF) is developed to meet the Federal Communications Commission (FCC) spectrum requirement. The proposed UWB transmitter has been laid out and post-layout simulation results are analyzed. A Gaussian mono-pulse of less than 100 ps falling/rising time with a 130 mVpp amplitude was observed, at a clock frequency of 500 MHz. The total power dissipation of the transmitter is 1.2 mW with only 316 muW consumed by impulse generator. The output of the transmitter is 48 mVpp under a 1.2 V power supply.
{"title":"A fully integrated CMOS transmitter design for IR-UWB communication systems","authors":"Yanjie Wang, S. Kilambi, K. Iniewski, V. Gaudet","doi":"10.1109/MWSCAS.2007.4488684","DOIUrl":"https://doi.org/10.1109/MWSCAS.2007.4488684","url":null,"abstract":"A fully integrated CMOS impulse-based transmitter with on-off keying (OOK) modulation scheme, for ultra- wideband (UWB) impulse radio (IR) system has been designed in a standard TSMC 0.18 mum CMOS technology. A novel Gaussian mono-pulse generator using simple and robust design method has been presented. On-chip pulse shaping using LC Band-Pass Filter (BPF) is developed to meet the Federal Communications Commission (FCC) spectrum requirement. The proposed UWB transmitter has been laid out and post-layout simulation results are analyzed. A Gaussian mono-pulse of less than 100 ps falling/rising time with a 130 mVpp amplitude was observed, at a clock frequency of 500 MHz. The total power dissipation of the transmitter is 1.2 mW with only 316 muW consumed by impulse generator. The output of the transmitter is 48 mVpp under a 1.2 V power supply.","PeriodicalId":256061,"journal":{"name":"2007 50th Midwest Symposium on Circuits and Systems","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124906266","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-08-01DOI: 10.1109/MWSCAS.2007.4488740
Heather A. Wake, Martin A. Brooke
Electrophoresis is a valuable technique for the separation and analysis of chemical and biological specimens. Typically, an electric field is established between two electrodes that induces charged particles to move and separate. Instead of using only one electrode at each end of the separation area, this paper presents a very small, low voltage system that utilizes electrodes beneath the entire separation area, enabling better control of high electric fields using very small voltages over small areas. By employing multiple electrodes, strong electric fields can be established using very low voltages (less than 5 V) over small distances. The electrodes are also used to sense sample locations and concentrations using amperometric detection, and integrated electronics allow precise control over the fields. The system presented here includes 100 individually addressable electrodes and their corresponding circuitry on a 2 mm by 2 mm chip and is designed using the AMI 1.5 mum CMOS process available through MOSIS.
电泳是一种有价值的分离和分析化学和生物样品的技术。通常，在两个电极之间建立电场，诱导带电粒子移动和分离。本文提出了一种非常小的低压系统，该系统利用整个分离区域下方的电极，而不是在分离区域的每一端只使用一个电极，从而可以在小区域上使用非常小的电压来更好地控制高电场。通过使用多个电极，可以在很小的距离上使用非常低的电压(小于5 V)建立强电场。电极也用于感应样品的位置和浓度使用安培检测，集成电子允许精确控制领域。该系统包括100个可单独寻址的电极及其在2mm × 2mm芯片上的相应电路，并采用MOSIS提供的AMI 1.5 μ m CMOS工艺设计。
{"title":"Low voltage electrophoresis on a CMOS chip","authors":"Heather A. Wake, Martin A. Brooke","doi":"10.1109/MWSCAS.2007.4488740","DOIUrl":"https://doi.org/10.1109/MWSCAS.2007.4488740","url":null,"abstract":"Electrophoresis is a valuable technique for the separation and analysis of chemical and biological specimens. Typically, an electric field is established between two electrodes that induces charged particles to move and separate. Instead of using only one electrode at each end of the separation area, this paper presents a very small, low voltage system that utilizes electrodes beneath the entire separation area, enabling better control of high electric fields using very small voltages over small areas. By employing multiple electrodes, strong electric fields can be established using very low voltages (less than 5 V) over small distances. The electrodes are also used to sense sample locations and concentrations using amperometric detection, and integrated electronics allow precise control over the fields. The system presented here includes 100 individually addressable electrodes and their corresponding circuitry on a 2 mm by 2 mm chip and is designed using the AMI 1.5 mum CMOS process available through MOSIS.","PeriodicalId":256061,"journal":{"name":"2007 50th Midwest Symposium on Circuits and Systems","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125071421","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-08-01DOI: 10.1109/MWSCAS.2007.4488832
K. Boyle, P. Mercier, N. Sadeghi, V. Gaudet, C. Schlegel, C. Winstead, M. Kashyap
The implementation of a 64-symbol analog, current-mode FFT processor is discussed. An analog FFT would be suitable for combination with an analog decoder in the making of an all-analog communication front-end for OFDM systems. Here the FFT is implemented using a butterfly diagram as the system block diagram; each node in the diagram is implemented using analog circuits. Implementation details, including consideration of the effect of approximation errors and the implementation of a test chip, are discussed.
{"title":"Design and implementation of an all-analog fast-fourier transform processor","authors":"K. Boyle, P. Mercier, N. Sadeghi, V. Gaudet, C. Schlegel, C. Winstead, M. Kashyap","doi":"10.1109/MWSCAS.2007.4488832","DOIUrl":"https://doi.org/10.1109/MWSCAS.2007.4488832","url":null,"abstract":"The implementation of a 64-symbol analog, current-mode FFT processor is discussed. An analog FFT would be suitable for combination with an analog decoder in the making of an all-analog communication front-end for OFDM systems. Here the FFT is implemented using a butterfly diagram as the system block diagram; each node in the diagram is implemented using analog circuits. Implementation details, including consideration of the effect of approximation errors and the implementation of a test chip, are discussed.","PeriodicalId":256061,"journal":{"name":"2007 50th Midwest Symposium on Circuits and Systems","volume":"91 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122964648","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-08-01DOI: 10.1109/MWSCAS.2007.4488633
S. Vatti, C. Papavassiliou
A novel bias and tuning scheme for capacitively cross-coupled inductance-capacitance (LC) oscillators is presented. This scheme allows more flexibility in defining the operating point of the cross-coupled transistors, together with wide frequency tunability. A capacitively coupled LC oscillator at 5 GHz has been designed in CMOS UMC 0.18 mum technology. The bias network is realized with an all-transistor voltage reference. The oscillator is tunable in the 5 GHz-9 GHz frequency range. Phase noise performance is maintained over the entire frequency range, with -58 dBc/Hz at 100 kHz offset and -116 dBc/Hz at 1 MHz.
{"title":"A capacitively-coupled 5GHz CMOS LC oscillator with bias tuning capability","authors":"S. Vatti, C. Papavassiliou","doi":"10.1109/MWSCAS.2007.4488633","DOIUrl":"https://doi.org/10.1109/MWSCAS.2007.4488633","url":null,"abstract":"A novel bias and tuning scheme for capacitively cross-coupled inductance-capacitance (LC) oscillators is presented. This scheme allows more flexibility in defining the operating point of the cross-coupled transistors, together with wide frequency tunability. A capacitively coupled LC oscillator at 5 GHz has been designed in CMOS UMC 0.18 mum technology. The bias network is realized with an all-transistor voltage reference. The oscillator is tunable in the 5 GHz-9 GHz frequency range. Phase noise performance is maintained over the entire frequency range, with -58 dBc/Hz at 100 kHz offset and -116 dBc/Hz at 1 MHz.","PeriodicalId":256061,"journal":{"name":"2007 50th Midwest Symposium on Circuits and Systems","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123721975","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A compact size and high efficient single-inductor dual-output (SIDO) DC-DC converter is proposed. Generally speaking, it is important to implement DC-DC converters with minimized components and small footprint area. However, large external compensated resistors and capacitors are required to stabilize DC-DC converters. The proposed SIDO DC-DC converter not only provides dual output sources but also has minimized cross regulation without using any external compensated components. Importantly, our proposed mode-switch technique corrects the mistakes in the previous design [1], which didn't mention the unstable condition. Besides, owing to dynamically adjusting DC current level like CCM operation, the SIDO DC-DC converter achieves high conversion efficiency. Experimental results show a high efficiency from 85% at light load condition to 94% at heavy load condition.
{"title":"Single-inductor dual-output (SIDO) DC-DC converters for minimized cross regulation and high efficiency in SoC supplying systems","authors":"Ming-Hsin Huang, Hong-Wei Huang, Jiun-Yan Peng, Tzung-Ling Tsai, Min-Chin Lee, Ching-Sung Wang, Ke-Horng Chen","doi":"10.1109/MWSCAS.2007.4488644","DOIUrl":"https://doi.org/10.1109/MWSCAS.2007.4488644","url":null,"abstract":"A compact size and high efficient single-inductor dual-output (SIDO) DC-DC converter is proposed. Generally speaking, it is important to implement DC-DC converters with minimized components and small footprint area. However, large external compensated resistors and capacitors are required to stabilize DC-DC converters. The proposed SIDO DC-DC converter not only provides dual output sources but also has minimized cross regulation without using any external compensated components. Importantly, our proposed mode-switch technique corrects the mistakes in the previous design [1], which didn't mention the unstable condition. Besides, owing to dynamically adjusting DC current level like CCM operation, the SIDO DC-DC converter achieves high conversion efficiency. Experimental results show a high efficiency from 85% at light load condition to 94% at heavy load condition.","PeriodicalId":256061,"journal":{"name":"2007 50th Midwest Symposium on Circuits and Systems","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122683369","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-08-01DOI: 10.1109/MWSCAS.2007.4488676
K. Waheed, S. Ba
The digital RF processor (DRP) based EDGE small- signal polar transmitter utilizes a highly non-linear digitally controlled pre-power amplifier (DPA) for on-chip combination of the amplitude and phase modulation paths. This complex signal drives an off-chip power amplifier (PA), optimized for power added efficiency (PAE), causing further degradation in the linearity of transmission. We propose an effective adaptive predistortion scheme that takes advantage of the time division duplex (TDD) nature of the EDGE modulation and uses the on-chip receiver as a feedback path during transmission. The proposed linearization technique features automatic calibration of nominal AM-AM and AM-PM look-up tables (LUT). The temporal variations primarily caused by temperature, aging, impedance and voltage changes are compensated by an incremental predistortion function that is periodically adapted using a low complexity iterative algorithm. The proposed predistortion technique improves the EDGE TX error vector magnitude (EVM) contribution from -20 dB (or 10%) in absence of predistortion to -67 dB (0.04%) while the adjacent channel power ratio (ACPR) at 400 kHz offset improves from -46 dBc to -69 dBc.
{"title":"Adaptive digital linearization of a DRP based edge transmitter for cellular handsets","authors":"K. Waheed, S. Ba","doi":"10.1109/MWSCAS.2007.4488676","DOIUrl":"https://doi.org/10.1109/MWSCAS.2007.4488676","url":null,"abstract":"The digital RF processor (DRP) based EDGE small- signal polar transmitter utilizes a highly non-linear digitally controlled pre-power amplifier (DPA) for on-chip combination of the amplitude and phase modulation paths. This complex signal drives an off-chip power amplifier (PA), optimized for power added efficiency (PAE), causing further degradation in the linearity of transmission. We propose an effective adaptive predistortion scheme that takes advantage of the time division duplex (TDD) nature of the EDGE modulation and uses the on-chip receiver as a feedback path during transmission. The proposed linearization technique features automatic calibration of nominal AM-AM and AM-PM look-up tables (LUT). The temporal variations primarily caused by temperature, aging, impedance and voltage changes are compensated by an incremental predistortion function that is periodically adapted using a low complexity iterative algorithm. The proposed predistortion technique improves the EDGE TX error vector magnitude (EVM) contribution from -20 dB (or 10%) in absence of predistortion to -67 dB (0.04%) while the adjacent channel power ratio (ACPR) at 400 kHz offset improves from -46 dBc to -69 dBc.","PeriodicalId":256061,"journal":{"name":"2007 50th Midwest Symposium on Circuits and Systems","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122931545","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-08-01DOI: 10.1109/MWSCAS.2007.4488724
M. A. Turi, J. Delgado-Frías
Two novel memory decoder designs for reducing energy consumption and delay are presented in this paper. These two decoding schemes are compared to the conventional NOR decoder. Fewer word lines are charged and discharged by the proposed schemes which leads to less energy dissipation. Energy, delay, and area calculations are provided for all three designs under analysis. The two novel decoder schemes range from dissipating 3.9% to 23.6% of the energy dissipated by the conventional decoder. The delays of these designs are 80.8% of the conventional decoder delay. Simulations of the three decoders are performed using a 90 nm CMOS technology.
{"title":"Reducing power in memory decoders by means of selective precharge schemes","authors":"M. A. Turi, J. Delgado-Frías","doi":"10.1109/MWSCAS.2007.4488724","DOIUrl":"https://doi.org/10.1109/MWSCAS.2007.4488724","url":null,"abstract":"Two novel memory decoder designs for reducing energy consumption and delay are presented in this paper. These two decoding schemes are compared to the conventional NOR decoder. Fewer word lines are charged and discharged by the proposed schemes which leads to less energy dissipation. Energy, delay, and area calculations are provided for all three designs under analysis. The two novel decoder schemes range from dissipating 3.9% to 23.6% of the energy dissipated by the conventional decoder. The delays of these designs are 80.8% of the conventional decoder delay. Simulations of the three decoders are performed using a 90 nm CMOS technology.","PeriodicalId":256061,"journal":{"name":"2007 50th Midwest Symposium on Circuits and Systems","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123927526","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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