Pub Date : 2019-02-01DOI: 10.1109/ISSCC.2019.8662393
P. Jain, U. Arslan, M. Sekhar, Blake C. Lin, Liqiong Wei, Tanay Sahu, Juan Alzate-vinasco, Ajay Vangapaty, M. Meterelliyoz, N. Strutt, Albert B. Chen, P. Hentges, Pedro A. Quintero, C. Connor, O. Golonzka, K. Fischer, F. Hamzaoglu
A resistive RAM (ReRAM) macro is developed as a low-cost, magnetic-disturb-immune option for embedded, non-volatile memory for SoCs used in IoT and automotive applications. We demonstrate the smallest ReRAM subarray density of 10.1Mb/mm2 in a 22nm low-power process. The subarray uses nominal-gate FINFET logic devices, with material innovations to allow low-voltage switching without impacting transistor reliability. Prior art features larger bit cell size or array density, and uses 28 or 40nm technology nodes [1]–[4]. The smallest read-sense time ($t_{mathrm {SENSE}},=5$ ns@0.7V) is demonstrated, compared to previous works [2]. An optimized pulse-width (PW) voltage-current write-verify-write (PVC-WVW) sequence helps in mitigating endurance and variability. A flexible and low-area TFR (thin-film resistor) based reference scheme enables optimization of forming, write yield, retention and endurance tradeoffs by skewing different verify and read resistances. A temperature-constant current source and a reference resistance help in the precise control of the forming/set current and the verify/read operations. Compared to area-inefficient bandgap circuits and temperature sensors, the in-situ TFR was used due to its low area, flexibility and seamless integration into the SoC. The memory bank uses a single supply coming from an in-situ charge pump (CP) that is shared across the macro.
{"title":"13.2 A 3.6Mb 10.1Mb/mm2 Embedded Non-Volatile ReRAM Macro in 22nm FinFET Technology with Adaptive Forming/Set/Reset Schemes Yielding Down to 0.5V with Sensing Time of 5ns at 0.7V","authors":"P. Jain, U. Arslan, M. Sekhar, Blake C. Lin, Liqiong Wei, Tanay Sahu, Juan Alzate-vinasco, Ajay Vangapaty, M. Meterelliyoz, N. Strutt, Albert B. Chen, P. Hentges, Pedro A. Quintero, C. Connor, O. Golonzka, K. Fischer, F. Hamzaoglu","doi":"10.1109/ISSCC.2019.8662393","DOIUrl":"https://doi.org/10.1109/ISSCC.2019.8662393","url":null,"abstract":"A resistive RAM (ReRAM) macro is developed as a low-cost, magnetic-disturb-immune option for embedded, non-volatile memory for SoCs used in IoT and automotive applications. We demonstrate the smallest ReRAM subarray density of 10.1Mb/mm2 in a 22nm low-power process. The subarray uses nominal-gate FINFET logic devices, with material innovations to allow low-voltage switching without impacting transistor reliability. Prior art features larger bit cell size or array density, and uses 28 or 40nm technology nodes [1]–[4]. The smallest read-sense time ($t_{mathrm {SENSE}},=5$ ns@0.7V) is demonstrated, compared to previous works [2]. An optimized pulse-width (PW) voltage-current write-verify-write (PVC-WVW) sequence helps in mitigating endurance and variability. A flexible and low-area TFR (thin-film resistor) based reference scheme enables optimization of forming, write yield, retention and endurance tradeoffs by skewing different verify and read resistances. A temperature-constant current source and a reference resistance help in the precise control of the forming/set current and the verify/read operations. Compared to area-inefficient bandgap circuits and temperature sensors, the in-situ TFR was used due to its low area, flexibility and seamless integration into the SoC. The memory bank uses a single supply coming from an in-situ charge pump (CP) that is shared across the macro.","PeriodicalId":265551,"journal":{"name":"2019 IEEE International Solid- State Circuits Conference - (ISSCC)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133070453","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Sophisticated OFDM modulation schemes with high spectrum efficiency and data throughput in modern wireless communication systems often result in a large peak-to-average power ratio (PAPR). Besides, wireless standards like LTE, WLAN, NB-IoT, etc., require wide transmission power range to accommodate various communication environments, and devices often function at low average output power. For better battery lifetime, it is critical to improve the power amplifier (PA) efficiency at deep power back-off (PBO) levels (e.g., 12/18dB or higher). Recently, several digital-style techniques have been employed to enhance PA PBO efficiency, such as dynamic power control [1], Class-G, and Doherty [2–4], as well as multilevel outphasing [5]. Class-G or Doherty techniques usually provide an efficiency peaking at 6dB PBO, and when combined together [2,3] or cascaded [6] they can further enhance the efficiency beyond 6dB PBO by introducing two efficiency peaks at 6/12dB PBOs. However, most of the Class-G Doherty PAs suffer from large area overhead with two power supply paths and glitches due to mode transitions. The dynamic power control or multi-level outphasing PA requires multiple phase modulators and amplitude-level transitions, which cause inherent discontinuities and degrade the linearity. In this work, a switched-transformer digital-PA technique is proposed for wide-range PBO efficiency enhancement. This topology does not require multiple power supplies and does not introduce AM/PM discontinuities. The PA achieves multiple efficiency peaks at 0/6/12/18dB PBOs and wide frequency coverage with a single-transformer footprint and only one supply voltage.
{"title":"4.2 A Broadband Switched-Transformer Digital Power Amplifier for Deep Back-Off Efficiency Enhancement","authors":"Liang Xiong, Tong Li, Yun Yin, Hao Min, N. Yan, Hongtao Xu","doi":"10.1109/ISSCC.2019.8662330","DOIUrl":"https://doi.org/10.1109/ISSCC.2019.8662330","url":null,"abstract":"Sophisticated OFDM modulation schemes with high spectrum efficiency and data throughput in modern wireless communication systems often result in a large peak-to-average power ratio (PAPR). Besides, wireless standards like LTE, WLAN, NB-IoT, etc., require wide transmission power range to accommodate various communication environments, and devices often function at low average output power. For better battery lifetime, it is critical to improve the power amplifier (PA) efficiency at deep power back-off (PBO) levels (e.g., 12/18dB or higher). Recently, several digital-style techniques have been employed to enhance PA PBO efficiency, such as dynamic power control [1], Class-G, and Doherty [2–4], as well as multilevel outphasing [5]. Class-G or Doherty techniques usually provide an efficiency peaking at 6dB PBO, and when combined together [2,3] or cascaded [6] they can further enhance the efficiency beyond 6dB PBO by introducing two efficiency peaks at 6/12dB PBOs. However, most of the Class-G Doherty PAs suffer from large area overhead with two power supply paths and glitches due to mode transitions. The dynamic power control or multi-level outphasing PA requires multiple phase modulators and amplitude-level transitions, which cause inherent discontinuities and degrade the linearity. In this work, a switched-transformer digital-PA technique is proposed for wide-range PBO efficiency enhancement. This topology does not require multiple power supplies and does not introduce AM/PM discontinuities. The PA achieves multiple efficiency peaks at 0/6/12/18dB PBOs and wide frequency coverage with a single-transformer footprint and only one supply voltage.","PeriodicalId":265551,"journal":{"name":"2019 IEEE International Solid- State Circuits Conference - (ISSCC)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125612111","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-02-01DOI: 10.1109/isscc.2019.8662519
Power Management Subcommittee
Power converters are widely used in many emerging applications like 5G communication, high-power wireless transfer, galvanically isolated systems and high-voltage automotive and offline systems. Efficiency, bandwidth, high frequency, low EMI, and high reliability are all key to these highperformance power converters. This session presents recent advances in high-bandwidth supply modulators for 5G systems, high-efficiency wireless power transfer, single-chip isolated power converters with on-chip transformers, and low-EMI high-reliability GaN power converters. Session Chair: Min Chen Analog Devices, Milpitas, CA Associate Chair: Johan Janssens ON Semiconductor, Mechelen, Belgium
电源转换器广泛应用于5G通信、大功率无线传输、电隔离系统、高压汽车和离线系统等许多新兴应用。效率、带宽、高频、低电磁干扰和高可靠性是这些高性能功率变换器的关键。本次会议将介绍用于5G系统的高带宽电源调制器、高效无线电力传输、带片上变压器的单片隔离电源转换器和低emi高可靠性GaN电源转换器的最新进展。副主席:Johan Janssens ON Semiconductor，梅赫伦，比利时
{"title":"ISSCC 2019 Session 15 Overview: Power for 5G, Wireless Power, and GaN Converters","authors":"Power Management Subcommittee","doi":"10.1109/isscc.2019.8662519","DOIUrl":"https://doi.org/10.1109/isscc.2019.8662519","url":null,"abstract":"Power converters are widely used in many emerging applications like 5G communication, high-power wireless transfer, galvanically isolated systems and high-voltage automotive and offline systems. Efficiency, bandwidth, high frequency, low EMI, and high reliability are all key to these highperformance power converters. This session presents recent advances in high-bandwidth supply modulators for 5G systems, high-efficiency wireless power transfer, single-chip isolated power converters with on-chip transformers, and low-EMI high-reliability GaN power converters. Session Chair: Min Chen Analog Devices, Milpitas, CA Associate Chair: Johan Janssens ON Semiconductor, Mechelen, Belgium","PeriodicalId":265551,"journal":{"name":"2019 IEEE International Solid- State Circuits Conference - (ISSCC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115852874","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Embedded nonvolatile memory (NVM) and computing-in-memory (CIM) are significantly reducing the latency (tMAC) and energy consumption (EMAC) of multiply- and-accumulate (MAC) operations in artificial intelligence (AI) edge devices [1, 2]. Previous ReRAM CIM macros demonstrated MAC operations for lb-input, ternary- weighted, 3b-output CNNs [1] or lb-input, 8b-weighted, 1b-output fully-connected networks with limited accuracy [2]. To support higher-accuracy convolution neural network heavy applications NVM-CIM should support multibit inputs/weights and multi-bit output (MAC-OUT) for CNN operations. One way to achieve multibit weights is to use a multi-level ReRAM cell to store the weight. However, as shown in Fig. 24.1.1, multibit ReRAM CIM faces several challenges. (1) a tradeoff between area and speed for multibit input/weight/MAC-OUT MAC operations; (2) sense amplifier’s high input offset, large area, and high parasitic load on the read-path due to large BL currents (IBL) from multibit MAC; (3) limited accuracy due to a small read/sensing margin (ISM) across MAC-OUT or variation in cell resistance (particularly MLC cells). To overcome these challenges, this work proposes, (1) a serial-input non-weighted product (SINWP) structure to optimize the tradeoff between area, tMAC and EMAC, (2) a down-scaling weighted current translator (DSWCT) and positive-negative current- subtractor (PN-ISUB) for short delay, a small offset and a compact read-path area; and (3) a triple-margin small-offset current-mode sense amplifier (TMCSA) to tolerate a small ISM. A fabricated 55nm 1Mb ReRAM-CIM macro is the first ReRAM CIM macro to support CNN operations using multibit input/weight MAC-OUT. This device achieves the shortest CIM-MAC-access time (tAC) among existing ReRAM-CIMs (tMAC=14.6ns with 2b-input, 3b-weight with 4b-MAC-OUT) and the best peak EMAC of 53.17 TOPS/W (in binary mode).
嵌入式非易失性存储器(NVM)和内存计算(CIM)显著降低了人工智能(AI)边缘设备中乘法累加(MAC)操作的延迟(tMAC)和能耗(EMAC)[1,2]。先前的ReRAM CIM宏演示了lb-input, three -weighted, 3b-output cnn[1]或lb-input, 8b-weighted, 1b-output全连接网络的MAC操作，但精度有限[2]。为了支持更高精度的卷积神经网络重型应用，NVM-CIM应该支持CNN操作的多位输入/权重和多位输出(MAC-OUT)。实现多位权重的一种方法是使用多级ReRAM单元来存储权重。然而，如图24.1.1所示，多位ReRAM CIM面临着几个挑战。(1)在多比特输入/权重/MAC- out MAC操作的面积和速度之间进行权衡;(2)多比特MAC产生的大BL电流(IBL)导致感测放大器输入偏置高、面积大、读路寄生负载高;(3)由于MAC-OUT读取/传感裕度(ISM)小或细胞电阻变化(特别是MLC细胞)，准确度有限。为了克服这些挑战，本研究提出:(1)一种串行输入非加权积(SINWP)结构，以优化面积、tMAC和EMAC之间的权衡;(2)一种降尺度加权电流转换器(DSWCT)和正负电流减法器(PN-ISUB)，用于短延迟、小偏移和紧凑的读径面积;以及(3)三裕度小偏置电流模式检测放大器(TMCSA)以容忍小ISM。制造的55nm 1Mb ReRAM-CIM宏是第一个使用多位输入/权重MAC-OUT支持CNN操作的ReRAM-CIM宏。该器件实现了现有reram - cim中最短的CIM-MAC-access time (tAC) (2b-input时tMAC=14.6ns, 3b- mac - out时tMAC= 4b- weight)和最佳峰值EMAC(二进制模式下)，为53.17 TOPS/W。
{"title":"24.1 A 1Mb Multibit ReRAM Computing-In-Memory Macro with 14.6ns Parallel MAC Computing Time for CNN Based AI Edge Processors","authors":"Cheng-Xin Xue, Wei-Hao Chen, Je-Syu Liu, Jia-Fang Li, Wei-Yu Lin, Wei-En Lin, Jing-Hong Wang, Wei-Chen Wei, Ting-Wei Chang, Tung-Cheng Chang, Tsung-Yuan Huang, Hui-Yao Kao, Shih-Ying Wei, Yen-Cheng Chiu, Chun-Ying Lee, C. Lo, Y. King, Chorng-Jung Lin, Ren-Shuo Liu, C. Hsieh, K. Tang, Meng-Fan Chang","doi":"10.1109/ISSCC.2019.8662395","DOIUrl":"https://doi.org/10.1109/ISSCC.2019.8662395","url":null,"abstract":"Embedded nonvolatile memory (NVM) and computing-in-memory (CIM) are significantly reducing the latency (tMAC) and energy consumption (EMAC) of multiply- and-accumulate (MAC) operations in artificial intelligence (AI) edge devices [1, 2]. Previous ReRAM CIM macros demonstrated MAC operations for lb-input, ternary- weighted, 3b-output CNNs [1] or lb-input, 8b-weighted, 1b-output fully-connected networks with limited accuracy [2]. To support higher-accuracy convolution neural network heavy applications NVM-CIM should support multibit inputs/weights and multi-bit output (MAC-OUT) for CNN operations. One way to achieve multibit weights is to use a multi-level ReRAM cell to store the weight. However, as shown in Fig. 24.1.1, multibit ReRAM CIM faces several challenges. (1) a tradeoff between area and speed for multibit input/weight/MAC-OUT MAC operations; (2) sense amplifier’s high input offset, large area, and high parasitic load on the read-path due to large BL currents (IBL) from multibit MAC; (3) limited accuracy due to a small read/sensing margin (ISM) across MAC-OUT or variation in cell resistance (particularly MLC cells). To overcome these challenges, this work proposes, (1) a serial-input non-weighted product (SINWP) structure to optimize the tradeoff between area, tMAC and EMAC, (2) a down-scaling weighted current translator (DSWCT) and positive-negative current- subtractor (PN-ISUB) for short delay, a small offset and a compact read-path area; and (3) a triple-margin small-offset current-mode sense amplifier (TMCSA) to tolerate a small ISM. A fabricated 55nm 1Mb ReRAM-CIM macro is the first ReRAM CIM macro to support CNN operations using multibit input/weight MAC-OUT. This device achieves the shortest CIM-MAC-access time (tAC) among existing ReRAM-CIMs (tMAC=14.6ns with 2b-input, 3b-weight with 4b-MAC-OUT) and the best peak EMAC of 53.17 TOPS/W (in binary mode).","PeriodicalId":265551,"journal":{"name":"2019 IEEE International Solid- State Circuits Conference - (ISSCC)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124868746","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-02-01DOI: 10.1109/ISSCC.2019.8662434
Mohamed I. Ibrahim, Christopher Foy, D. Englund, R. Han
Room-temperature control and detection of the nitrogen vacancy (NV) center in diamond’s spin-state has enabled magnetic sensing with high sensitivity and spatial resolution [1], [2]. However, current NV sensing apparatuses use bulky off-the-shelf components, which greatly increase the system’s scale. In [3], a compact platform, which attaches nanodiamond particles to a CMOS sensor, shrinks this spin-based magnetometer to chip scale; however, the optically detected magnetic resonance (ODMR) curve it generates carries large fluctuation leading to inferior sensitivity. In this paper, we present a CMOS-NV quantum sensor with (i) a highly-scalable microwave-delivering structure and (ii) a Talboteffect-based photonic filter with enhanced green-to-red suppression ratio. The former enables coherent driving of an increased number of NV centers, and the latter reduces the shot noise of the photo-detector caused by the input green laser. In addition, the usage of a bulk diamond also enables vector magnetometry, which allows for the tracking of magnetic objects and navigation. The prototype sensor provides a measured vector-field sensitivity of 245nT/Hz $^{1/2}$.
{"title":"29.2 A Scalable Quantum Magnetometer in 65nm CMOS with Vector-Field Detection Capability","authors":"Mohamed I. Ibrahim, Christopher Foy, D. Englund, R. Han","doi":"10.1109/ISSCC.2019.8662434","DOIUrl":"https://doi.org/10.1109/ISSCC.2019.8662434","url":null,"abstract":"Room-temperature control and detection of the nitrogen vacancy (NV) center in diamond’s spin-state has enabled magnetic sensing with high sensitivity and spatial resolution [1], [2]. However, current NV sensing apparatuses use bulky off-the-shelf components, which greatly increase the system’s scale. In [3], a compact platform, which attaches nanodiamond particles to a CMOS sensor, shrinks this spin-based magnetometer to chip scale; however, the optically detected magnetic resonance (ODMR) curve it generates carries large fluctuation leading to inferior sensitivity. In this paper, we present a CMOS-NV quantum sensor with (i) a highly-scalable microwave-delivering structure and (ii) a Talboteffect-based photonic filter with enhanced green-to-red suppression ratio. The former enables coherent driving of an increased number of NV centers, and the latter reduces the shot noise of the photo-detector caused by the input green laser. In addition, the usage of a bulk diamond also enables vector magnetometry, which allows for the tracking of magnetic objects and navigation. The prototype sensor provides a measured vector-field sensitivity of 245nT/Hz $^{1/2}$.","PeriodicalId":265551,"journal":{"name":"2019 IEEE International Solid- State Circuits Conference - (ISSCC)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131800370","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-02-01DOI: 10.1109/ISSCC.2019.8662529
Liang Qi, Ankesh Jain, Dongyang Jiang, Sai-Weng Sin, R. Martins, M. Ortmanns
The demands for wider cellular bandwidth (BW) drive the development of continuous time (CT) ΔΣ modulators (DSMs). Oversampling ratio (OSR) is generally restricted due to high signal BW. To obtain an adequate resolution while maintaining good power efficiency, CT DSMs generally need to achieve an aggressive noise shaping and employ a multibit quantizer (QTZ) [1]–[3]. Though multibit operation requires a highly linear feedback (FB) DAC, dictating sophisticated linearization techniques [1]–[3]. Multi-stage noise-shaping (MASH) topologies can be employed to increase the order and they can apply multibit quantization only in the latter stages, where linearity requirements are highly relaxed. However, MASH DSMs suffer from quantization noise (ON) leakage due to the mismatch between analog and digital filters.
{"title":"20.5 A 76.6dB-SNDR 50MHz-BW 29.2mW Noise-Coupling-Assisted CT Sturdy MASH ΔΣ Modulator with 1.5b/4b Quantizers in 28nm CMOS","authors":"Liang Qi, Ankesh Jain, Dongyang Jiang, Sai-Weng Sin, R. Martins, M. Ortmanns","doi":"10.1109/ISSCC.2019.8662529","DOIUrl":"https://doi.org/10.1109/ISSCC.2019.8662529","url":null,"abstract":"The demands for wider cellular bandwidth (BW) drive the development of continuous time (CT) ΔΣ modulators (DSMs). Oversampling ratio (OSR) is generally restricted due to high signal BW. To obtain an adequate resolution while maintaining good power efficiency, CT DSMs generally need to achieve an aggressive noise shaping and employ a multibit quantizer (QTZ) [1]–[3]. Though multibit operation requires a highly linear feedback (FB) DAC, dictating sophisticated linearization techniques [1]–[3]. Multi-stage noise-shaping (MASH) topologies can be employed to increase the order and they can apply multibit quantization only in the latter stages, where linearity requirements are highly relaxed. However, MASH DSMs suffer from quantization noise (ON) leakage due to the mismatch between analog and digital filters.","PeriodicalId":265551,"journal":{"name":"2019 IEEE International Solid- State Circuits Conference - (ISSCC)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133519324","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-02-01DOI: 10.1109/ISSCC.2019.8662531
Jihee Lee, Kyoung-Rog Lee, B. Eovino, J. Park, Liwei Lin, H. Yoo, Jerald Yoo
Intracardiac echocardiography (ICE) is an ultrasound sonogram that visualizes the anatomical structure of the heart in real time, with a mm-scale catheter inserted through the intracardiac vessels, and guides surgical intervention for atrial septal defect (ASD) closure. To achieve high-quality medical imaging, an ICE system must meet stringent power consumption requirements with low-noise operation. Since an ASIC and ultrasound transducers are tightly bonded through flip-chip or direct integration, an ultrasound unit TRX channel must be pitch-matched to each transducer channel [1], [2]. A piezoelectric Micro-machined Ultrasound Transducer (pMUT) is a suitable ultrasound transducer for implantable sensor applications, since it does not need high $(sim 200mathrm {V})$ bias that is a must in capacitive MUTs (cMUT) [3]. However, pMUT devices suffer from process variation, which leads to low image quality, and to date, no work addresses this issue for both TX/RX in real time. To meet all these requirements at once, we present a $6 times 6$ TRX pitch-matched pMUT ASIC with a standard CMOS-compatible 13.2V HV pulser, on-chip per-pixel calibration scheme, and a Dynamic Bit-Shared (DBS) ADC for portable ICE applications.
{"title":"11.1 A 5.37mW/Channel Pitch-Matched Ultrasound ASIC with Dynamic-Bit-Shared SAR ADC and 13.2V Charge-Recycling TX in Standard CMOS for Intracardiac Echocardiography","authors":"Jihee Lee, Kyoung-Rog Lee, B. Eovino, J. Park, Liwei Lin, H. Yoo, Jerald Yoo","doi":"10.1109/ISSCC.2019.8662531","DOIUrl":"https://doi.org/10.1109/ISSCC.2019.8662531","url":null,"abstract":"Intracardiac echocardiography (ICE) is an ultrasound sonogram that visualizes the anatomical structure of the heart in real time, with a mm-scale catheter inserted through the intracardiac vessels, and guides surgical intervention for atrial septal defect (ASD) closure. To achieve high-quality medical imaging, an ICE system must meet stringent power consumption requirements with low-noise operation. Since an ASIC and ultrasound transducers are tightly bonded through flip-chip or direct integration, an ultrasound unit TRX channel must be pitch-matched to each transducer channel [1], [2]. A piezoelectric Micro-machined Ultrasound Transducer (pMUT) is a suitable ultrasound transducer for implantable sensor applications, since it does not need high $(sim 200mathrm {V})$ bias that is a must in capacitive MUTs (cMUT) [3]. However, pMUT devices suffer from process variation, which leads to low image quality, and to date, no work addresses this issue for both TX/RX in real time. To meet all these requirements at once, we present a $6 times 6$ TRX pitch-matched pMUT ASIC with a standard CMOS-compatible 13.2V HV pulser, on-chip per-pixel calibration scheme, and a Dynamic Bit-Shared (DBS) ADC for portable ICE applications.","PeriodicalId":265551,"journal":{"name":"2019 IEEE International Solid- State Circuits Conference - (ISSCC)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116066513","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-02-01DOI: 10.1109/ISSCC.2019.8662520
M. Konijnenburg, Roland Van Wegberg, Shuang Song, Hyunsoo Ha, W. Sijbers, Jiawei Xu, S. Stanzione, C. V. Liempd, Dwaipayan Biswas, Arjan Breeschoten, P. Vis, C. Hoof, N. V. Helleputte
Continuous vital-sign monitoring is of paramount importance in remote heath monitoring or rehabilitation environments for chronic diseases. Medical-grade wireless and wearable bio-sensor systems that can be used at home offer a much more attractive solution than hospital-based monitoring systems. We report an all-in-one battery-powered SoC designed for low-cost single-use health patches (Fig. 22.1.1), allowing continuous monitoring in a home setting to improve patient comfort and reduce cost of care by, e.g., reducing hospital stays. In addition to medical-grade signal quality, low power consumption is key in such a health patch system, to enable a comfortable form factor with miniature battery size and prolong the operational lifetime to at least several weeks.
{"title":"22.1 A 769μW Battery-Powered Single-Chip SoC With BLE for Multi-Modal Vital Sign Health Patches","authors":"M. Konijnenburg, Roland Van Wegberg, Shuang Song, Hyunsoo Ha, W. Sijbers, Jiawei Xu, S. Stanzione, C. V. Liempd, Dwaipayan Biswas, Arjan Breeschoten, P. Vis, C. Hoof, N. V. Helleputte","doi":"10.1109/ISSCC.2019.8662520","DOIUrl":"https://doi.org/10.1109/ISSCC.2019.8662520","url":null,"abstract":"Continuous vital-sign monitoring is of paramount importance in remote heath monitoring or rehabilitation environments for chronic diseases. Medical-grade wireless and wearable bio-sensor systems that can be used at home offer a much more attractive solution than hospital-based monitoring systems. We report an all-in-one battery-powered SoC designed for low-cost single-use health patches (Fig. 22.1.1), allowing continuous monitoring in a home setting to improve patient comfort and reduce cost of care by, e.g., reducing hospital stays. In addition to medical-grade signal quality, low power consumption is key in such a health patch system, to enable a comfortable form factor with miniature battery size and prolong the operational lifetime to at least several weeks.","PeriodicalId":265551,"journal":{"name":"2019 IEEE International Solid- State Circuits Conference - (ISSCC)","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117055685","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：