Pub Date : 2019-03-06DOI: 10.1109/ISSCC.2019.8662388
Injun Park, Chanmin Park, Jimin Cheon, Youngcheol Chae
The demand for high-frame-rate CMOS image sensors is steadily increasing. Column-parallel single-slope (SS) ADCs are widely used in CMOS image sensors, because they can be implemented with small area, low noise, and high energy efficiency. To achieve high frame rate and low noise simultaneously, several techniques using SS ADCs, such as parallel multiple sampling [1], [2], dual-gain slopes [3], and dual-gain amplifiers [4], have been investigated. However, since the clock frequency of the SS ADC is already in the GHz range, it is very challenging to maintain energy efficiency as the frame rate increases further.
{"title":"5.4 A 76mW 500fps VGA CMOS Image Sensor with Time-Stretched Single-Slope ADCs Achieving 1.95e- Random Noise","authors":"Injun Park, Chanmin Park, Jimin Cheon, Youngcheol Chae","doi":"10.1109/ISSCC.2019.8662388","DOIUrl":"https://doi.org/10.1109/ISSCC.2019.8662388","url":null,"abstract":"The demand for high-frame-rate CMOS image sensors is steadily increasing. Column-parallel single-slope (SS) ADCs are widely used in CMOS image sensors, because they can be implemented with small area, low noise, and high energy efficiency. To achieve high frame rate and low noise simultaneously, several techniques using SS ADCs, such as parallel multiple sampling [1], [2], dual-gain slopes [3], and dual-gain amplifiers [4], have been investigated. However, since the clock frequency of the SS ADC is already in the GHz range, it is very challenging to maintain energy efficiency as the frame rate increases further.","PeriodicalId":265551,"journal":{"name":"2019 IEEE International Solid- State Circuits Conference - (ISSCC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128497496","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-03-06DOI: 10.1109/ISSCC.2019.8662414
Miao Meng, Ahmed Ibrahim, T. Xue, H. Yeo, Dixiong Wang, S. Roundy, S. Trolier-McKinstry, M. Kiani
The past few years have witnessed a growing demand for self-powered wearables that can enable vigilant health monitoring, with 24/7 operation. Energy harvesting from human-body motion is attractive for wearables; however, conventional unidirectional single-cantilever-beam piezoelectric energy harvesters (PEHs) [1]–[4] suffer from several body-motion harvesting challenges: such as multi-axial motion, irregular frequencies, and unpredictable amplitudes with frequent low-power levels [5]. To address these challenges, an eccentric rotor-based inertial PEH has been developed, which utilizes multiple magnetically plucked flexible thin-film $(60 mu mathrm {m})$ PZT-nickel-PZT beams to significantly increase the harvested energy within a small volume [5]; compared to bulk-PZT beams that are more feasible in direct-force-driven PEHs. The wrist-worn multi-beam PEH, shown in Fig. 27.4.1, converts multi-axial body motion into AC voltages with different phases and decaying amplitudes (up to several volts) within the frequency range of 90–160Hz for each beam.
过去几年，人们对自供电可穿戴设备的需求不断增长，这些设备可以实现全天候的健康监测。从人体运动中收集能量对可穿戴设备很有吸引力;然而，传统的单向单悬臂梁压电能量采集器(PEHs)[1] -[4]面临着几个身体运动收集方面的挑战:如多轴运动、不规则频率和频繁低功率电平的不可预测振幅[5]。为了解决这些挑战，一种基于偏心转子的惯性PEH已经被开发出来，它利用多个磁弹拨柔性薄膜$(60 mu mathm {m})$ pzt -镍- pzt光束在小体积内显着增加收获的能量[5];与块状pzt梁相比，块状pzt梁在直接力驱动的PEHs中更可行。如图27.4.1所示，腕戴式多波束PEH将多轴体运动转换为每波束在90-160Hz频率范围内具有不同相位和衰减幅度(可达数伏)的交流电压。
{"title":"27.4 Multi-Beam Shared-Inductor Reconfigurable Voltage/SECE-Mode Piezoelectric Energy Harvesting of Multi-Axial Human Motion","authors":"Miao Meng, Ahmed Ibrahim, T. Xue, H. Yeo, Dixiong Wang, S. Roundy, S. Trolier-McKinstry, M. Kiani","doi":"10.1109/ISSCC.2019.8662414","DOIUrl":"https://doi.org/10.1109/ISSCC.2019.8662414","url":null,"abstract":"The past few years have witnessed a growing demand for self-powered wearables that can enable vigilant health monitoring, with 24/7 operation. Energy harvesting from human-body motion is attractive for wearables; however, conventional unidirectional single-cantilever-beam piezoelectric energy harvesters (PEHs) [1]–[4] suffer from several body-motion harvesting challenges: such as multi-axial motion, irregular frequencies, and unpredictable amplitudes with frequent low-power levels [5]. To address these challenges, an eccentric rotor-based inertial PEH has been developed, which utilizes multiple magnetically plucked flexible thin-film $(60 mu mathrm {m})$ PZT-nickel-PZT beams to significantly increase the harvested energy within a small volume [5]; compared to bulk-PZT beams that are more feasible in direct-force-driven PEHs. The wrist-worn multi-beam PEH, shown in Fig. 27.4.1, converts multi-axial body motion into AC voltages with different phases and decaying amplitudes (up to several volts) within the frequency range of 90–160Hz for each beam.","PeriodicalId":265551,"journal":{"name":"2019 IEEE International Solid- State Circuits Conference - (ISSCC)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122173461","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-03-06DOI: 10.1109/ISSCC.2019.8662536
Yao-Hong Liu, Sunil Sheelavant, M. Mercuri, Paul Mateman, J. Dijkhuis, A. W. Zomagboguelou, Arjan Breeschoten, Stefano Traferro, Yan Zhang, T. Torfs, Christian Bachmann, P. Harpe, M. Babaie
For remote vital signs and occupancy detection in many smart home/building applications, radar sensors are a preferred option over cameras, due to privacy preservation and robustness to ambient light conditions. These radars not only need to provide precise range and vital signs information over meters distance, but also preferably can operate on a battery up to a few months or even years, for cost and practical reasons (like smoke detectors). State-of-the-art remote vital-sign sensors typically use an impulse-radio UWB (IR-UWB) radar [1,2] because it provides a range resolution <20 cm. However, their power consumption is typically in the order of 100’s of mW, preventing long-term maintenance-free battery-powered operations. Although mains power can be used to supply such radars, this is not always available, depending on the location and the building type, and the installation cost (e.g., power routing) is significantly higher than for battery-powered ones. In this work, a burst-chirp radar with an energy-efficient chirp generation is proposed, leading to a record-low power consumption of 680 μW.
{"title":"9.3 A680 μW Burst-Chirp UWB Radar Transceiver for Vital Signs and Occupancy Sensing up to 15m Distance","authors":"Yao-Hong Liu, Sunil Sheelavant, M. Mercuri, Paul Mateman, J. Dijkhuis, A. W. Zomagboguelou, Arjan Breeschoten, Stefano Traferro, Yan Zhang, T. Torfs, Christian Bachmann, P. Harpe, M. Babaie","doi":"10.1109/ISSCC.2019.8662536","DOIUrl":"https://doi.org/10.1109/ISSCC.2019.8662536","url":null,"abstract":"For remote vital signs and occupancy detection in many smart home/building applications, radar sensors are a preferred option over cameras, due to privacy preservation and robustness to ambient light conditions. These radars not only need to provide precise range and vital signs information over meters distance, but also preferably can operate on a battery up to a few months or even years, for cost and practical reasons (like smoke detectors). State-of-the-art remote vital-sign sensors typically use an impulse-radio UWB (IR-UWB) radar [1,2] because it provides a range resolution <20 cm. However, their power consumption is typically in the order of 100’s of mW, preventing long-term maintenance-free battery-powered operations. Although mains power can be used to supply such radars, this is not always available, depending on the location and the building type, and the installation cost (e.g., power routing) is significantly higher than for battery-powered ones. In this work, a burst-chirp radar with an energy-efficient chirp generation is proposed, leading to a record-low power consumption of 680 μW.","PeriodicalId":265551,"journal":{"name":"2019 IEEE International Solid- State Circuits Conference - (ISSCC)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126228511","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-03-06DOI: 10.1109/ISSCC.2019.8662305
Parisa Mahmoudidaryan, Debashis Mandal, B. Bakkaloglu, S. Kiaei
Envelope tracking (ET) is widely used to improve the efficiency of linear power amplifiers (PAs) in applications such as LTE, LTE-Advanced inter- or intra-band carrier aggregation (CA), and for high-speed uplink packet access (HSUPA) with a high peak-to-average power ratio (PAPR). The hybrid ET modulator (ETM), where an efficient switching regulator (SWR) operates in parallel with a fast class-AB linear amplifier (LA), is one method to address the bandwidth (BW), power-efficiency and output ripple requirements.
{"title":"27.5 A 91%-Efficiency Envelope-Tracking Modulator Using Hysteresis-Controlled Three-Level Switching Regulator and Slew-Rate-Enhanced Linear Amplifier for LTE-80MHz Applications","authors":"Parisa Mahmoudidaryan, Debashis Mandal, B. Bakkaloglu, S. Kiaei","doi":"10.1109/ISSCC.2019.8662305","DOIUrl":"https://doi.org/10.1109/ISSCC.2019.8662305","url":null,"abstract":"Envelope tracking (ET) is widely used to improve the efficiency of linear power amplifiers (PAs) in applications such as LTE, LTE-Advanced inter- or intra-band carrier aggregation (CA), and for high-speed uplink packet access (HSUPA) with a high peak-to-average power ratio (PAPR). The hybrid ET modulator (ETM), where an efficient switching regulator (SWR) operates in parallel with a fast class-AB linear amplifier (LA), is one method to address the bandwidth (BW), power-efficiency and output ripple requirements.","PeriodicalId":265551,"journal":{"name":"2019 IEEE International Solid- State Circuits Conference - (ISSCC)","volume":"81 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131987813","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-03-06DOI: 10.1109/ISSCC.2019.8662507
Arun Manickam, Kae-Dyi You, Nicholas Wood, Lei Pei, Yang Liu, Rituraj Singh, N. Gamini, D. Shahrjerdi, R. Kuimelis, A. Hassibi
Electro-analytical (E-chem) biosensors offer unique advantages over widely used optical biosensors and can be considered ideal for low-cost, mass-deployable point-of-care (PoC) diagnostic devices [1]. They possess fully electronic and real-time transduction methods and require little or no external instrumentation. Despite these advantages, two fundamental challenges have hampered broad adoption of E-chem biosensors: 1C design and transducer (surface) material suitability. E-chem sensors require both low-noise and high detection dynamic range (DDR) front-end circuits and must also accommodate electrode-electrolyte interfaces with significant PVT variations and temporal drifts [2]–[5]. The absence of CMOS-compatible bio-electronic interfaces with adequate chemical and thermal stability has been another impediment [6].
{"title":"11.2 A CMOS Biosensor Array with 1024 3-Electrode Voltammetry Pixels and 93dB Dynamic Range","authors":"Arun Manickam, Kae-Dyi You, Nicholas Wood, Lei Pei, Yang Liu, Rituraj Singh, N. Gamini, D. Shahrjerdi, R. Kuimelis, A. Hassibi","doi":"10.1109/ISSCC.2019.8662507","DOIUrl":"https://doi.org/10.1109/ISSCC.2019.8662507","url":null,"abstract":"Electro-analytical (E-chem) biosensors offer unique advantages over widely used optical biosensors and can be considered ideal for low-cost, mass-deployable point-of-care (PoC) diagnostic devices [1]. They possess fully electronic and real-time transduction methods and require little or no external instrumentation. Despite these advantages, two fundamental challenges have hampered broad adoption of E-chem biosensors: 1C design and transducer (surface) material suitability. E-chem sensors require both low-noise and high detection dynamic range (DDR) front-end circuits and must also accommodate electrode-electrolyte interfaces with significant PVT variations and temporal drifts [2]–[5]. The absence of CMOS-compatible bio-electronic interfaces with adequate chemical and thermal stability has been another impediment [6].","PeriodicalId":265551,"journal":{"name":"2019 IEEE International Solid- State Circuits Conference - (ISSCC)","volume":"96 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115802342","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-03-06DOI: 10.1109/ISSCC.2019.8662462
Hyunsu Park, Junyoung Song, Yeonho Lee, Jincheol Sim, Jonghyuck Choi, Chulwoo Kim
Bandwidths of memory interfaces have been increased tremendously to enable high-data throughput while maintaining single-ended signaling and the supply voltage of I/O has been scaled down. Due to the increasing interface bandwidth the required area and power consumption has increased as well, resulting in higher I/O circuit design costs [3]. A high-loss channel causes ISI, which in turn limits the maximum data rate. Therefore, complex equalizers are needed for compensation, resulting in additional power dissipation and area overhead. As the data sampling rate increases, the deterministic and random noises degrade the data sampling margin and further limit the bandwidth. To lessen the negative impact of high channel loss and to reduce the forwarded clock frequency, multi-level signaling, such as PAM-4, can be used, as shown in Fig. 23.3.1 [2]. While the voltage sense margin for PAM-4 is theoretically $frac{1}{3}$ of NRZ, in practice it is smaller due to simultaneous switching noise (SSN), crosstalk, and random noise in single-ended signaling. Eventually, the reduced voltage sense margin degrades the SNR, which causes a reduction in the BER. On the other hand, PAM-3’s voltage sense margin is ${textstyle frac {1}{2}}$ of NRZ’s. Duo-binary signaling is commonly used for PAM-3 signaling [1]. However, the pin efficiency and the forwarded clock frequency for duo-binary signaling is the same as for NRZ. In this paper, a 3b/2UI PAM-3 single-ended memory interface is proposed, with a pin efficiency of 150% and a reduced clock frequency, compared to NRZ signaling. To address PAM-3 equalizer inefficiencies a tri-level decision feedback equalizer (DFE) is implemented in the receiver (RX).
{"title":"23.3 A 3-bit/2UI 27Gb/s PAM-3 Single-Ended Transceiver Using One-Tap DFE for Next-Generation Memory Interface","authors":"Hyunsu Park, Junyoung Song, Yeonho Lee, Jincheol Sim, Jonghyuck Choi, Chulwoo Kim","doi":"10.1109/ISSCC.2019.8662462","DOIUrl":"https://doi.org/10.1109/ISSCC.2019.8662462","url":null,"abstract":"Bandwidths of memory interfaces have been increased tremendously to enable high-data throughput while maintaining single-ended signaling and the supply voltage of I/O has been scaled down. Due to the increasing interface bandwidth the required area and power consumption has increased as well, resulting in higher I/O circuit design costs [3]. A high-loss channel causes ISI, which in turn limits the maximum data rate. Therefore, complex equalizers are needed for compensation, resulting in additional power dissipation and area overhead. As the data sampling rate increases, the deterministic and random noises degrade the data sampling margin and further limit the bandwidth. To lessen the negative impact of high channel loss and to reduce the forwarded clock frequency, multi-level signaling, such as PAM-4, can be used, as shown in Fig. 23.3.1 [2]. While the voltage sense margin for PAM-4 is theoretically $frac{1}{3}$ of NRZ, in practice it is smaller due to simultaneous switching noise (SSN), crosstalk, and random noise in single-ended signaling. Eventually, the reduced voltage sense margin degrades the SNR, which causes a reduction in the BER. On the other hand, PAM-3’s voltage sense margin is ${textstyle frac {1}{2}}$ of NRZ’s. Duo-binary signaling is commonly used for PAM-3 signaling [1]. However, the pin efficiency and the forwarded clock frequency for duo-binary signaling is the same as for NRZ. In this paper, a 3b/2UI PAM-3 single-ended memory interface is proposed, with a pin efficiency of 150% and a reduced clock frequency, compared to NRZ signaling. To address PAM-3 equalizer inefficiencies a tri-level decision feedback equalizer (DFE) is implemented in the receiver (RX).","PeriodicalId":265551,"journal":{"name":"2019 IEEE International Solid- State Circuits Conference - (ISSCC)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124588981","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-03-06DOI: 10.1109/ISSCC.2019.8662396
Yann LeCun
Historically, progress in neural networks and deep learning research has been greatly influenced by the available hardware and software tools. This paper identifies trends in deep learning research that will influence hardware architectures and software platforms of the future.
{"title":"1.1 Deep Learning Hardware: Past, Present, and Future","authors":"Yann LeCun","doi":"10.1109/ISSCC.2019.8662396","DOIUrl":"https://doi.org/10.1109/ISSCC.2019.8662396","url":null,"abstract":"Historically, progress in neural networks and deep learning research has been greatly influenced by the available hardware and software tools. This paper identifies trends in deep learning research that will influence hardware architectures and software platforms of the future.","PeriodicalId":265551,"journal":{"name":"2019 IEEE International Solid- State Circuits Conference - (ISSCC)","volume":"67 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130655639","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-02-22DOI: 10.1109/ISSCC.2019.8662344
Arvind Singh, Monodeep Kar, S. Mathew, Anand Rajan, V. De, S. Mukhopadhyay
Side channel attacks (SCA) exploit data-dependent information leakage through power consumption and electromagnetic (EM) emissions from cryptographic engines to uncover secret keys. Integrated inductive voltage regulators (IVR) with a randomized control loop [1] or switching frequency [2], and random voltage dithering [3] have demonstrated improved power side-channel analysis (PSCA) resistance. Simulation studies have shown PSCA resistance via shunt linear regulators [4]. This paper demonstrates improved power and EM SCA resistance of standard (unprotected) 128b AES engines with parallel (P-AES, 128b) and serial (S-AES, 8b) datapaths via an on-die security-aware all-digital series low-dropout (DLDO) regulator, commonly used for fine-grain SoC power management. The security-aware DLDO improves SCA resistance using control-loop induced perturbations in a baseline DLDO, enhanced by a random switching noise injector (SNI) via power stage control and a randomized reference voltage (R-VREF) generator coupled with all-digital clock modulation (ADCM).
{"title":"25.3 A 128b AES Engine with Higher Resistance to Power and Electromagnetic Side-Channel Attacks Enabled by a Security-Aware Integrated All-Digital Low-Dropout Regulator","authors":"Arvind Singh, Monodeep Kar, S. Mathew, Anand Rajan, V. De, S. Mukhopadhyay","doi":"10.1109/ISSCC.2019.8662344","DOIUrl":"https://doi.org/10.1109/ISSCC.2019.8662344","url":null,"abstract":"Side channel attacks (SCA) exploit data-dependent information leakage through power consumption and electromagnetic (EM) emissions from cryptographic engines to uncover secret keys. Integrated inductive voltage regulators (IVR) with a randomized control loop [1] or switching frequency [2], and random voltage dithering [3] have demonstrated improved power side-channel analysis (PSCA) resistance. Simulation studies have shown PSCA resistance via shunt linear regulators [4]. This paper demonstrates improved power and EM SCA resistance of standard (unprotected) 128b AES engines with parallel (P-AES, 128b) and serial (S-AES, 8b) datapaths via an on-die security-aware all-digital series low-dropout (DLDO) regulator, commonly used for fine-grain SoC power management. The security-aware DLDO improves SCA resistance using control-loop induced perturbations in a baseline DLDO, enhanced by a random switching noise injector (SNI) via power stage control and a randomized reference voltage (R-VREF) generator coupled with all-digital clock modulation (ADCM).","PeriodicalId":265551,"journal":{"name":"2019 IEEE International Solid- State Circuits Conference - (ISSCC)","volume":"244 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-02-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132551804","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-02-20DOI: 10.1109/ISSCC.2019.8662373
Nahmil Koo, Seonghwan Cho
Two-electrode ECG devices have gained popularity in the recent past to enable comfortable and long-term monitoring of cardiovascular health. As a ground or bias electrode is not used in a two-electrode ECG device, common-mode interference (CMI) caused by powerline coupling to the human body can be as large as a few tens of volts. Such a large CMI ruins the ECG recording, and thus the analog front-end of the ECG device must be immune to large CMI.
{"title":"22.4 A 27.8μW Biopotential Amplifier Tolerant to 30Vpp Common-Mode Interference for Two-Electrode ECG Recording in 0.18μm CMOS","authors":"Nahmil Koo, Seonghwan Cho","doi":"10.1109/ISSCC.2019.8662373","DOIUrl":"https://doi.org/10.1109/ISSCC.2019.8662373","url":null,"abstract":"Two-electrode ECG devices have gained popularity in the recent past to enable comfortable and long-term monitoring of cardiovascular health. As a ground or bias electrode is not used in a two-electrode ECG device, common-mode interference (CMI) caused by powerline coupling to the human body can be as large as a few tens of volts. Such a large CMI ruins the ECG recording, and thus the analog front-end of the ECG device must be immune to large CMI.","PeriodicalId":265551,"journal":{"name":"2019 IEEE International Solid- State Circuits Conference - (ISSCC)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-02-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115340230","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-02-18DOI: 10.1109/ISSCC.2019.8662512
Jinseok Park, Seungchan Lee, Dong-Ho Lee, Songcheol Hong
Millimeter-wave beamforming front-end ICs have been studied intensively as the service of 5G wireless communication is scheduled to begin in the near future [1–4]. The ICs include circuit elements such as PAs, LNAs, phase shifters, variable gain blocks, and switches to support antenna arrays for RF/hybrid beamforming. Due to the large number of antennas required for beamforming, the beamforming IC should include as many circuit elements as possible in a chip. The IC also needs high phase- and gain-control resolutions not only for controlling the beams precisely but also for error corrections and calibrations [1]. However, higher-bit controls of the phase and gain as well as high transmitting power increase the chip size in conventional structures, posing a trade-off between them. The front-end IC structure proposed here increases both transmitting power and gain/phase resolutions without increasing either the chip size or the power consumption.
{"title":"9.8 A 28GHz 20.3%-Transmitter-Efficiency 1.5°-Phase-Error Beamforming Front-End IC with Embedded Switches and Dual-Vector Variable-Gain Phase Shifters","authors":"Jinseok Park, Seungchan Lee, Dong-Ho Lee, Songcheol Hong","doi":"10.1109/ISSCC.2019.8662512","DOIUrl":"https://doi.org/10.1109/ISSCC.2019.8662512","url":null,"abstract":"Millimeter-wave beamforming front-end ICs have been studied intensively as the service of 5G wireless communication is scheduled to begin in the near future [1–4]. The ICs include circuit elements such as PAs, LNAs, phase shifters, variable gain blocks, and switches to support antenna arrays for RF/hybrid beamforming. Due to the large number of antennas required for beamforming, the beamforming IC should include as many circuit elements as possible in a chip. The IC also needs high phase- and gain-control resolutions not only for controlling the beams precisely but also for error corrections and calibrations [1]. However, higher-bit controls of the phase and gain as well as high transmitting power increase the chip size in conventional structures, posing a trade-off between them. The front-end IC structure proposed here increases both transmitting power and gain/phase resolutions without increasing either the chip size or the power consumption.","PeriodicalId":265551,"journal":{"name":"2019 IEEE International Solid- State Circuits Conference - (ISSCC)","volume":"275 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-02-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116437189","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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