Pub Date : 2019-02-01DOI: 10.1109/ISSCC.2019.8662494
Dihang Yang, A. Abidi, H. Darabi, Hao Xu, D. Murphy, Hao Wu, Zhaowen Wang
To deliver a good EVM performance, modern communication standards, such as WiFi 802.11ax with a 1024-QAM mode, require RF clocks with extremely low integrated phase error and low spurs. Because of their good scalability, digital phase-locked loops (DPLLs) have been widely studied [1]–[3]. However, they face two problems: nonlinearity and quantization noise of time-to-digital converters (TDCs). High-performance DPLLs require complicated TDC structures and calibrations. By contrast, a bang-bang phase detector (PD), i.e., a one-bit TDC, can be linear and low noise [4]. However, in the fractional mode, the PD gain is lowered by the significant phase fluctuations from the fractional divider. The gain can be restored by calibration, but the nonlinearity of the calibration circuit creates large spurs in an otherwise good integrated rms noise [5]. A sub-sampling PLL [6] avoids amplifying the PD noise and eliminates the loop divider, but still needs calibration for fractional operation. This work describes a calibration-free fractional BBDPLL. With the assistance of two auxiliary PLLs, this triple-loop PLL architecture combines the advantages of the sub-sampling PLL and bang-bang PD to achieve $131fs_{mathrm{rms}}$ jitter and lower than-70dBc fractional spurs.
{"title":"16.6 A Calibration-Free Triple-Loop Bang-Bang PLL Achieving 131fsrms Jitter and-70dBc Fractional Spurs","authors":"Dihang Yang, A. Abidi, H. Darabi, Hao Xu, D. Murphy, Hao Wu, Zhaowen Wang","doi":"10.1109/ISSCC.2019.8662494","DOIUrl":"https://doi.org/10.1109/ISSCC.2019.8662494","url":null,"abstract":"To deliver a good EVM performance, modern communication standards, such as WiFi 802.11ax with a 1024-QAM mode, require RF clocks with extremely low integrated phase error and low spurs. Because of their good scalability, digital phase-locked loops (DPLLs) have been widely studied [1]–[3]. However, they face two problems: nonlinearity and quantization noise of time-to-digital converters (TDCs). High-performance DPLLs require complicated TDC structures and calibrations. By contrast, a bang-bang phase detector (PD), i.e., a one-bit TDC, can be linear and low noise [4]. However, in the fractional mode, the PD gain is lowered by the significant phase fluctuations from the fractional divider. The gain can be restored by calibration, but the nonlinearity of the calibration circuit creates large spurs in an otherwise good integrated rms noise [5]. A sub-sampling PLL [6] avoids amplifying the PD noise and eliminates the loop divider, but still needs calibration for fractional operation. This work describes a calibration-free fractional BBDPLL. With the assistance of two auxiliary PLLs, this triple-loop PLL architecture combines the advantages of the sub-sampling PLL and bang-bang PD to achieve $131fs_{mathrm{rms}}$ jitter and lower than-70dBc fractional spurs.","PeriodicalId":265551,"journal":{"name":"2019 IEEE International Solid- State Circuits Conference - (ISSCC)","volume":"1060 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123159026","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-02-01DOI: 10.1109/ISSCC.2019.8662339
Yi-Wen Chen, J. Horng, Chin-Ho Chang, A. Kundu, Y. Peng, Mark Chen
Bandgap reference (BGR) circuits are widely used due to their stable output voltage over process, supply voltage and temperature variations. Reference voltage stability is critical for data-acquisition applications and lower supply voltages can reduce the power of mixed-signal systems. However BGR for analog circuits is one of the bottlenecks for sub-1V supply operation because BGR supply voltage is limited by VEB+VDS [1]. VEB refers to the emitter-base voltage of a pnp transistor which is limited to ~0.6 to 0.7V due to silicon junction cut-in voltage, while VDS is the drain-source saturation voltage of a current-mirror. The BGR temperature dependence is decided by the weighted sum of proportional-to-absolute-temperature(PTAT) and complementary-to-absolute-temperature (CTAT) terms. An alternative PTAT generator can be implemented by dVGS (gate-to-source voltage difference) of a MOS pair in subthreshold [2]. The CTAT generator can be implemented by special devices or using the gate-source voltage VGS of subthreshold MOSFETs. Although the VGS of a subthreshold MOSFET is smaller than emitter-base voltage of a pnp transistor, the MOSFET model inaccuracy in the subthreshold region and high process-dependent characteristic of MOSFET gate-source voltage induces high variation for voltage reference circuits.
{"title":"18.7 A 0.7V, 2.35% 3σ-Accuracy Bandgap Reference in 12nm CMOS","authors":"Yi-Wen Chen, J. Horng, Chin-Ho Chang, A. Kundu, Y. Peng, Mark Chen","doi":"10.1109/ISSCC.2019.8662339","DOIUrl":"https://doi.org/10.1109/ISSCC.2019.8662339","url":null,"abstract":"Bandgap reference (BGR) circuits are widely used due to their stable output voltage over process, supply voltage and temperature variations. Reference voltage stability is critical for data-acquisition applications and lower supply voltages can reduce the power of mixed-signal systems. However BGR for analog circuits is one of the bottlenecks for sub-1V supply operation because BGR supply voltage is limited by VEB+VDS [1]. VEB refers to the emitter-base voltage of a pnp transistor which is limited to ~0.6 to 0.7V due to silicon junction cut-in voltage, while VDS is the drain-source saturation voltage of a current-mirror. The BGR temperature dependence is decided by the weighted sum of proportional-to-absolute-temperature(PTAT) and complementary-to-absolute-temperature (CTAT) terms. An alternative PTAT generator can be implemented by dVGS (gate-to-source voltage difference) of a MOS pair in subthreshold [2]. The CTAT generator can be implemented by special devices or using the gate-source voltage VGS of subthreshold MOSFETs. Although the VGS of a subthreshold MOSFET is smaller than emitter-base voltage of a pnp transistor, the MOSFET model inaccuracy in the subthreshold region and high process-dependent characteristic of MOSFET gate-source voltage induces high variation for voltage reference circuits.","PeriodicalId":265551,"journal":{"name":"2019 IEEE International Solid- State Circuits Conference - (ISSCC)","volume":"61 47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126070121","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-02-01DOI: 10.1109/isscc.2019.8662452
{"title":"ISSCC 2020 Call for Papers","authors":"","doi":"10.1109/isscc.2019.8662452","DOIUrl":"https://doi.org/10.1109/isscc.2019.8662452","url":null,"abstract":"","PeriodicalId":265551,"journal":{"name":"2019 IEEE International Solid- State Circuits Conference - (ISSCC)","volume":"148 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121157593","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-02-01DOI: 10.1109/ISSCC.2019.8662404
Antonino Caizzone, Assim Boukhayma, C. Enz
Photoplethysmography (PPG) is a key technology allowing non-invasive monitoring of vital indicators such as heart rate (HR) and oxygen saturation (SpO2). Today, the total PPG sensor power consumption is dominated by the few tens of mA of the LEDs driving current. Different solutions have been proposed to solve this bottle-neck, either by reducing the LED duty cycle [1], [2] or by nonuniform sub-sampling [3]. A heart-beat-locked loop system that significantly reduces the LED power has been recently demonstrated [4]. However, this power reduction comes at the cost of more complexity since it requires a non-trivial heart beat prediction scheme and intrinsically hinders the full PPG wave representation.
{"title":"17.8 A 2.6μW Monolithic CMOS Photoplethysmographic Sensor Operating with 2μW LED Power","authors":"Antonino Caizzone, Assim Boukhayma, C. Enz","doi":"10.1109/ISSCC.2019.8662404","DOIUrl":"https://doi.org/10.1109/ISSCC.2019.8662404","url":null,"abstract":"Photoplethysmography (PPG) is a key technology allowing non-invasive monitoring of vital indicators such as heart rate (HR) and oxygen saturation (SpO2). Today, the total PPG sensor power consumption is dominated by the few tens of mA of the LEDs driving current. Different solutions have been proposed to solve this bottle-neck, either by reducing the LED duty cycle [1], [2] or by nonuniform sub-sampling [3]. A heart-beat-locked loop system that significantly reduces the LED power has been recently demonstrated [4]. However, this power reduction comes at the cost of more complexity since it requires a non-trivial heart beat prediction scheme and intrinsically hinders the full PPG wave representation.","PeriodicalId":265551,"journal":{"name":"2019 IEEE International Solid- State Circuits Conference - (ISSCC)","volume":"150 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116117558","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-02-01DOI: 10.1109/ISSCC.2019.8662523
Tamer A. Ali, R. Yousry, Henry Park, Ehung Chen, Po-Shuan Weng, Yi-Chieh Huang, Chun-Cheng Liu, Chien-Hua Wu, Shih-Hao Huang, Chungshi Lin, Ke-Chung Wu, Kun-Hung Tsai, K. Tan, A. ElShater, Kuang-Ren Chen, Wei-Hao Tsai, Huan-Sheng Chen, Weiyu Leng, Mazen Soliman
A soaring amount of data transfer has been witnessed in recent years. By 2020, 50 billion connected devices are expected, which will generate more than 2 zettabytes of data traffic annually. Given the constraints in power & space, this explosive growth puts high stress on network infrastructure, which demands low power, high BW, and area efficient transceivers. To improve BW efficiency, modern transceivers use PAM-4 instead of NRZ to double the throughput in the same BW. However, PAM-4 introduces substantial ISI, reduces peak-to-average-ratio, and imposes non-linearity constraints compared to NRZ modulation. Scaling in CMOS technology assisted the rise of DSP-based transceivers and digital equalization schemes to compensate PAM-4 non-idealities and achieve higher SNR at the receiver output [1–3].
{"title":"6.4 A 180mW 56Gb/s DSP-Based Transceiver for High Density IOs in Data Center Switches in 7nm FinFET Technology","authors":"Tamer A. Ali, R. Yousry, Henry Park, Ehung Chen, Po-Shuan Weng, Yi-Chieh Huang, Chun-Cheng Liu, Chien-Hua Wu, Shih-Hao Huang, Chungshi Lin, Ke-Chung Wu, Kun-Hung Tsai, K. Tan, A. ElShater, Kuang-Ren Chen, Wei-Hao Tsai, Huan-Sheng Chen, Weiyu Leng, Mazen Soliman","doi":"10.1109/ISSCC.2019.8662523","DOIUrl":"https://doi.org/10.1109/ISSCC.2019.8662523","url":null,"abstract":"A soaring amount of data transfer has been witnessed in recent years. By 2020, 50 billion connected devices are expected, which will generate more than 2 zettabytes of data traffic annually. Given the constraints in power & space, this explosive growth puts high stress on network infrastructure, which demands low power, high BW, and area efficient transceivers. To improve BW efficiency, modern transceivers use PAM-4 instead of NRZ to double the throughput in the same BW. However, PAM-4 introduces substantial ISI, reduces peak-to-average-ratio, and imposes non-linearity constraints compared to NRZ modulation. Scaling in CMOS technology assisted the rise of DSP-based transceivers and digital equalization schemes to compensate PAM-4 non-idealities and achieve higher SNR at the receiver output [1–3].","PeriodicalId":265551,"journal":{"name":"2019 IEEE International Solid- State Circuits Conference - (ISSCC)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115954097","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-02-01DOI: 10.1109/ISSCC.2019.8662374
Hanli Liu, Zheng Sun, Hongye Huang, W. Deng, T. Siriburanon, Jian Pang, Yun Wang, Rui Wu, T. Someya, A. Shirane, K. Okada
The demand for highly energy-efficient circuits and systems has exponentially increased for Systems on Chip (SoC). A fractional-N phase-locked loop (PLL) is one of the most important building blocks in SoCs for a variety of applications, such as frequency synthesis for wireless transceivers and system clock generation for processors, memories, and I/O interfaces. Recent developments in fractional-N digital PLLs (DPLLs) [1]–[3] have shown great potential for achieving low-power operation and small chip area. However, none of these works have achieved power consumption below $500 mu mathrm {W}$ due to the number of building blocks operating at the oscillator frequency. Furthermore, the digitally controlled oscillators (DCOs) in [1]–[3] consume more than $250 mu mathrm {W}$ of power to achieve a good phase noise and a high-enough amplitude for DPLL locking. A digital sub-sampling architecture [1], [2], [4] can potentially reduce the overall power consumption by bypassing these high-frequency building blocks. Unfortunately, the absence of frequency acquisition makes such architecture vulnerable to sudden or large frequency disturbances. Even though a background frequency-locked loop (FLL) [1], [4] can be applied, it consumes large power due to the counter working at the DCO frequency. The typical solution to save power consumption is to turn off the FLL [2] after the PLL has been stabilized. Despite the benefit of the power reduction, a sub-sampling PLL has multiple frequency lock-in ranges near the integer multiple of the reference frequency, which could cause false locking if the frequency disturbances are within those ranges. To address the above issues, this work presents a fractional-N DPLL achieving a $265 mu mathrm {W}$ power consumption with robust phase and frequency acquisition with negligible power overhead in a 65nm CMOS technology. It also achieves an rms jitter of 2.8ps, which corresponds to an FoM of-236.8dB.
片上系统(SoC)对高能效电路和系统的需求呈指数级增长。分数n锁相环(PLL)是soc中最重要的构建模块之一，适用于各种应用，例如无线收发器的频率合成和处理器、存储器和I/O接口的系统时钟生成。分数n数字锁相环(dpll)[1] -[3]的最新发展显示出实现低功耗和小芯片面积的巨大潜力。然而，由于在振荡器频率下工作的构建模块的数量，这些工作都没有实现低于500美元mu mathm {W}$的功耗。此外，[1]-[3]中的数字控制振荡器(dco)消耗超过250美元的功率，以实现良好的相位噪声和足够高的幅度用于DPLL锁定。数字子采样架构[1]，[2]，[4]可以通过绕过这些高频构建模块来潜在地降低总体功耗。不幸的是，缺乏频率采集使得这种结构容易受到突然或大频率干扰。尽管可以采用背景锁频环[1]，[4]，但由于计数器工作在DCO频率，因此功耗较大。节省功耗的典型解决方案是在锁相环稳定后关闭FLL[2]。尽管功率降低了，但子采样锁相环在参考频率的整数倍附近有多个频率锁定范围，如果频率干扰在这些范围内，则可能导致误锁。为了解决上述问题，本工作提出了一种分数n DPLL，在65nm CMOS技术中实现了265 mu 数学{W}$功耗，具有稳健的相位和频率采集，功耗可以忽略不计。它还实现了2.8ps的有效值抖动，对应于236.8 db的FoM。
{"title":"16.1 A 265μW Fractional-N Digital PLL with Seamless Automatic Switching Subsampling/Sampling Feedback Path and Duty-Cycled Frequency-Locked Loop in 65nm CMOS","authors":"Hanli Liu, Zheng Sun, Hongye Huang, W. Deng, T. Siriburanon, Jian Pang, Yun Wang, Rui Wu, T. Someya, A. Shirane, K. Okada","doi":"10.1109/ISSCC.2019.8662374","DOIUrl":"https://doi.org/10.1109/ISSCC.2019.8662374","url":null,"abstract":"The demand for highly energy-efficient circuits and systems has exponentially increased for Systems on Chip (SoC). A fractional-N phase-locked loop (PLL) is one of the most important building blocks in SoCs for a variety of applications, such as frequency synthesis for wireless transceivers and system clock generation for processors, memories, and I/O interfaces. Recent developments in fractional-N digital PLLs (DPLLs) [1]–[3] have shown great potential for achieving low-power operation and small chip area. However, none of these works have achieved power consumption below $500 mu mathrm {W}$ due to the number of building blocks operating at the oscillator frequency. Furthermore, the digitally controlled oscillators (DCOs) in [1]–[3] consume more than $250 mu mathrm {W}$ of power to achieve a good phase noise and a high-enough amplitude for DPLL locking. A digital sub-sampling architecture [1], [2], [4] can potentially reduce the overall power consumption by bypassing these high-frequency building blocks. Unfortunately, the absence of frequency acquisition makes such architecture vulnerable to sudden or large frequency disturbances. Even though a background frequency-locked loop (FLL) [1], [4] can be applied, it consumes large power due to the counter working at the DCO frequency. The typical solution to save power consumption is to turn off the FLL [2] after the PLL has been stabilized. Despite the benefit of the power reduction, a sub-sampling PLL has multiple frequency lock-in ranges near the integer multiple of the reference frequency, which could cause false locking if the frequency disturbances are within those ranges. To address the above issues, this work presents a fractional-N DPLL achieving a $265 mu mathrm {W}$ power consumption with robust phase and frequency acquisition with negligible power overhead in a 65nm CMOS technology. It also achieves an rms jitter of 2.8ps, which corresponds to an FoM of-236.8dB.","PeriodicalId":265551,"journal":{"name":"2019 IEEE International Solid- State Circuits Conference - (ISSCC)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125334016","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-02-01DOI: 10.1109/ISSCC.2019.8662473
Taehwan Kim, Pavan Bhargava, C. Poulton, J. Notaros, A. Yaacobi, E. Timurdogan, C. Baiocco, Nicholas M. Fahrenkopf, S. Kruger, Tat Ngai, Yukta Timalsina, M. Watts, V. Stojanović
The realization of a low-cost and robust optical beam-steering platform is a key enabler for a number of applications, including light detection and ranging (LIDAR) and free-space optical communications (FSO). Optical phased arrays (OPAs) have emerged as a promising solution, due to advancements in photonic integrated circuits (PIC) foundry processes, which have enabled high-precision fabrication of PICs with a large number of components [1]–[3]. In order to meet steering range and directivity requirements in systems such as autonomous vehicles, a clear path to scaling OPAs to millimeter-scale apertures with thousands of tight-pitched antenna elements is critical. As the element count grows, independent phase control for each element becomes crucial since maintaining coherence between elements becomes more difficult due to process variations. Moreover, independent control allows for unique system capabilities, such as multi-beam formation and converging/adaptive beams, which makes OPAs a particularly attractive solid-state beamforming technology.
{"title":"29.5 A Single-Chip Optical Phased Array in a 3D-Integrated Silicon Photonics/65nm CMOS Technology","authors":"Taehwan Kim, Pavan Bhargava, C. Poulton, J. Notaros, A. Yaacobi, E. Timurdogan, C. Baiocco, Nicholas M. Fahrenkopf, S. Kruger, Tat Ngai, Yukta Timalsina, M. Watts, V. Stojanović","doi":"10.1109/ISSCC.2019.8662473","DOIUrl":"https://doi.org/10.1109/ISSCC.2019.8662473","url":null,"abstract":"The realization of a low-cost and robust optical beam-steering platform is a key enabler for a number of applications, including light detection and ranging (LIDAR) and free-space optical communications (FSO). Optical phased arrays (OPAs) have emerged as a promising solution, due to advancements in photonic integrated circuits (PIC) foundry processes, which have enabled high-precision fabrication of PICs with a large number of components [1]–[3]. In order to meet steering range and directivity requirements in systems such as autonomous vehicles, a clear path to scaling OPAs to millimeter-scale apertures with thousands of tight-pitched antenna elements is critical. As the element count grows, independent phase control for each element becomes crucial since maintaining coherence between elements becomes more difficult due to process variations. Moreover, independent control allows for unique system capabilities, such as multi-beam formation and converging/adaptive beams, which makes OPAs a particularly attractive solid-state beamforming technology.","PeriodicalId":265551,"journal":{"name":"2019 IEEE International Solid- State Circuits Conference - (ISSCC)","volume":"22 10","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113974724","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-02-01DOI: 10.1109/ISSCC.2019.8662468
Susnata Mondal, Rahul Singh, J. Paramesh
This paper presents a 28/37/39GHz front-end applicable to beyond-5G wireless networks. It features three key contributions. First, a fully connected (FC) transmitter architecture is introduced for hybrid beamforming (HBF); it is shown that the power efficiency of FC-HBF is superior to the conventional partially connected (PC) HBF for a given modulation and antenna geometry. Second, a compact/low-cost circuit concept is introduced that supports bi-directional T/R operation concurrently at 28 and 37/39GHz, thereby facilitating multi-antenna carrier-aggregation (CA) or MIMO TDD with high antenna count. Third, a built-in mechanism for dual-band, per antenna, self-interference cancellation (SIC) is introduced, thanks to the FC-HBF architecture. The front-end is applicable to FDD or full-duplex (FD) multi-antenna systems; such SIC is not available in PC-HBF’s. Also, the front-end is directly applicable to dual-band digital beamformers (DBF).
{"title":"21.3 A Reconfigurable Bidirectional 28/37/39GHz Front-End Supporting MIMO-TDD, Carrier Aggregation TDD and FDD/Full-Duplex with Self-Interference Cancellation in Digital and Fully Connected Hybrid Beamformers","authors":"Susnata Mondal, Rahul Singh, J. Paramesh","doi":"10.1109/ISSCC.2019.8662468","DOIUrl":"https://doi.org/10.1109/ISSCC.2019.8662468","url":null,"abstract":"This paper presents a 28/37/39GHz front-end applicable to beyond-5G wireless networks. It features three key contributions. First, a fully connected (FC) transmitter architecture is introduced for hybrid beamforming (HBF); it is shown that the power efficiency of FC-HBF is superior to the conventional partially connected (PC) HBF for a given modulation and antenna geometry. Second, a compact/low-cost circuit concept is introduced that supports bi-directional T/R operation concurrently at 28 and 37/39GHz, thereby facilitating multi-antenna carrier-aggregation (CA) or MIMO TDD with high antenna count. Third, a built-in mechanism for dual-band, per antenna, self-interference cancellation (SIC) is introduced, thanks to the FC-HBF architecture. The front-end is applicable to FDD or full-duplex (FD) multi-antenna systems; such SIC is not available in PC-HBF’s. Also, the front-end is directly applicable to dual-band digital beamformers (DBF).","PeriodicalId":265551,"journal":{"name":"2019 IEEE International Solid- State Circuits Conference - (ISSCC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133763810","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-02-01DOI: 10.1109/ISSCC.2019.8662312
Xiaofeng Yang, Chi-Hang Chan, Yan Zhu, R. Martins
Low-jitter phase-locked loops (PLLs) are critical building blocks in various systems, including wireless and wireline communications and ADCs. LC oscillators exhibit low phase noise (PN) but suffer from large area, magnetic coupling, and small tuning range. While ring voltage-controlled oscillators (RVCO) are free from the above issues, their inferior PN performance restricts their applicability. The injection-locked clock multiplier (ILCM) attains a low PN through phase realignment. However, both the PN and the reference spur deteriorate when the injection instant drifts over PVT. Although the frequency-tracking loop (FTL) can calibrate the center frequency, its power consumption, converging speed, and accuracy limit the performance of the ILCM [1, 2]. The Type-I PLL performs wideband filtering [3], but its efficiency is 3dB lower than that of the ILCM [4]. A PLL with fast phase-error correction (FPEC) [4] realizes a PN filtering close to the ILCM and keeps a small reference spur. Nevertheless, both Type-I and FPEC PLLs rely on the closed-loop wideband filtering to achieve a low PN. The drifted loop gain over PVT significantly degrades jitter performance and even causes instability, implying a trade-off between wideband filtering and stability. Consequently, a loop-gain calibration [4] is necessary to maintain the stability and low PN.
{"title":"16.3 A −246dB Jitter-FoM 2.4GHz Calibration-Free Ring-Oscillator PLL Achieving 9% Jitter Variation Over PVT","authors":"Xiaofeng Yang, Chi-Hang Chan, Yan Zhu, R. Martins","doi":"10.1109/ISSCC.2019.8662312","DOIUrl":"https://doi.org/10.1109/ISSCC.2019.8662312","url":null,"abstract":"Low-jitter phase-locked loops (PLLs) are critical building blocks in various systems, including wireless and wireline communications and ADCs. LC oscillators exhibit low phase noise (PN) but suffer from large area, magnetic coupling, and small tuning range. While ring voltage-controlled oscillators (RVCO) are free from the above issues, their inferior PN performance restricts their applicability. The injection-locked clock multiplier (ILCM) attains a low PN through phase realignment. However, both the PN and the reference spur deteriorate when the injection instant drifts over PVT. Although the frequency-tracking loop (FTL) can calibrate the center frequency, its power consumption, converging speed, and accuracy limit the performance of the ILCM [1, 2]. The Type-I PLL performs wideband filtering [3], but its efficiency is 3dB lower than that of the ILCM [4]. A PLL with fast phase-error correction (FPEC) [4] realizes a PN filtering close to the ILCM and keeps a small reference spur. Nevertheless, both Type-I and FPEC PLLs rely on the closed-loop wideband filtering to achieve a low PN. The drifted loop gain over PVT significantly degrades jitter performance and even causes instability, implying a trade-off between wideband filtering and stability. Consequently, a loop-gain calibration [4] is necessary to maintain the stability and low PN.","PeriodicalId":265551,"journal":{"name":"2019 IEEE International Solid- State Circuits Conference - (ISSCC)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134020222","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-02-01DOI: 10.1109/ISSCC.2019.8662302
Jinsu Lee, Juhyoung Lee, Donghyeon Han, Jinmook Lee, Gwangtae Park, H. Yoo
Recently, deep neural network (DNN) hardware accelerators have been reported for energy-efficient deep learning (DL) acceleration [1–6]. Most prior DNN inference accelerators are trained in the cloud using public datasets; parameters are then downloaded to implement AI [1–5]. However, local DNN learning with domain-specific and private data is required meet various user preferences on edge or mobile devices. Since edge and mobile devices contain only limited computation capability with battery power, an energy-efficient DNN learning processor is necessary. Only [6] supported on-chip DNN learning, but it was not energy-efficient, as it did not utilize sparsity which represents 37%-61% of the inputs for various CNNs, such as VGG16, AlexNet and ResNet-18, as shown in Fig. 7.7.1. Although [3–5] utilized the sparsity, they only considered the inference phase with inter-channel accumulation in Fig. 7.7.1, and did not support intra-channel accumulation for the weight-gradient generation (WG) step of the learning phase. Also, [6] adopted FP16, but it was not energy optimal because FP8 is enough for many input operands with 4× less energy than FP16.
{"title":"7.7 LNPU: A 25.3TFLOPS/W Sparse Deep-Neural-Network Learning Processor with Fine-Grained Mixed Precision of FP8-FP16","authors":"Jinsu Lee, Juhyoung Lee, Donghyeon Han, Jinmook Lee, Gwangtae Park, H. Yoo","doi":"10.1109/ISSCC.2019.8662302","DOIUrl":"https://doi.org/10.1109/ISSCC.2019.8662302","url":null,"abstract":"Recently, deep neural network (DNN) hardware accelerators have been reported for energy-efficient deep learning (DL) acceleration [1–6]. Most prior DNN inference accelerators are trained in the cloud using public datasets; parameters are then downloaded to implement AI [1–5]. However, local DNN learning with domain-specific and private data is required meet various user preferences on edge or mobile devices. Since edge and mobile devices contain only limited computation capability with battery power, an energy-efficient DNN learning processor is necessary. Only [6] supported on-chip DNN learning, but it was not energy-efficient, as it did not utilize sparsity which represents 37%-61% of the inputs for various CNNs, such as VGG16, AlexNet and ResNet-18, as shown in Fig. 7.7.1. Although [3–5] utilized the sparsity, they only considered the inference phase with inter-channel accumulation in Fig. 7.7.1, and did not support intra-channel accumulation for the weight-gradient generation (WG) step of the learning phase. Also, [6] adopted FP16, but it was not energy optimal because FP8 is enough for many input operands with 4× less energy than FP16.","PeriodicalId":265551,"journal":{"name":"2019 IEEE International Solid- State Circuits Conference - (ISSCC)","volume":"298 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134543634","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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