The continuous development of wireline communication encourages transmitters to operate at higher speeds. The applications of 400GbE also push the transmitter to be designed at 112Gb/s for a single lane [1–2]. However, the use of advanced processes $(lt16$ nm) hardly reduces the costs. This paper presents a 112Gb/s PAM-4 voltage-mode transmitter fabricated in 40nm CMOS by using the proposed two-step FFE and the automatic phase alignment techniques, improving the output bandwidth as well as the power dissipation. It delivers high-quality eye diagrams under 5.5dB loss at 28GHz with 3.89pJ/b efficiency.
{"title":"6.7 A 112Gb/s PAM-4 Voltage-Mode Transmitter with 4-Tap Two-Step FFE and Automatic Phase Alignment Techniques in 40nm CMOS","authors":"Pen-Jui Peng, Yan-Ting Chen, Sheng-Tsung Lai, Chao-Hsuan Chen, Hsiang-En Huang, T. Shih","doi":"10.1109/ISSCC.2019.8662361","DOIUrl":"https://doi.org/10.1109/ISSCC.2019.8662361","url":null,"abstract":"The continuous development of wireline communication encourages transmitters to operate at higher speeds. The applications of 400GbE also push the transmitter to be designed at 112Gb/s for a single lane [1–2]. However, the use of advanced processes $(lt16$ nm) hardly reduces the costs. This paper presents a 112Gb/s PAM-4 voltage-mode transmitter fabricated in 40nm CMOS by using the proposed two-step FFE and the automatic phase alignment techniques, improving the output bandwidth as well as the power dissipation. It delivers high-quality eye diagrams under 5.5dB loss at 28GHz with 3.89pJ/b efficiency.","PeriodicalId":265551,"journal":{"name":"2019 IEEE International Solid- State Circuits Conference - (ISSCC)","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116658653","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-02-01DOI: 10.1109/ISSCC.2019.8662442
L. E. Aygun, Prakhar Kumar, Zhiwu Zheng, Ting-Sheng Chen, S. Wagner, J. Sturm, N. Verma
Tactile sensing has wide-ranging applications, from intelligent surfaces to advanced robotics. Large-Area Electronics (LAE), based on low-temp. fabrication $(lt 200 ^{circ}mathrm {C})$ of thin films, presents distinct capabilities, due to compatibility with a broad range of materials (enabling diverse transducers), as well as large and flexible substrates and materials-deposition methods (enabling expansive and formfitting sensing arrays). However, low performance/energy-efficiency of LAE thin-film transistors (TFTs) necessitates hybrid systems, integrating Si-CMOS ICs for system functions (sensor readout/control, processing, etc.). Initial work shows that a primary challenge in hybrid systems is the large number of interfaces required between LAE and CMOS, particularly as the number of sensors scales [1], [2]. This paper presents a force-sensing system that exploits signal sparsity exhibited in many large-area tactile-sensing applications (e.g., detecting point damage/stress in structures [3]), to reduce interfacing complexity to the level of sparsity, rather than a level related to the number of sensors (e.g., [1]). This is achieved via compressed sensing (CS), enabling sensor-acquisition by simple switches, readily implemented using TFTs. While CS has previously been leveraged in a hybrid-system architecture targeting signal sampling-rate requirements [2], this system applies it for high spatial resolution in tactile sensing.
{"title":"17.3 Hybrid System for Efficient LAE-CMOS Interfacing in Large-Scale Tactile-Sensing Skins via TFT-Based Compressed Sensing","authors":"L. E. Aygun, Prakhar Kumar, Zhiwu Zheng, Ting-Sheng Chen, S. Wagner, J. Sturm, N. Verma","doi":"10.1109/ISSCC.2019.8662442","DOIUrl":"https://doi.org/10.1109/ISSCC.2019.8662442","url":null,"abstract":"Tactile sensing has wide-ranging applications, from intelligent surfaces to advanced robotics. Large-Area Electronics (LAE), based on low-temp. fabrication $(lt 200 ^{circ}mathrm {C})$ of thin films, presents distinct capabilities, due to compatibility with a broad range of materials (enabling diverse transducers), as well as large and flexible substrates and materials-deposition methods (enabling expansive and formfitting sensing arrays). However, low performance/energy-efficiency of LAE thin-film transistors (TFTs) necessitates hybrid systems, integrating Si-CMOS ICs for system functions (sensor readout/control, processing, etc.). Initial work shows that a primary challenge in hybrid systems is the large number of interfaces required between LAE and CMOS, particularly as the number of sensors scales [1], [2]. This paper presents a force-sensing system that exploits signal sparsity exhibited in many large-area tactile-sensing applications (e.g., detecting point damage/stress in structures [3]), to reduce interfacing complexity to the level of sparsity, rather than a level related to the number of sensors (e.g., [1]). This is achieved via compressed sensing (CS), enabling sensor-acquisition by simple switches, readily implemented using TFTs. While CS has previously been leveraged in a hybrid-system architecture targeting signal sampling-rate requirements [2], this system applies it for high spatial resolution in tactile sensing.","PeriodicalId":265551,"journal":{"name":"2019 IEEE International Solid- State Circuits Conference - (ISSCC)","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125183732","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-02-01DOI: 10.1109/ISSCC.2019.8662542
Seyed Danesh, W. Holland, J. Spalding, Michael Guidry, J. Hurwitz
Millions of utility electricity meters are deployed globally to determine billable energy consumption. These devices are factory calibrated, and then perform measurement without interruption over their lifetime. Once in the field their accuracy is unknown due to component aging and high voltage/current events [1]. Meters are periodically replaced as a preventive measure, leading to the unnecessary replacement of perfectly good meters while some inaccurate meters may remain in field. This paper presents an energy-measurement front-end that enables continuous background Condition Base Monitoring (CbM) over the lifetime of a meter. Crucially it monitors the performance of its voltage and current sensors, which are typically the largest sources of inaccuracy and drift. During normal operation, small test signals (“stimuli”), with adaptable but well-defined characteristics are injected into the sensors. Their amplitudes at the front-end’s output are then extracted to determine the gain accuracy of the full signal chain. In order to do this, the system must meet 3 main challenges. First, it must be able to generate and inject highly stable and accurate stimuli signals into the sensors. Second, it must have a wide dynamic range in order to accurately extract the stimuli in the presence of unknown and significantly larger load signals. Third, it must incorporate all the digital signal processing involved with stimuli signal selection, extraction and removal. This paper describes the circuit techniques used to address the first two challenges.
{"title":"10.1 An Energy Measurement Front-End with Integrated In-Situ Background Full System Accuracy Monitoring Including the Current and Voltage Sensors","authors":"Seyed Danesh, W. Holland, J. Spalding, Michael Guidry, J. Hurwitz","doi":"10.1109/ISSCC.2019.8662542","DOIUrl":"https://doi.org/10.1109/ISSCC.2019.8662542","url":null,"abstract":"Millions of utility electricity meters are deployed globally to determine billable energy consumption. These devices are factory calibrated, and then perform measurement without interruption over their lifetime. Once in the field their accuracy is unknown due to component aging and high voltage/current events [1]. Meters are periodically replaced as a preventive measure, leading to the unnecessary replacement of perfectly good meters while some inaccurate meters may remain in field. This paper presents an energy-measurement front-end that enables continuous background Condition Base Monitoring (CbM) over the lifetime of a meter. Crucially it monitors the performance of its voltage and current sensors, which are typically the largest sources of inaccuracy and drift. During normal operation, small test signals (“stimuli”), with adaptable but well-defined characteristics are injected into the sensors. Their amplitudes at the front-end’s output are then extracted to determine the gain accuracy of the full signal chain. In order to do this, the system must meet 3 main challenges. First, it must be able to generate and inject highly stable and accurate stimuli signals into the sensors. Second, it must have a wide dynamic range in order to accurately extract the stimuli in the presence of unknown and significantly larger load signals. Third, it must incorporate all the digital signal processing involved with stimuli signal selection, extraction and removal. This paper describes the circuit techniques used to address the first two challenges.","PeriodicalId":265551,"journal":{"name":"2019 IEEE International Solid- State Circuits Conference - (ISSCC)","volume":"158 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123457994","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-02-01DOI: 10.1109/ISSCC.2019.8662457
S. Pan, Cagri Gurleyuk, Matheus Pimenta, K. Makinwa
Resistor-based temperature sensors can achieve much higher resolution and energy efficiency than conventional BJT-based sensors [1], but they typically occupy more area $(gt 0.25$ mm2) and have lower operating temperatures $(le 125 ^{circ}mathrm {C})$ [2]–[4]. This work describes a 0.12mm2 resistor-based sensor that uses a Wien-bridge (WB) filter to achieve $0.1 ^{circ}mathrm {C} (3 sigma)$ inaccuracy from $- 40 ^{circ}mathrm {C}$ to $180 ^{circ}mathrm {C}$. Compared to a state-of-the-art WB sensor [4], it occupies $6 times $ less area and achieves comparable relative accuracy over a 76% wider operating range.
{"title":"10.3 A 0.12mm2 Wien-Bridge Temperature Sensor with 0.1°C (3σ) Inaccuracy from -40°C to 180°C","authors":"S. Pan, Cagri Gurleyuk, Matheus Pimenta, K. Makinwa","doi":"10.1109/ISSCC.2019.8662457","DOIUrl":"https://doi.org/10.1109/ISSCC.2019.8662457","url":null,"abstract":"Resistor-based temperature sensors can achieve much higher resolution and energy efficiency than conventional BJT-based sensors [1], but they typically occupy more area $(gt 0.25$ mm2) and have lower operating temperatures $(le 125 ^{circ}mathrm {C})$ [2]–[4]. This work describes a 0.12mm2 resistor-based sensor that uses a Wien-bridge (WB) filter to achieve $0.1 ^{circ}mathrm {C} (3 sigma)$ inaccuracy from $- 40 ^{circ}mathrm {C}$ to $180 ^{circ}mathrm {C}$. Compared to a state-of-the-art WB sensor [4], it occupies $6 times $ less area and achieves comparable relative accuracy over a 76% wider operating range.","PeriodicalId":265551,"journal":{"name":"2019 IEEE International Solid- State Circuits Conference - (ISSCC)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114374676","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-02-01DOI: 10.1109/ISSCC.2019.8662294
C. Schaef, Nachiket V. Desai, H. Krishnamurthy, Sheldon Weng, H. Do, William J. Lambert, K. Radhakrishnan, K. Ravichandran, J. Tschanz, V. De
Fully Integrated Voltage Regulators (FIVR) with package-embedded air-core inductors [1] or on-die solenoid inductors with planar magnetic core [2] promise efficient power delivery and fine-grain wide-range DVFS in complex SoCs while providing fast transient response. The FIVR must provide high conversion efficiency across a wide operating range of output voltages and load currents, including light to medium loads, to maximize the overall energy efficiency of the SoC across different power states. Phase shedding and switch scaling have been used for high-frequency FIVR designs with pulse-width modulation (PWM) control in continuous conduction mode (CCM) to maintain high efficiency for large load currents [1–5], and pulse-frequency modulation (PFM) and hysteretic control have been used to achieve high efficiency across light to medium loads [3–5]. In this paper, we present an FIVR in 14nm CMOS with a 2.5nH air-core inductor embedded in an ultrathin coreless package $( 200 mu m$ thick) (Fig. 8.5.7), featuring self-trimmed, soft-switched and digitally controlled variable ON-time DCM operation up to 70MHz to achieve high conversion efficiencies across light to medium load currents ranging from 5mA to 500mA and wide 0.7-1.2V output voltage range. The FIVR uses a cascoded thin-gate powertrain (Fig. 8.5.1) to support input voltages up to 2Vmax with the cascode bias rail set at $V_{in} /2$ which consumes $lt/pgtlt1$ uA at light load. A small thick-gate device is connected across the inductor to dampen oscillations when the power stage is in a high-impedance state. The output voltage is monitored by a comparator with sub-ns response time which triggers an inductor current pulse when the output drops below the reference voltage. A resistor divider with a feedforward capacitor is used to achieve fast response time.
{"title":"8.5 A Fully Integrated Voltage Regulator in 14nm CMOS with Package-Embedded Air-Core Inductor Featuring Self-Trimmed, Digitally Controlled Variable On-Time Discontinuous Conduction Mode Operation","authors":"C. Schaef, Nachiket V. Desai, H. Krishnamurthy, Sheldon Weng, H. Do, William J. Lambert, K. Radhakrishnan, K. Ravichandran, J. Tschanz, V. De","doi":"10.1109/ISSCC.2019.8662294","DOIUrl":"https://doi.org/10.1109/ISSCC.2019.8662294","url":null,"abstract":"Fully Integrated Voltage Regulators (FIVR) with package-embedded air-core inductors [1] or on-die solenoid inductors with planar magnetic core [2] promise efficient power delivery and fine-grain wide-range DVFS in complex SoCs while providing fast transient response. The FIVR must provide high conversion efficiency across a wide operating range of output voltages and load currents, including light to medium loads, to maximize the overall energy efficiency of the SoC across different power states. Phase shedding and switch scaling have been used for high-frequency FIVR designs with pulse-width modulation (PWM) control in continuous conduction mode (CCM) to maintain high efficiency for large load currents [1–5], and pulse-frequency modulation (PFM) and hysteretic control have been used to achieve high efficiency across light to medium loads [3–5]. In this paper, we present an FIVR in 14nm CMOS with a 2.5nH air-core inductor embedded in an ultrathin coreless package $( 200 mu m$ thick) (Fig. 8.5.7), featuring self-trimmed, soft-switched and digitally controlled variable ON-time DCM operation up to 70MHz to achieve high conversion efficiencies across light to medium load currents ranging from 5mA to 500mA and wide 0.7-1.2V output voltage range. The FIVR uses a cascoded thin-gate powertrain (Fig. 8.5.1) to support input voltages up to 2Vmax with the cascode bias rail set at $V_{in} /2$ which consumes $lt/pgtlt1$ uA at light load. A small thick-gate device is connected across the inductor to dampen oscillations when the power stage is in a high-impedance state. The output voltage is monitored by a comparator with sub-ns response time which triggers an inductor current pulse when the output drops below the reference voltage. A resistor divider with a feedforward capacitor is used to achieve fast response time.","PeriodicalId":265551,"journal":{"name":"2019 IEEE International Solid- State Circuits Conference - (ISSCC)","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114516258","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-02-01DOI: 10.1109/ISSCC.2019.8662476
Jinook Song, Yun-Jin Cho, Jun-Seok Park, Jun-Woo Jang, Sehwan Lee, Joonho Song, Jae-Gon Lee, Inyup Kang
Deep learning has been widely applied for image and speech recognition. Response time, connectivity, privacy and security drive applications towards mobile platforms rather than cloud. For mobile systems-on-a-chip (SoCs), energy-efficient neural processing units (NPU) have been studied for performing the convolutional layers (CLs) and fully-connected layers (FCLs) [2–5] in deep neural networks. Moreover, considering that neural networks are getting deeper, the NPU needs to integrate 1K or even more multiply/accumulate (MAC) units. For energy efficiency, compression of neural networks has been studied by pruning neural connections and quantizing weights and features with 8b or even lower fixed-point precision without accuracy loss [1]. A hardware accelerator exploited network sparsity for high utilization of MAC units [3]. However, since it is challenging to predict where pruning is possible, the accelerator needed complex circuitry for selecting an array of features corresponding to an array of non-zero weights. For reducing the power of MAC operations, bit-serial multipliers have been applied [5]. Generally, extremely low- or variable-bit-precision neural networks need to be carefully trained.
{"title":"7.1 An 11.5TOPS/W 1024-MAC Butterfly Structure Dual-Core Sparsity-Aware Neural Processing Unit in 8nm Flagship Mobile SoC","authors":"Jinook Song, Yun-Jin Cho, Jun-Seok Park, Jun-Woo Jang, Sehwan Lee, Joonho Song, Jae-Gon Lee, Inyup Kang","doi":"10.1109/ISSCC.2019.8662476","DOIUrl":"https://doi.org/10.1109/ISSCC.2019.8662476","url":null,"abstract":"Deep learning has been widely applied for image and speech recognition. Response time, connectivity, privacy and security drive applications towards mobile platforms rather than cloud. For mobile systems-on-a-chip (SoCs), energy-efficient neural processing units (NPU) have been studied for performing the convolutional layers (CLs) and fully-connected layers (FCLs) [2–5] in deep neural networks. Moreover, considering that neural networks are getting deeper, the NPU needs to integrate 1K or even more multiply/accumulate (MAC) units. For energy efficiency, compression of neural networks has been studied by pruning neural connections and quantizing weights and features with 8b or even lower fixed-point precision without accuracy loss [1]. A hardware accelerator exploited network sparsity for high utilization of MAC units [3]. However, since it is challenging to predict where pruning is possible, the accelerator needed complex circuitry for selecting an array of features corresponding to an array of non-zero weights. For reducing the power of MAC operations, bit-serial multipliers have been applied [5]. Generally, extremely low- or variable-bit-precision neural networks need to be carefully trained.","PeriodicalId":265551,"journal":{"name":"2019 IEEE International Solid- State Circuits Conference - (ISSCC)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129510262","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-02-01DOI: 10.1109/ISSCC.2019.8662420
Ji-Seon Paek, Takahiro Nomiyama, Jae-Yeol Han, Ik-Hwan Kim, Yumi Lee, Dongsu Kim, Euiyoung Park, Sung-Jun Lee, Jongwoo Lee, T. Cho, Inyup Kang
The 5G-New-Radio (NR) standard in millimeter wave (mm-wave) bands requires a low-cost antenna module consisting of a phased-array transceiver with beamforming [1], an antenna array, and a power management IC (PMIC). Since a typical on-chip mm-wave CMOS power-amplifier (PA) arrays have poor power efficiency due to the lossy substrate and the low maximum available-gain frequency of CMOS processes, they cause serious thermal issues due to the high power density and reduce battery life in a mobile handset. Recently, supply-modulation (SM) techniques, such as an envelope tracking (ET) and an average-power tracking (APT) instead of a direct battery-connected supply, have been introduced to enhance PA efficiency [2]. However, these techniques have few challenges, such as limited ET tracking bandwidth and APT transition time, to support new requirements of the 5G NR standard. In order to manage the power effectively of a phased-array module, a special SM technique named symbol-power tracking (SPT) is proposed for the power management in this work. The SPT controls the supply voltage of mm-wave PA arrays every few micro-second (symbol to symbol), which is much faster than that of APT, which adjusts the output voltage every one millisecond (sub-frame to sub-frame).
{"title":"15.2 A 90ns/V Fast-Transition Symbol-Power-Tracking Buck Converter for 5G mm-Wave Phased-Array Transceiver","authors":"Ji-Seon Paek, Takahiro Nomiyama, Jae-Yeol Han, Ik-Hwan Kim, Yumi Lee, Dongsu Kim, Euiyoung Park, Sung-Jun Lee, Jongwoo Lee, T. Cho, Inyup Kang","doi":"10.1109/ISSCC.2019.8662420","DOIUrl":"https://doi.org/10.1109/ISSCC.2019.8662420","url":null,"abstract":"The 5G-New-Radio (NR) standard in millimeter wave (mm-wave) bands requires a low-cost antenna module consisting of a phased-array transceiver with beamforming [1], an antenna array, and a power management IC (PMIC). Since a typical on-chip mm-wave CMOS power-amplifier (PA) arrays have poor power efficiency due to the lossy substrate and the low maximum available-gain frequency of CMOS processes, they cause serious thermal issues due to the high power density and reduce battery life in a mobile handset. Recently, supply-modulation (SM) techniques, such as an envelope tracking (ET) and an average-power tracking (APT) instead of a direct battery-connected supply, have been introduced to enhance PA efficiency [2]. However, these techniques have few challenges, such as limited ET tracking bandwidth and APT transition time, to support new requirements of the 5G NR standard. In order to manage the power effectively of a phased-array module, a special SM technique named symbol-power tracking (SPT) is proposed for the power management in this work. The SPT controls the supply voltage of mm-wave PA arrays every few micro-second (symbol to symbol), which is much faster than that of APT, which adjusts the output voltage every one millisecond (sub-frame to sub-frame).","PeriodicalId":265551,"journal":{"name":"2019 IEEE International Solid- State Circuits Conference - (ISSCC)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127875331","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-02-01DOI: 10.1109/ISSCC.2019.8662511
Aoyang Zhang, M. Chen
Modern wireless communication systems often utilize spectrum-efficient modulation schemes for higher data throughput, given the finite bandwidth. This type of modulation schemes, such as Orthogonal Frequency Division Multiplexing (OFDM), results in a high peak-to-average power ratio (PAPR) for the transmitted signal. Therefore, power amplifier efficiency in the power back-off (PBO) region has become an important design target. Meanwhile, obtaining high output power and high average efficiency still remains a key design challenge when developing an integrated CMOS PA. Recently, a subharmonic switching (SHS) digital PA architecture was reported in [1]. It toggles the PA cell at the subharmonic component of the carrier frequency (Fc) to achieve power back-off. The slower toggling rate reduces dynamic and conduction loss in the switching PA, resulting in better PBO efficiency. However, the SHS PA requires additional notch filtering of the subharmonic components in the matching network. Therefore, we propose a phase-interleaved architecture that combines three SHS PAs to increase output power (Watt-level) and inherently cancel the subharmonic components in the PBO mode, thereby alleviating the burden of the matching network. Moreover, multiple subharmonic components are utilized to create a greater number of efficiency peaks in the PBO region. This is referred to as a multi-SHS scheme. Lastly, a hybrid Class-G operation, in combination with the multi-SHS scheme, is used to further enhance average efficiency.
{"title":"4.1 A Watt-Level Phase-Interleaved Multi-Subharmonic Switching Digital Power Amplifier Achieving 31.4% Average Drain Efficiency","authors":"Aoyang Zhang, M. Chen","doi":"10.1109/ISSCC.2019.8662511","DOIUrl":"https://doi.org/10.1109/ISSCC.2019.8662511","url":null,"abstract":"Modern wireless communication systems often utilize spectrum-efficient modulation schemes for higher data throughput, given the finite bandwidth. This type of modulation schemes, such as Orthogonal Frequency Division Multiplexing (OFDM), results in a high peak-to-average power ratio (PAPR) for the transmitted signal. Therefore, power amplifier efficiency in the power back-off (PBO) region has become an important design target. Meanwhile, obtaining high output power and high average efficiency still remains a key design challenge when developing an integrated CMOS PA. Recently, a subharmonic switching (SHS) digital PA architecture was reported in [1]. It toggles the PA cell at the subharmonic component of the carrier frequency (Fc) to achieve power back-off. The slower toggling rate reduces dynamic and conduction loss in the switching PA, resulting in better PBO efficiency. However, the SHS PA requires additional notch filtering of the subharmonic components in the matching network. Therefore, we propose a phase-interleaved architecture that combines three SHS PAs to increase output power (Watt-level) and inherently cancel the subharmonic components in the PBO mode, thereby alleviating the burden of the matching network. Moreover, multiple subharmonic components are utilized to create a greater number of efficiency peaks in the PBO region. This is referred to as a multi-SHS scheme. Lastly, a hybrid Class-G operation, in combination with the multi-SHS scheme, is used to further enhance average efficiency.","PeriodicalId":265551,"journal":{"name":"2019 IEEE International Solid- State Circuits Conference - (ISSCC)","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127883883","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-02-01DOI: 10.1109/ISSCC.2019.8662490
A. Ramkaj, J. P. Ramos, Yifan Lyu, M. Strackx, Marcel J. M. Pelgrom, M. Steyaert, M. Verhelst, F. Tavernier
Emerging 5G communication systems require ADCs to directly digitize wide bandwidth (BW) signals with high spectral purity at low power consumption. Current state-of-the-art solutions include mainly time-interleaved (TI) pipelined [1–4] or pipelined-SAR [5] architectures, enhanced by digital calibration. To ensure a sufficiently high input BW, all these designs employ a static front-end buffer. This buffer often dissipates more power than the ADC itself, significantly deteriorates the linearity and noise performance, and severely limits the available swing, unless over-voltage or multiple supplies are used [1–5].
{"title":"3.3 A 5GS/s 158.6mW 12b Passive-Sampling 8×-Interleaved Hybrid ADC with 9.4 ENOB and 160.5dB FoMS in 28nm CMOS","authors":"A. Ramkaj, J. P. Ramos, Yifan Lyu, M. Strackx, Marcel J. M. Pelgrom, M. Steyaert, M. Verhelst, F. Tavernier","doi":"10.1109/ISSCC.2019.8662490","DOIUrl":"https://doi.org/10.1109/ISSCC.2019.8662490","url":null,"abstract":"Emerging 5G communication systems require ADCs to directly digitize wide bandwidth (BW) signals with high spectral purity at low power consumption. Current state-of-the-art solutions include mainly time-interleaved (TI) pipelined [1–4] or pipelined-SAR [5] architectures, enhanced by digital calibration. To ensure a sufficiently high input BW, all these designs employ a static front-end buffer. This buffer often dissipates more power than the ADC itself, significantly deteriorates the linearity and noise performance, and severely limits the available swing, unless over-voltage or multiple supplies are used [1–5].","PeriodicalId":265551,"journal":{"name":"2019 IEEE International Solid- State Circuits Conference - (ISSCC)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128040297","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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