Pub Date : 2019-02-01DOI: 10.1109/ISSCC.2019.8662496
S. Pellerano, Steven Callender, W. Shin, Yanjie Wang, Somnath Kundu, Abhishek Agrawal, Peter Sagazio, B. Carlton, F. Sheikh, A. Amadjikpe, William J. Lambert, Divya Shree Vemparala, Mark Chakravorti, Satoshi Suzuki, R. Flory, C. Hull
Fifth-generation cellular communication standards (5G) target Gb/s data-rates, pushing the industry beyond the sub-6GHz bands. Tens of GHz of spectrum are available in the frequency bands from 30 to 300GHz. To maintain acceptable link budgets with sufficient antenna apertures, arrays are typically required at these frequencies and electrical beam steering is needed to retain spatial coverage. For such complex systems, highly-integrated, low-cost and energy-efficient SoCs are desirable to enable volume deployment. FinFET technologies are an ideal candidate to tackle this challenging integration, given the excellent balance between density and RF/mm-wave performance that has been recently demonstrated [1].
{"title":"9.7 A Scalable 71-to-76GHz 64-Element Phased-Array Transceiver Module with 2×2 Direct-Conversion IC in 22nm FinFET CMOS Technology","authors":"S. Pellerano, Steven Callender, W. Shin, Yanjie Wang, Somnath Kundu, Abhishek Agrawal, Peter Sagazio, B. Carlton, F. Sheikh, A. Amadjikpe, William J. Lambert, Divya Shree Vemparala, Mark Chakravorti, Satoshi Suzuki, R. Flory, C. Hull","doi":"10.1109/ISSCC.2019.8662496","DOIUrl":"https://doi.org/10.1109/ISSCC.2019.8662496","url":null,"abstract":"Fifth-generation cellular communication standards (5G) target Gb/s data-rates, pushing the industry beyond the sub-6GHz bands. Tens of GHz of spectrum are available in the frequency bands from 30 to 300GHz. To maintain acceptable link budgets with sufficient antenna apertures, arrays are typically required at these frequencies and electrical beam steering is needed to retain spatial coverage. For such complex systems, highly-integrated, low-cost and energy-efficient SoCs are desirable to enable volume deployment. FinFET technologies are an ideal candidate to tackle this challenging integration, given the excellent balance between density and RF/mm-wave performance that has been recently demonstrated [1].","PeriodicalId":265551,"journal":{"name":"2019 IEEE International Solid- State Circuits Conference - (ISSCC)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116409496","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-02-01DOI: 10.1109/ISSCC.2019.8662453
Minho Choi, Chan-Ho Kye, Jonghyun Oh, Min-Seong Choo, D. Jeong
Achieving a fast-transient response is a major challenge when designing a switching regulator for a processor. Furthermore, high-frequency operation with small passive devices and robust control with a small area footprint in a CMOS-logic process are essential for integrated digital-system voltage regulators. A 4-phase hysteretic converter [1] has a superior transient response using a 3.3V input voltage. However, the analog control circuit under a low input voltage suffers from limited dynamic range. Although a time-based design [2] minimizes the use of analog circuits, it still requires an accurate analog-to-time converter and exhibits only a moderate transient response time. A buck voltage regulator (VR) with a digital controller has been proposed for modern digital systems [3], [4], since it can take advantage of the advanced digital process. However, with a conventional digital proportional-integral-derivative (PID) controller it is difficult to offer high bandwidth due to the large power and chip area of the PID and the required multi-bit ADC. Thus, an additional circuit, the resistive transient assist (RTA), was proposed [4]. This paper presents an all-digital synthesizable VR using a digitally-adaptive on-time (DAOT) controller implemented in a CMOS logic process to achieve a fast recovery time.
{"title":"27.7 A Synthesizable Digital AOT 4-Phase Buck Voltage Regulator for Digital Systems with 0.0054mm2 Controller and 80ns Recovery Time","authors":"Minho Choi, Chan-Ho Kye, Jonghyun Oh, Min-Seong Choo, D. Jeong","doi":"10.1109/ISSCC.2019.8662453","DOIUrl":"https://doi.org/10.1109/ISSCC.2019.8662453","url":null,"abstract":"Achieving a fast-transient response is a major challenge when designing a switching regulator for a processor. Furthermore, high-frequency operation with small passive devices and robust control with a small area footprint in a CMOS-logic process are essential for integrated digital-system voltage regulators. A 4-phase hysteretic converter [1] has a superior transient response using a 3.3V input voltage. However, the analog control circuit under a low input voltage suffers from limited dynamic range. Although a time-based design [2] minimizes the use of analog circuits, it still requires an accurate analog-to-time converter and exhibits only a moderate transient response time. A buck voltage regulator (VR) with a digital controller has been proposed for modern digital systems [3], [4], since it can take advantage of the advanced digital process. However, with a conventional digital proportional-integral-derivative (PID) controller it is difficult to offer high bandwidth due to the large power and chip area of the PID and the required multi-bit ADC. Thus, an additional circuit, the resistive transient assist (RTA), was proposed [4]. This paper presents an all-digital synthesizable VR using a digitally-adaptive on-time (DAOT) controller implemented in a CMOS logic process to achieve a fast recovery time.","PeriodicalId":265551,"journal":{"name":"2019 IEEE International Solid- State Circuits Conference - (ISSCC)","volume":"95 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115520796","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-02-01DOI: 10.1109/ISSCC.2019.8662358
M. Fujita
In 1956 at the Dartmouth conference, the terminology of artificial intelligence (AI) was first used. In those days it was also called as symbolic AI (Symbolic-AI) [1]. For example, let us assume a block world problem in Fig 17.1.1 (right), where a block is represented as a symbol, “Block1”, and it can be operated by operators such as “PICKUP(Block1). In order to apply the operator “PICKUP” to the target object, “Block1”, the AI system has to check the pre-condition such as “CLEAR Block1”, which means there is no object on “Block1”. The Fig. 17.1.1 (right) shows an example of a task from State-A to State-B. The system has to search the possible operators and the pre-conditions so that State-B is achieved. There are many basic algorithms developed in Symbolic-AI era, which are often used today including the A*-search algorithm. Shakey is the representative example of intelligent robots based on Symbolic-AI. It was a wheel-based movable robot equipped with a TV-camera, Laser-Range-Finder, etc. It can move blocks in the real world using Symbolic-AI technologies. Its behavior control architecture is shown in Fig 17.1.1 (left). It has three steps, SENSE, PLAN, and ACT. Therefore, it is known as the SENSE-PLAN-ACT architecture. It is computationally intensive especially in the PLAN computation, therefore it is difficult if the environment is dynamically changing.
{"title":"17.1 AI x Robotics: Technology Challenges and Opportunities in Sensors, Actuators, and Integrated Circuits","authors":"M. Fujita","doi":"10.1109/ISSCC.2019.8662358","DOIUrl":"https://doi.org/10.1109/ISSCC.2019.8662358","url":null,"abstract":"In 1956 at the Dartmouth conference, the terminology of artificial intelligence (AI) was first used. In those days it was also called as symbolic AI (Symbolic-AI) [1]. For example, let us assume a block world problem in Fig 17.1.1 (right), where a block is represented as a symbol, “Block1”, and it can be operated by operators such as “PICKUP(Block1). In order to apply the operator “PICKUP” to the target object, “Block1”, the AI system has to check the pre-condition such as “CLEAR Block1”, which means there is no object on “Block1”. The Fig. 17.1.1 (right) shows an example of a task from State-A to State-B. The system has to search the possible operators and the pre-conditions so that State-B is achieved. There are many basic algorithms developed in Symbolic-AI era, which are often used today including the A*-search algorithm. Shakey is the representative example of intelligent robots based on Symbolic-AI. It was a wheel-based movable robot equipped with a TV-camera, Laser-Range-Finder, etc. It can move blocks in the real world using Symbolic-AI technologies. Its behavior control architecture is shown in Fig 17.1.1 (left). It has three steps, SENSE, PLAN, and ACT. Therefore, it is known as the SENSE-PLAN-ACT architecture. It is computationally intensive especially in the PLAN computation, therefore it is difficult if the environment is dynamically changing.","PeriodicalId":265551,"journal":{"name":"2019 IEEE International Solid- State Circuits Conference - (ISSCC)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115555273","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-02-01DOI: 10.1109/isscc.2019.8662518
S. Pamarti, M. Chen, N. Krishnapura
With the end of Moore’s Law and Dennard Scaling, domain-specific architecture remains the only viable path to continue scaling computing performance. In this era of domain-specific hardware, differentiation will come primarily from efficient hardware design and hardware designers, and the system level will play a key role. Domain specific hardware achieves its performance from massive parallelism, specialized data types and operations, fine-grained memory systems, and efficient interconnection networks. The latter two, memory and interconnect, are domain independent and will be provided by general-purpose platforms, such as GPUs. Hardware system designers will differentiate their products via algorithm-hardware co-design, and the design of special purpose units that provide the data-type and operation specialization – like the TensorCores and RTCores in a Turing GPU. hardware and software accelerate demanding applications, including machine learning, bioinformatics, and logical designing innovative and efficient experimental computing systems. microprocessor hardware MOSSIM Simulation and the Torus wormhole routing and virtual-channel flow control. J-Machine and the M-Machine, experimental parallel computer systems the separation of mechanisms from programming models and very low overhead synchronization and communication mechanisms. the Imagine processor, the concepts of stream processing and partitioned register organizations, the Merrimac supercomputer, to GPU computing, and the ELM low-power processor. National Academy Engineering productivity has not kept pace with Moore’s Law, leading to prohibitive increases in development costs and team sizes for leading edge SoCs. The main strategy for managing complexity in today’s SoCs is through design reuse of proprietary licensed intellectual property (IP) modules. The current IP reuse approach has markedly improved productivity, but the single layer point-to-point approach has limited the scope of reuse and abstraction. A pathway to revolutionizing SoC design is to copy the software design community, where open source has enabled a deep software hierarchy with many abstraction layers, significantly increasing productivity. Open source technology forms the foundation of fields like machine learning that are moving forward at an astounding rate. The adoption of an open source culture within the circuit design community would speed up the circuit innovation cycle, while democratizing access to specialized circuits needed to create state-of-the-art mixed-signal systems. Andreas Olofsson is DARPA the Microsystems Technology Office. His include intelligent design automation, system optimization, and open hardware. Prior to his at DARPA, Mr. Olofsson 20 to designing and testing low-power processors and mixed-signal circuits at Texas Instruments, Analog Devices, and Adapteva. Chip products designed by Mr. Olofsson include low-power digital signal processors (DSPs), charge-coupled device (CCD) readout circuits, and ma
{"title":"EE6: \"How Can Hardware Designers Reclaim the Spotlight?\"","authors":"S. Pamarti, M. Chen, N. Krishnapura","doi":"10.1109/isscc.2019.8662518","DOIUrl":"https://doi.org/10.1109/isscc.2019.8662518","url":null,"abstract":"With the end of Moore’s Law and Dennard Scaling, domain-specific architecture remains the only viable path to continue scaling computing performance. In this era of domain-specific hardware, differentiation will come primarily from efficient hardware design and hardware designers, and the system level will play a key role. Domain specific hardware achieves its performance from massive parallelism, specialized data types and operations, fine-grained memory systems, and efficient interconnection networks. The latter two, memory and interconnect, are domain independent and will be provided by general-purpose platforms, such as GPUs. Hardware system designers will differentiate their products via algorithm-hardware co-design, and the design of special purpose units that provide the data-type and operation specialization – like the TensorCores and RTCores in a Turing GPU. hardware and software accelerate demanding applications, including machine learning, bioinformatics, and logical designing innovative and efficient experimental computing systems. microprocessor hardware MOSSIM Simulation and the Torus wormhole routing and virtual-channel flow control. J-Machine and the M-Machine, experimental parallel computer systems the separation of mechanisms from programming models and very low overhead synchronization and communication mechanisms. the Imagine processor, the concepts of stream processing and partitioned register organizations, the Merrimac supercomputer, to GPU computing, and the ELM low-power processor. National Academy Engineering productivity has not kept pace with Moore’s Law, leading to prohibitive increases in development costs and team sizes for leading edge SoCs. The main strategy for managing complexity in today’s SoCs is through design reuse of proprietary licensed intellectual property (IP) modules. The current IP reuse approach has markedly improved productivity, but the single layer point-to-point approach has limited the scope of reuse and abstraction. A pathway to revolutionizing SoC design is to copy the software design community, where open source has enabled a deep software hierarchy with many abstraction layers, significantly increasing productivity. Open source technology forms the foundation of fields like machine learning that are moving forward at an astounding rate. The adoption of an open source culture within the circuit design community would speed up the circuit innovation cycle, while democratizing access to specialized circuits needed to create state-of-the-art mixed-signal systems. Andreas Olofsson is DARPA the Microsystems Technology Office. His include intelligent design automation, system optimization, and open hardware. Prior to his at DARPA, Mr. Olofsson 20 to designing and testing low-power processors and mixed-signal circuits at Texas Instruments, Analog Devices, and Adapteva. Chip products designed by Mr. Olofsson include low-power digital signal processors (DSPs), charge-coupled device (CCD) readout circuits, and ma","PeriodicalId":265551,"journal":{"name":"2019 IEEE International Solid- State Circuits Conference - (ISSCC)","volume":"43 6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116079042","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-02-01DOI: 10.1109/ISSCC.2019.8662538
Youngwoo Ji, Jungho Lee, Byungsub Kim, Hong-June Park, J. Sim
A voltage reference circuit is an essential block of a system to generate various internal voltages. Since it consumes static power in standby modes, it plays an important role in energy management of battery-limited applications. The bandgap reference (BGR) has been a widely used approach since it provides a well-defined large value ($sim 1.15text{V}$) with strong immunity to process, supply and temperature changes. Recently proposed BGR approaches achieved a great reduction of power consumption by taking only complementary-to-absolute-temperature (CTAT) quantity from a PN junction while they obtained proportional-to-absolute-temperature (PTAT) quantity from alternative CMOS circuits such as a CTAT divider [1]or leakage-based two diodes [2, 3]. However, these BGR schemes are formed with multiple branches fed from a supply voltage above 1.4V and require power consumption of order larger than 10nW. To further reduce power consumption, threshold-based reference approaches with CMOS-only circuits have been proposed [4, 5]. However, generation of a practical voltage level by up-scaling of a threshold-based reference also causes an amplification of the uncertainty by the same factor. I addition, though [4]has successfully achieved sub-nW power consumption, the threshold voltage eventually suffers from a large sensitivity to process variation because the threshold voltage is affected by process and design parameters. To reduce the effect of process variation, [5]proposed a PMOS-only circuit. However, it requires a different body biasing for a threshold difference that is needed to generate a non-zero reference.
{"title":"18.8 A 192pW Hybrid Bandgap-Vth Reference with Process Dependence Compensated by a Dimension-Induced Side-Effect","authors":"Youngwoo Ji, Jungho Lee, Byungsub Kim, Hong-June Park, J. Sim","doi":"10.1109/ISSCC.2019.8662538","DOIUrl":"https://doi.org/10.1109/ISSCC.2019.8662538","url":null,"abstract":"A voltage reference circuit is an essential block of a system to generate various internal voltages. Since it consumes static power in standby modes, it plays an important role in energy management of battery-limited applications. The bandgap reference (BGR) has been a widely used approach since it provides a well-defined large value ($sim 1.15text{V}$) with strong immunity to process, supply and temperature changes. Recently proposed BGR approaches achieved a great reduction of power consumption by taking only complementary-to-absolute-temperature (CTAT) quantity from a PN junction while they obtained proportional-to-absolute-temperature (PTAT) quantity from alternative CMOS circuits such as a CTAT divider [1]or leakage-based two diodes [2, 3]. However, these BGR schemes are formed with multiple branches fed from a supply voltage above 1.4V and require power consumption of order larger than 10nW. To further reduce power consumption, threshold-based reference approaches with CMOS-only circuits have been proposed [4, 5]. However, generation of a practical voltage level by up-scaling of a threshold-based reference also causes an amplification of the uncertainty by the same factor. I addition, though [4]has successfully achieved sub-nW power consumption, the threshold voltage eventually suffers from a large sensitivity to process variation because the threshold voltage is affected by process and design parameters. To reduce the effect of process variation, [5]proposed a PMOS-only circuit. However, it requires a different body biasing for a threshold difference that is needed to generate a non-zero reference.","PeriodicalId":265551,"journal":{"name":"2019 IEEE International Solid- State Circuits Conference - (ISSCC)","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126767652","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-02-01DOI: 10.1109/ISSCC.2019.8662327
Michael Peter Kennedy, Yann Donnelly, James Breslin, Stefano Tulisi, Sanganagouda Patil, Ciaran Curtin, Stephen Brookes, Brian Shelly, P. Griffin, M. Keaveney
The instantaneous divide value of the multimodulus divider in the feedback path of a fractional-N PLL is determined by a divider controller, which is usually implemented as a digital delta-sigma modulator $(mathrm (D)Delta Sigma mathrm (M))$. A disadvantage of the fractional-N PLL is the presence of fractional spurs, which result from interaction between the signal introduced by the $(mathrm (D)Delta Sigma mathrm (M))$ and nonlinearities in the loop. When fractional spurs at frequencies close to integer boundaries lie inside the loop bandwidth, they cannot be attenuated by filtering. The Successive Requantizer (SR) is an alternative to the $(mathrm (D)Delta Sigma mathrm (M))$-based divider controller, which randomizes the quantization process more effectively than $(mathrm (D)Delta Sigma mathrm (M))$. Wang et al. reported a worst-case in-band fractional spur of -64dBc in a 2.4GHz charge-pump PLL [1]. Liang and Wang reported a -70dBc worst-case fractional spur in a 2GHz analog PLL with a hybrid VCO and $(mathrm (D)Delta Sigma mathrm (M))$-based divider controller [2]. Familier and Galton improved the performance of the SR by implementing higher-order noise shaping. They achieved a worst-case fractional spur of -72dBc in a 3.3GHz analog PLL with a third-order SR [3]. The SR quantizes the frequency-control word one bit at a time, and, therefore, requires n stages in the case of an n-bit modulus. Thirunarayanan et al. implemented a hybrid MASH-SR divider-controller structure using four SR quantization blocks [4]. The divider-controller architecture described in this paper enables a 4.48GHz analog PLL to exhibit an in-band fractional spur of -80dBc and a -145dBc reference spur. It comprises a conventional MASH $(mathrm (D)Delta Sigma mathrm (M))$ followed by a programmable Probability Mass Redistributor (PMR). The PMR requantizes the output of the $(mathrm (D)Delta Sigma mathrm (M))$ and redistributes its samples in such a way that the in-band spurs are reduced by 7dB compared to the $(mathrm (D)Delta Sigma mathrm (M))$ alone.
{"title":"16.9 4.48GHz 0.18μm SiGe BiCMOS Exact-Frequency Fractional-N Frequency Synthesizer with Spurious-Tone Suppression Yielding a -80dBc In-Band Fractional Spur","authors":"Michael Peter Kennedy, Yann Donnelly, James Breslin, Stefano Tulisi, Sanganagouda Patil, Ciaran Curtin, Stephen Brookes, Brian Shelly, P. Griffin, M. Keaveney","doi":"10.1109/ISSCC.2019.8662327","DOIUrl":"https://doi.org/10.1109/ISSCC.2019.8662327","url":null,"abstract":"The instantaneous divide value of the multimodulus divider in the feedback path of a fractional-N PLL is determined by a divider controller, which is usually implemented as a digital delta-sigma modulator $(mathrm (D)Delta Sigma mathrm (M))$. A disadvantage of the fractional-N PLL is the presence of fractional spurs, which result from interaction between the signal introduced by the $(mathrm (D)Delta Sigma mathrm (M))$ and nonlinearities in the loop. When fractional spurs at frequencies close to integer boundaries lie inside the loop bandwidth, they cannot be attenuated by filtering. The Successive Requantizer (SR) is an alternative to the $(mathrm (D)Delta Sigma mathrm (M))$-based divider controller, which randomizes the quantization process more effectively than $(mathrm (D)Delta Sigma mathrm (M))$. Wang et al. reported a worst-case in-band fractional spur of -64dBc in a 2.4GHz charge-pump PLL [1]. Liang and Wang reported a -70dBc worst-case fractional spur in a 2GHz analog PLL with a hybrid VCO and $(mathrm (D)Delta Sigma mathrm (M))$-based divider controller [2]. Familier and Galton improved the performance of the SR by implementing higher-order noise shaping. They achieved a worst-case fractional spur of -72dBc in a 3.3GHz analog PLL with a third-order SR [3]. The SR quantizes the frequency-control word one bit at a time, and, therefore, requires n stages in the case of an n-bit modulus. Thirunarayanan et al. implemented a hybrid MASH-SR divider-controller structure using four SR quantization blocks [4]. The divider-controller architecture described in this paper enables a 4.48GHz analog PLL to exhibit an in-band fractional spur of -80dBc and a -145dBc reference spur. It comprises a conventional MASH $(mathrm (D)Delta Sigma mathrm (M))$ followed by a programmable Probability Mass Redistributor (PMR). The PMR requantizes the output of the $(mathrm (D)Delta Sigma mathrm (M))$ and redistributes its samples in such a way that the in-band spurs are reduced by 7dB compared to the $(mathrm (D)Delta Sigma mathrm (M))$ alone.","PeriodicalId":265551,"journal":{"name":"2019 IEEE International Solid- State Circuits Conference - (ISSCC)","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124138769","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-02-01DOI: 10.1109/ISSCC.2019.8662539
G. D. Besten
Car communication networks are rapidly evolving from a collection of sub-MHz control busses to a high-performance data network for connecting sensors, processors, and actuators to enable autonomous driving [1]. A plurality of high-bandwidth nodes like cameras, displays, radars, and wireless transceivers, demand a network architecture revision and drive the need-for-speed on individual links [1], [2]. Harsh automotive requirements on emissions, robustness, and reliability apply [3]. Size and weight of cables are critical factors too. These challenges inspired a new class of single-pair physical layer solutions, with 100Mb/s currently in production, 1Gb/s ramping up soon, and new standards for 2.5–10Gb/s in development.
{"title":"30.1 Single-Pair Automotive PHY Solutions from 10Mb/s to 10Gb/s and Beyond","authors":"G. D. Besten","doi":"10.1109/ISSCC.2019.8662539","DOIUrl":"https://doi.org/10.1109/ISSCC.2019.8662539","url":null,"abstract":"Car communication networks are rapidly evolving from a collection of sub-MHz control busses to a high-performance data network for connecting sensors, processors, and actuators to enable autonomous driving [1]. A plurality of high-bandwidth nodes like cameras, displays, radars, and wireless transceivers, demand a network architecture revision and drive the need-for-speed on individual links [1], [2]. Harsh automotive requirements on emissions, robustness, and reliability apply [3]. Size and weight of cables are critical factors too. These challenges inspired a new class of single-pair physical layer solutions, with 100Mb/s currently in production, 1Gb/s ramping up soon, and new standards for 2.5–10Gb/s in development.","PeriodicalId":265551,"journal":{"name":"2019 IEEE International Solid- State Circuits Conference - (ISSCC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124780031","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-02-01DOI: 10.1109/ISSCC.2019.8662467
A. Nagulu, H. Krishnaswamy
There has been significant recent research on non-magnetic non-reciprocal components at RF and mm-waves, such as circulators and isolators, based on spatio-temporal modulation [1-3]. Circulators enable simultaneous transmit and receive (STAR) on a shared antenna for applications such as full-duplex wireless communication and FMCW radar. While there has been exciting initial progress, existing architectures do not scale well to mm-waves, whether they are based on switch-based conductivity modulation [1, 2]or varactor-based permittivity modulation [3]. Loss levels increase due to losses in the switches or varactors, isolation is degraded due to reflections produced by parasitics, and power consumption is high due to the relatively high modulation frequencies required. In this work, we present a non-magnetic CMOS 60GHz circulator based on spatiotemporal conductivity modulation (STCM) across a loss/dispersion-engineered bandpass filter. This new architecture improves the insertion loss, isolation, power consumption, and spurious response compared to prior art. The 60GHz circulator achieves 3.6dB/3.1dB insertion loss for TX-to-ANT/ANT-to-RX paths, respectively, TX-to-RX isolation $> 40$dB over 1.3GHz, 3.2dB of ANT-to-RX NF, $> +19.5$dBm TX-to-ANT/ANT-to-RX IP1dBS and spurious tones lower than -30dBc at both ANT and RX ports at a power consumption of 41mW from 1.2V.
{"title":"28.5 Non-Magnetic 60GHz SOI CMOS Circulator Based on Loss/Dispersion-Engineered Switched Bandpass Filters","authors":"A. Nagulu, H. Krishnaswamy","doi":"10.1109/ISSCC.2019.8662467","DOIUrl":"https://doi.org/10.1109/ISSCC.2019.8662467","url":null,"abstract":"There has been significant recent research on non-magnetic non-reciprocal components at RF and mm-waves, such as circulators and isolators, based on spatio-temporal modulation [1-3]. Circulators enable simultaneous transmit and receive (STAR) on a shared antenna for applications such as full-duplex wireless communication and FMCW radar. While there has been exciting initial progress, existing architectures do not scale well to mm-waves, whether they are based on switch-based conductivity modulation [1, 2]or varactor-based permittivity modulation [3]. Loss levels increase due to losses in the switches or varactors, isolation is degraded due to reflections produced by parasitics, and power consumption is high due to the relatively high modulation frequencies required. In this work, we present a non-magnetic CMOS 60GHz circulator based on spatiotemporal conductivity modulation (STCM) across a loss/dispersion-engineered bandpass filter. This new architecture improves the insertion loss, isolation, power consumption, and spurious response compared to prior art. The 60GHz circulator achieves 3.6dB/3.1dB insertion loss for TX-to-ANT/ANT-to-RX paths, respectively, TX-to-RX isolation $> 40$dB over 1.3GHz, 3.2dB of ANT-to-RX NF, $> +19.5$dBm TX-to-ANT/ANT-to-RX IP1dBS and spurious tones lower than -30dBc at both ANT and RX ports at a power consumption of 41mW from 1.2V.","PeriodicalId":265551,"journal":{"name":"2019 IEEE International Solid- State Circuits Conference - (ISSCC)","volume":"582 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124697038","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-02-01DOI: 10.1109/ISSCC.2019.8662464
Szu-Yao Hung, S. Pamarti
There is need for a low-power, compact, means of generating multiple, low-jitter, spectrally pure, clock signals at different frequencies using a single reference oscillator, both in wireline and wireless applications, owing to circuit size, cost, and complexity considerations. PLL-based frequency synthesis - analog or digital - can achieve very low jitter and spur levels, but the VCO size and/or power consumption concerns preclude its duplication for multiple on-chip clock generators [1], [2]. Open-loop digital methods based on digital-to-phase or digital-to-time converters (DPCs) are compact and employ no power-hungry oscillators, but their circuit errors and mismatches result in strong spurious tones.
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