Pub Date : 2019-02-01DOI: 10.1109/ISSCC.2019.8662300
S. Otani, N. Otsuki, Yasufumi Suzuki, N. Okumura, Shohei Maeda, T. Yanagita, Takao Koike, Y. Shimazaki, Masao Ito, Minoru Uemura, T. Hattori, T. Yamauchi, H. Kondo
Automotive architecture has been rapidly progressing toward integration and centralization [1]. Integration of multiple electronic control units (ECUs) reduces vehicle weight by deleting the wire harness between ECUs and the cooperative control of multiple functions, resulting in energy savings. The power consumption of automotive MCUs must be single-digit Watts under thermal constraints, and many functions have to be squeezed into one MCU. Adoption of a 28nm process is necessary for speed, power and density, because a conventional 40nm embedded flash process is insufficient on these axes. Furthermore, the integration of ECUs also mixes software components with varying safety integrity levels in one MCU. Resource isolation is inevitable for functional safety to avoid latent faults. In the autonomous driving era, data size and performance requirements will increase owing to the number and complexity of sensors requiring fusion in real time. Fast networks within vehicles are vital. With the evolution of sensor fusion, information centralization, and control decentralization, automotive architectures have been progressing toward increased integration and centralization.
{"title":"2.7 A 28nm 600MHz Automotive Flash Microcontroller with Virtualization-Assisted Processor for Next-Generation Automotive Architecture Complying with ISO26262 ASIL-D","authors":"S. Otani, N. Otsuki, Yasufumi Suzuki, N. Okumura, Shohei Maeda, T. Yanagita, Takao Koike, Y. Shimazaki, Masao Ito, Minoru Uemura, T. Hattori, T. Yamauchi, H. Kondo","doi":"10.1109/ISSCC.2019.8662300","DOIUrl":"https://doi.org/10.1109/ISSCC.2019.8662300","url":null,"abstract":"Automotive architecture has been rapidly progressing toward integration and centralization [1]. Integration of multiple electronic control units (ECUs) reduces vehicle weight by deleting the wire harness between ECUs and the cooperative control of multiple functions, resulting in energy savings. The power consumption of automotive MCUs must be single-digit Watts under thermal constraints, and many functions have to be squeezed into one MCU. Adoption of a 28nm process is necessary for speed, power and density, because a conventional 40nm embedded flash process is insufficient on these axes. Furthermore, the integration of ECUs also mixes software components with varying safety integrity levels in one MCU. Resource isolation is inevitable for functional safety to avoid latent faults. In the autonomous driving era, data size and performance requirements will increase owing to the number and complexity of sensors requiring fusion in real time. Fast networks within vehicles are vital. With the evolution of sensor fusion, information centralization, and control decentralization, automotive architectures have been progressing toward increased integration and centralization.","PeriodicalId":265551,"journal":{"name":"2019 IEEE International Solid- State Circuits Conference - (ISSCC)","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124890311","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-02-01DOI: 10.1109/ISSCC.2019.8662541
H. Inoue, T. Aoki, F. Akasawa, T. Hamada, T. Takeuchi, Kousei Nei, Takako Seki, Y. Yakubo, Kei Takahashi, S. Fukai, T. Ishizu, M. Kozuma, R. Tajima, T. Matsuzaki, T. Ikeda, M. Ikeda, S. Yamazaki
Li-ion batteries are primarily used as power sources in electronic devices and electric vehicles and offer substantial conveniences to consumers. However, fires have broken out likely due to micro short-circuit (also called internal or soft shortcircuit) in Li-ion batteries [1]. The micro short-circuit is a failure mode where Li metal first precipitates on a negative electrode and then reaches a positive electrode; eventually a short-circuit occurs between the negative and positive electrodes and the battery voltage slightly decreases. Repetitive occurrences of micro short-circuit will generate heat and lead to serious accidents with a fire or an explosion in the worst-case scenario. Micro short-circuit detection methods are still in the research phase, and applications of battery voltage monitoring systems with AI are expected [1], [2]. This situation demands urgent research and development of micro short-circuit detectors for battery protection ICs.
{"title":"12.2 Micro Short-Circuit Detector Including S/H Circuit for 1hr Retention and 52dB Comparator Composed of C-Axis Aligned Crystalline IGZO FETs for Li-Ion Battery Protection IC","authors":"H. Inoue, T. Aoki, F. Akasawa, T. Hamada, T. Takeuchi, Kousei Nei, Takako Seki, Y. Yakubo, Kei Takahashi, S. Fukai, T. Ishizu, M. Kozuma, R. Tajima, T. Matsuzaki, T. Ikeda, M. Ikeda, S. Yamazaki","doi":"10.1109/ISSCC.2019.8662541","DOIUrl":"https://doi.org/10.1109/ISSCC.2019.8662541","url":null,"abstract":"Li-ion batteries are primarily used as power sources in electronic devices and electric vehicles and offer substantial conveniences to consumers. However, fires have broken out likely due to micro short-circuit (also called internal or soft shortcircuit) in Li-ion batteries [1]. The micro short-circuit is a failure mode where Li metal first precipitates on a negative electrode and then reaches a positive electrode; eventually a short-circuit occurs between the negative and positive electrodes and the battery voltage slightly decreases. Repetitive occurrences of micro short-circuit will generate heat and lead to serious accidents with a fire or an explosion in the worst-case scenario. Micro short-circuit detection methods are still in the research phase, and applications of battery voltage monitoring systems with AI are expected [1], [2]. This situation demands urgent research and development of micro short-circuit detectors for battery protection ICs.","PeriodicalId":265551,"journal":{"name":"2019 IEEE International Solid- State Circuits Conference - (ISSCC)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128207684","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-02-01DOI: 10.1109/ISSCC.2019.8662456
Shon-Hang Wen, Kuan-Dar Chen, C. Hsiao, Ya-Chi Chen
Three major design issues that arise for high-fidelity audio decoders are: 1) DAC reference noise limiting achievable SNR [1], [2]; 2) THD+N degradation at large output swing [3], [4]; and 3) Distortion arising from limited amplifier loop gain as a consequence of high output load capacitance (CL) [5]. In the first issue, reference noise along with individual DAC cell noise generally limits SNR for a full-scale signal. The use of large device sizes [1], source degeneration [2] and chopping can mitigate 1/f noise, but none are effective for reducing thermal noise. Consequently, either more power or an external bypass capacitor for noise filtering is necessary for reducing DAC reference noise. In the second issue, THD+N of high-output-swing amplifiers degrades proportionally as the output swing increases above 1.6VPP, even with a 4.5V supply [3], [4]. The primary cause of this severe 2nd-order harmonic distortion (HD2) is due to the depletion effect of poly resistors [6]. Lastly, for adequate stability margin, the UGB and loop gain of the conventional nested Miller compensation (NMC) amplifier is restricted by an output limiting pole $(omega _{mathrm{limit}})$ and CL. In [5], a frequency compensation scheme is proposed to push the UGB close to $omega _{mathrm{limit}}$ and enhance the loop gain over the audio band (20Hz to 20kHz) while handling a CL up to 10nF. However, with a CL of 22nF, the amplifier begins to ring for a transient step. In this work, three solutions are presented to solve the aforementioned issues: 1) an area- and power-efficient sample-and-hold (S&H) noise filtering technique is introduced to shape the 1/f and thermal noise of the reference to frequencies below the audio band, thus greatly improving SNR for a full-scale signal; 2) a poly resistor linearization scheme is presented to improve HD2 by mitigating the depletion effect of resistors; and 3) a frequency compensation method for multistage amplifiers is introduced that boosts loop gain and thus enhances amplifier linearity without being limited by large CL. Combining these techniques, the decoder and amplifier achieve -105dBc THD+N (-114dBc HD2) and 120dB DR, and can support a CL up to 22nF.
{"title":"18.1 A -105dBc THD+N (-114dBc HD2) at 2.8VPP Swing and 120dB DR Audio Decoder with Sample-and-Hold Noise Filtering and Poly Resistor Linearization Schemes","authors":"Shon-Hang Wen, Kuan-Dar Chen, C. Hsiao, Ya-Chi Chen","doi":"10.1109/ISSCC.2019.8662456","DOIUrl":"https://doi.org/10.1109/ISSCC.2019.8662456","url":null,"abstract":"Three major design issues that arise for high-fidelity audio decoders are: 1) DAC reference noise limiting achievable SNR [1], [2]; 2) THD+N degradation at large output swing [3], [4]; and 3) Distortion arising from limited amplifier loop gain as a consequence of high output load capacitance (CL) [5]. In the first issue, reference noise along with individual DAC cell noise generally limits SNR for a full-scale signal. The use of large device sizes [1], source degeneration [2] and chopping can mitigate 1/f noise, but none are effective for reducing thermal noise. Consequently, either more power or an external bypass capacitor for noise filtering is necessary for reducing DAC reference noise. In the second issue, THD+N of high-output-swing amplifiers degrades proportionally as the output swing increases above 1.6VPP, even with a 4.5V supply [3], [4]. The primary cause of this severe 2nd-order harmonic distortion (HD2) is due to the depletion effect of poly resistors [6]. Lastly, for adequate stability margin, the UGB and loop gain of the conventional nested Miller compensation (NMC) amplifier is restricted by an output limiting pole $(omega _{mathrm{limit}})$ and CL. In [5], a frequency compensation scheme is proposed to push the UGB close to $omega _{mathrm{limit}}$ and enhance the loop gain over the audio band (20Hz to 20kHz) while handling a CL up to 10nF. However, with a CL of 22nF, the amplifier begins to ring for a transient step. In this work, three solutions are presented to solve the aforementioned issues: 1) an area- and power-efficient sample-and-hold (S&H) noise filtering technique is introduced to shape the 1/f and thermal noise of the reference to frequencies below the audio band, thus greatly improving SNR for a full-scale signal; 2) a poly resistor linearization scheme is presented to improve HD2 by mitigating the depletion effect of resistors; and 3) a frequency compensation method for multistage amplifiers is introduced that boosts loop gain and thus enhances amplifier linearity without being limited by large CL. Combining these techniques, the decoder and amplifier achieve -105dBc THD+N (-114dBc HD2) and 120dB DR, and can support a CL up to 22nF.","PeriodicalId":265551,"journal":{"name":"2019 IEEE International Solid- State Circuits Conference - (ISSCC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129676380","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-02-01DOI: 10.1109/isscc.2019.8662521
{"title":"ISSCC 2019 Index to Authors","authors":"","doi":"10.1109/isscc.2019.8662521","DOIUrl":"https://doi.org/10.1109/isscc.2019.8662521","url":null,"abstract":"","PeriodicalId":265551,"journal":{"name":"2019 IEEE International Solid- State Circuits Conference - (ISSCC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129840852","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-02-01DOI: 10.1109/ISSCC.2019.8662429
Takashi Toi, J. Wadatsumi, Hiroyuki Kobayashi, Yutaka Shimizu, Yuji Satoh, Makoto Morimoto, R. Ito, M. Ashida, Y. Tsubouchi, M. Nozawa, Go Urakawa, J. Deguchi
High-bandwidth (BW) and large-capacity storage systems with NAND Flash memory (hereinafter referred to as “NAND”) have been increasingly required for big data applications, such as the field of advanced biomedical science [1]. However, a conventional NAND interface (I/F), e.g., Toggle DDR, with multi-drop bus topology has a tradeoff between BW and capacity due to the large load capacitance of NAND packages (PKGs). Although increasing the number of parallelized lanes of Toggle DDR improves both BW and capacity, it costs a large number of pins/wires on a controller/PCB. In order to overcome these problems, a daisy-chained serial I/F has been proposed [2]. In the I/F, bridge chips mask large load capacitance of NAND PKGs seen from a controller’s transmitter (TX) so that a 12.8Gb/s downlink is realized. However, the multi-band multiplexing technique employed in [2] has a drawback in the difficulty in implementing an uplink because severe timing control is required for cumulatively multiplexing multiple bands (i.e., channels) in each bridge chip. In order to realize both a downlink and an uplink with lower power consumption, this paper presents a newly developed serial I/F with three key techniques: (1) PAM-4-based 4-channel (4-ch) multiplexing, (2) cascaded CDR circuits in (3) ring topology. The fabricated transceiver (TRX) for the proposed I/F achieves 3.69pJ/b with a BER lower than 10-15 at 25.Gb/s with PRBS31 through 1.84dB of channel loss at 6.4GHz. The proposed I/F can achieve a state-of-the-art FoM (defined as “# of packages × Data Rate / power consumption”) of 1.80PKG.Gb/s/mW.
{"title":"30.3 A 25.6Gb/s Uplink-Downlink Interface Employing PAM-4-Based 4-Channel Multiplexing and Cascaded CDR Circuits in Ring Topology for High-Bandwidth and Large-Capacity Storage Systems","authors":"Takashi Toi, J. Wadatsumi, Hiroyuki Kobayashi, Yutaka Shimizu, Yuji Satoh, Makoto Morimoto, R. Ito, M. Ashida, Y. Tsubouchi, M. Nozawa, Go Urakawa, J. Deguchi","doi":"10.1109/ISSCC.2019.8662429","DOIUrl":"https://doi.org/10.1109/ISSCC.2019.8662429","url":null,"abstract":"High-bandwidth (BW) and large-capacity storage systems with NAND Flash memory (hereinafter referred to as “NAND”) have been increasingly required for big data applications, such as the field of advanced biomedical science [1]. However, a conventional NAND interface (I/F), e.g., Toggle DDR, with multi-drop bus topology has a tradeoff between BW and capacity due to the large load capacitance of NAND packages (PKGs). Although increasing the number of parallelized lanes of Toggle DDR improves both BW and capacity, it costs a large number of pins/wires on a controller/PCB. In order to overcome these problems, a daisy-chained serial I/F has been proposed [2]. In the I/F, bridge chips mask large load capacitance of NAND PKGs seen from a controller’s transmitter (TX) so that a 12.8Gb/s downlink is realized. However, the multi-band multiplexing technique employed in [2] has a drawback in the difficulty in implementing an uplink because severe timing control is required for cumulatively multiplexing multiple bands (i.e., channels) in each bridge chip. In order to realize both a downlink and an uplink with lower power consumption, this paper presents a newly developed serial I/F with three key techniques: (1) PAM-4-based 4-channel (4-ch) multiplexing, (2) cascaded CDR circuits in (3) ring topology. The fabricated transceiver (TRX) for the proposed I/F achieves 3.69pJ/b with a BER lower than 10-15 at 25.Gb/s with PRBS31 through 1.84dB of channel loss at 6.4GHz. The proposed I/F can achieve a state-of-the-art FoM (defined as “# of packages × Data Rate / power consumption”) of 1.80PKG.Gb/s/mW.","PeriodicalId":265551,"journal":{"name":"2019 IEEE International Solid- State Circuits Conference - (ISSCC)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130115736","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-02-01DOI: 10.1109/ISSCC.2019.8662534
S. Kawai, T. Ueno, Kohei Onizuka
Active gate control is an emerging technique to minimize the switching loss of high-power converters facing noise-suppression challenges. In a conventional gate-driver design, a fixed value of gate resistance is chosen by the converter designers so that the slew rate (SR) of the drain voltage Vd, namely $dV_{d}/$dt, does not exceed noise-aware design guidelines in each application and use case. Minimizing the gate resistance leads to high $dV_{d}/$dt and the reduction in switching loss while shortening the turn-on delay for the overall converter performance. However, the impact is limited because of uncontrollable $dV_{d}/$dt drift caused by load-current, temperature, and $mathrm {V}_{th}$ variations of the power transistors. Thus, in practice there is significant room for further loss and turn-on-delay minimization for the active gate control that adaptively modulates gate driving ability within every switching cycle.
{"title":"15.8 A 4.5V/ns Active Slew-Rate-Controlling Gate Driver with Robust Discrete-Time Feedback Technique for 600V Superjunction MOSFETs","authors":"S. Kawai, T. Ueno, Kohei Onizuka","doi":"10.1109/ISSCC.2019.8662534","DOIUrl":"https://doi.org/10.1109/ISSCC.2019.8662534","url":null,"abstract":"Active gate control is an emerging technique to minimize the switching loss of high-power converters facing noise-suppression challenges. In a conventional gate-driver design, a fixed value of gate resistance is chosen by the converter designers so that the slew rate (SR) of the drain voltage Vd, namely $dV_{d}/$dt, does not exceed noise-aware design guidelines in each application and use case. Minimizing the gate resistance leads to high $dV_{d}/$dt and the reduction in switching loss while shortening the turn-on delay for the overall converter performance. However, the impact is limited because of uncontrollable $dV_{d}/$dt drift caused by load-current, temperature, and $mathrm {V}_{th}$ variations of the power transistors. Thus, in practice there is significant room for further loss and turn-on-delay minimization for the active gate control that adaptively modulates gate driving ability within every switching cycle.","PeriodicalId":265551,"journal":{"name":"2019 IEEE International Solid- State Circuits Conference - (ISSCC)","volume":"65 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130121112","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-02-01DOI: 10.1109/ISSCC.2019.8662401
Silvester Sadjina, K. Dufrêne, R. S. Kanumalli, M. Huemer, H. Pretl
To enable high data-rates in mobile communications the LTE standard has implemented carrier aggregation (CA) to increase channel bandwidth. Several local oscillator (LO) signals are needed to drive a multitude of mixers to receive from a number of LTE bands in the different CA scenarios. Due to device nonlinearities in the LO signal distribution and cross-talk between LO paths spurs are generated inside the transceiver chip which may downconvert interfering signals located at the spurious frequencies into the receiver baseband (Fig. 21.7.1). These unwanted signals could either be the transceiver’s own transmit signal when operating in frequency-division duplex (FDD), or external signals received by the antenna. An interferer downconverted by an RX LO-LO spur is referred to as a modulated spur and causes severe degradation of the signal-to-noise-and-distortion ratio (SNDR) of the desired signal.
{"title":"21.7 A Mixed-Signal Circuit Technique for Cancellation of Multiple Modulated Spurs in 4G/5G Carrier-Aggregation Transceivers","authors":"Silvester Sadjina, K. Dufrêne, R. S. Kanumalli, M. Huemer, H. Pretl","doi":"10.1109/ISSCC.2019.8662401","DOIUrl":"https://doi.org/10.1109/ISSCC.2019.8662401","url":null,"abstract":"To enable high data-rates in mobile communications the LTE standard has implemented carrier aggregation (CA) to increase channel bandwidth. Several local oscillator (LO) signals are needed to drive a multitude of mixers to receive from a number of LTE bands in the different CA scenarios. Due to device nonlinearities in the LO signal distribution and cross-talk between LO paths spurs are generated inside the transceiver chip which may downconvert interfering signals located at the spurious frequencies into the receiver baseband (Fig. 21.7.1). These unwanted signals could either be the transceiver’s own transmit signal when operating in frequency-division duplex (FDD), or external signals received by the antenna. An interferer downconverted by an RX LO-LO spur is referred to as a modulated spur and causes severe degradation of the signal-to-noise-and-distortion ratio (SNDR) of the desired signal.","PeriodicalId":265551,"journal":{"name":"2019 IEEE International Solid- State Circuits Conference - (ISSCC)","volume":"21 43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129096334","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-02-01DOI: 10.1109/isscc.2019.8662347
Digital Circuits Subcommittee
In this session, seven papers highlight developments in machine learning and digital low-dropout (LDO) linear regulators. The papers demonstrate a hybrid digital and mixed-signal computing platform for swarm robotics, bi-directional memory delay lines to perform time-domain MAC operations, hybrid in-/near-memory compute SRAM and resistive RAM for/with resilience techniques. The digital LDO papers present a computational regulation scheme, a sub-nA wide-dynamic-range implementation and a universal modular hybrid LDO in 14nm CMOS. Session Chair: Vivek De Intel, Beaverton, OR Associate Chair: Ping-Ying Wang CMOS-Crystal Technology, Zhubei City, Hsinchu County, Taiwan
在本次会议上，七篇论文重点介绍了机器学习和数字低差(LDO)线性稳压器的发展。论文展示了用于群体机器人的混合数字和混合信号计算平台，用于执行时域MAC操作的双向存储器延迟线，用于/具有弹性技术的混合内/近存储器计算SRAM和电阻性RAM。数字LDO论文提出了一个计算调节方案，一个亚na宽动态范围实现和一个通用模块化混合LDO在14nm CMOS。会议主席:Vivek De Intel, Beaverton, OR副主席:Wang Ping-Ying - crystal Technology, Zhubei City, sinchu County, Taiwan
{"title":"ISSCC 2019 Session 14 Overview: Machine Learning and Digital LDO Circuits","authors":"Digital Circuits Subcommittee","doi":"10.1109/isscc.2019.8662347","DOIUrl":"https://doi.org/10.1109/isscc.2019.8662347","url":null,"abstract":"In this session, seven papers highlight developments in machine learning and digital low-dropout (LDO) linear regulators. The papers demonstrate a hybrid digital and mixed-signal computing platform for swarm robotics, bi-directional memory delay lines to perform time-domain MAC operations, hybrid in-/near-memory compute SRAM and resistive RAM for/with resilience techniques. The digital LDO papers present a computational regulation scheme, a sub-nA wide-dynamic-range implementation and a universal modular hybrid LDO in 14nm CMOS. Session Chair: Vivek De Intel, Beaverton, OR Associate Chair: Ping-Ying Wang CMOS-Crystal Technology, Zhubei City, Hsinchu County, Taiwan","PeriodicalId":265551,"journal":{"name":"2019 IEEE International Solid- State Circuits Conference - (ISSCC)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132900555","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-02-01DOI: 10.1109/ISSCC.2019.8662340
Zhengyu Chen, Jie Gu
Dynamic time warping (DTW), a variant of the dynamic programming algorithm, is widely used for time series classification [1]. Its strong capability for distance measurement for variable-speed temporal sequences makes DTW a popular method for time-series classification in broad applications, such as ECG diagnosis, motion detection, DNA sequencing, etc. [1]. Several efforts have proposed for accelerating the operation of DTW, including a recent demonstration of time-based design in DNA sequencing [2]. However, the demonstration was confined to single-bit operations, a fixed sequence length and low throughput due to nonpipelined operation and a large single-bit delay. To overcome such challenges, this work presents a general-purpose DTW engine for time-series classification using time-domain computing. Pipelined operation is enabled by a time flip-flop (TFF) leading to order-of-magnitude improvements in throughput and a scalable processing capability for time series. Compared with recent time-domain designs, which do not have time-domain memory elements, this work realizes a time-domain pipelined architecture [3].
动态时间规整(Dynamic time warping, DTW)是动态规划算法的一种变体，被广泛用于时间序列分类[1]。DTW对变速时间序列具有较强的距离测量能力，在心电图诊断、运动检测、DNA测序等广泛应用中成为时间序列分类的常用方法[1]。已经提出了一些加速DTW操作的努力，包括最近在DNA测序中基于时间的设计的演示[2]。然而，该演示仅限于单比特操作、固定的序列长度、由于非流水线操作和大的单比特延迟而导致的低吞吐量。为了克服这些挑战，本工作提出了一种通用的DTW引擎，用于使用时域计算进行时间序列分类。通过时间触发器(TFF)实现流水线操作，从而提高吞吐量和时间序列的可扩展处理能力。与最近没有时域存储元件的时域设计相比，本工作实现了时域流水线架构[3]。
{"title":"19.7 A Scalable Pipelined Time-Domain DTW Engine for Time-Series Classification Using Multibit Time Flip-Flops With 140Giga-Cell-Updates/s Throughput","authors":"Zhengyu Chen, Jie Gu","doi":"10.1109/ISSCC.2019.8662340","DOIUrl":"https://doi.org/10.1109/ISSCC.2019.8662340","url":null,"abstract":"Dynamic time warping (DTW), a variant of the dynamic programming algorithm, is widely used for time series classification [1]. Its strong capability for distance measurement for variable-speed temporal sequences makes DTW a popular method for time-series classification in broad applications, such as ECG diagnosis, motion detection, DNA sequencing, etc. [1]. Several efforts have proposed for accelerating the operation of DTW, including a recent demonstration of time-based design in DNA sequencing [2]. However, the demonstration was confined to single-bit operations, a fixed sequence length and low throughput due to nonpipelined operation and a large single-bit delay. To overcome such challenges, this work presents a general-purpose DTW engine for time-series classification using time-domain computing. Pipelined operation is enabled by a time flip-flop (TFF) leading to order-of-magnitude improvements in throughput and a scalable processing capability for time series. Compared with recent time-domain designs, which do not have time-domain memory elements, this work realizes a time-domain pipelined architecture [3].","PeriodicalId":265551,"journal":{"name":"2019 IEEE International Solid- State Circuits Conference - (ISSCC)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130931347","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-02-01DOI: 10.1109/ISSCC.2019.8662314
Sangyeop Lee, R. Dong, T. Yoshida, S. Amakawa, S. Hara, A. Kasamatsu, J. Sato, M. Fujishima
IEEE Standard 802.15.3d, published in October 2017, defines a high-data-rate wireless physical layer that enables up to 100Gb/s using the lower THz frequency range between 252 and 325GHz (hereafter referred to as the “300GHz band”). It stipulates that the 300GHz band be channelized into thirty-two 2.16GHz-wide channels (Fig. 9.5.1) or a smaller number of wider channels whose bandwidths are all integer multiples of 2.16GHz. This paper presents a CMOS transceiver (TRX) chip targeted at channels 49 through 51 and 66 of 802.15.3d (Fig. 9.5.1). The TRX was fabricated using a 40nm CMOS process. There have been reports on solid-state transceivers (TRXs) operating in or near the 300GHz band [1]–[6]. Some of these [1]–[3] were TX/RX or block-level chipsets, which can enjoy more flexibility in design and independent optimization of TX and RX. They successfully achieved $geq 64$ Gb/s. On the other hand, single-chip TRXs [4]–[6] did not always reveal achievable data-rates nor were capable of supporting quadrature amplitude modulation (QAM). Nevertheless, eventual development of full-featured single-chip TRXs is desirable especially for applications requiring deployment of many TRXs, as is envisioned implicitly by 802.15.3d. The single-chip QAM-capable CMOS TRX presented herein is an outcome of efforts in that direction.
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