Pub Date : 2019-02-01DOI: 10.1109/ISSCC.2019.8662338
B. Verhoef, J. Prummel, W. Kruiskamp, R. Post
Low-power sensor nodes (e.g., Bluetooth Low Energy, BLE) use low duty-cycle transceivers to obtain an overall low power consumption. The system typically spends most of the time in a low-power sleep state and only briefly wakes up to transmit and receive data. Due to the high Q (>100k) of the crystal resonator the start-up time of a typical crystal oscillator is relatively long ($approx 0.5$ to 5ms) which causes a substantial amount of energy to be consumed by the crystal oscillator in a transmit/receive event. As the system usually is in an active state when the crystal oscillator ramps up (multiple sub-systems are powered up) not only should the start-up energy of the crystal oscillator be optimized, but also the startup time. As the crystal resonator is one of the most costly components in IoT sensor nodes, a wide range of crystal resonators should be supported by the circuit. This work proposes a synchronized signal injection (SSI) start-up mechanism that can drive the crystal up to any amplitude in a minimum amount of time, does not require a high-precision RC oscillator, is insensitive to PTV and is effective for a wide range of crystals: the technique does not require the shunt capacitance or the load capacitance to be small. A programmable capacitor-bank is included to support a range of crystals (load-capacitance) and allow for the customer to calibrate the frequency but is not required for the SSI technique.
{"title":"18.6 A 32MHz Crystal Oscillator with Fast Start-up Using Synchronized Signal Injection","authors":"B. Verhoef, J. Prummel, W. Kruiskamp, R. Post","doi":"10.1109/ISSCC.2019.8662338","DOIUrl":"https://doi.org/10.1109/ISSCC.2019.8662338","url":null,"abstract":"Low-power sensor nodes (e.g., Bluetooth Low Energy, BLE) use low duty-cycle transceivers to obtain an overall low power consumption. The system typically spends most of the time in a low-power sleep state and only briefly wakes up to transmit and receive data. Due to the high Q (>100k) of the crystal resonator the start-up time of a typical crystal oscillator is relatively long ($approx 0.5$ to 5ms) which causes a substantial amount of energy to be consumed by the crystal oscillator in a transmit/receive event. As the system usually is in an active state when the crystal oscillator ramps up (multiple sub-systems are powered up) not only should the start-up energy of the crystal oscillator be optimized, but also the startup time. As the crystal resonator is one of the most costly components in IoT sensor nodes, a wide range of crystal resonators should be supported by the circuit. This work proposes a synchronized signal injection (SSI) start-up mechanism that can drive the crystal up to any amplitude in a minimum amount of time, does not require a high-precision RC oscillator, is insensitive to PTV and is effective for a wide range of crystals: the technique does not require the shunt capacitance or the load capacitance to be small. A programmable capacitor-bank is included to support a range of crystals (load-capacitance) and allow for the customer to calibrate the frequency but is not required for the SSI technique.","PeriodicalId":265551,"journal":{"name":"2019 IEEE International Solid- State Circuits Conference - (ISSCC)","volume":"93 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127954519","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-02-01DOI: 10.1109/ISSCC.2019.8662405
Y. Hirose, S. Koyama, T. Okino, Akito Inoue, S. Saito, Yugo Nose, M. Ishii, S. Yamahira, S. Kasuga, M. Mori, T. Kabe, K. Nakanishi, M. Usuda, A. Odagawa, Tsuyoshi Tanaka
The intensive development of Single-photon avalanche photodiode (SPAD) based CMOS image sensors (CIS) continues, with rapid progress [1–6]. Yet, due to unestablished quenching operation [5,6], realization of SPADs onto a CIS alongside conventional pixel circuitry has been a fundamental challenge.
{"title":"5.6 A 400×400-Pixel 6μm-Pitch Vertical Avalanche Photodiodes CMOS Image Sensor Based on 150ps-Fast Capacitive Relaxation Quenching in Geiger Mode for Synthesis of Arbitrary Gain Images","authors":"Y. Hirose, S. Koyama, T. Okino, Akito Inoue, S. Saito, Yugo Nose, M. Ishii, S. Yamahira, S. Kasuga, M. Mori, T. Kabe, K. Nakanishi, M. Usuda, A. Odagawa, Tsuyoshi Tanaka","doi":"10.1109/ISSCC.2019.8662405","DOIUrl":"https://doi.org/10.1109/ISSCC.2019.8662405","url":null,"abstract":"The intensive development of Single-photon avalanche photodiode (SPAD) based CMOS image sensors (CIS) continues, with rapid progress [1–6]. Yet, due to unestablished quenching operation [5,6], realization of SPADs onto a CIS alongside conventional pixel circuitry has been a fundamental challenge.","PeriodicalId":265551,"journal":{"name":"2019 IEEE International Solid- State Circuits Conference - (ISSCC)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121602879","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-02-01DOI: 10.1109/ISSCC.2019.8662495
A. Cevrero, Ilter Özkaya, P. Francese, M. Brändli, C. Menolfi, T. Morf, M. Kossel, L. Kull, D. Luu, M. Dazzi, T. Toifl
The growing demand for higher data rates in wireline communications has led to emerging standards in the 100Gb/s+ range using PAM-4 signaling. ADC-based receivers have demonstrated robust operation over channels with high losses $(gt20$ dB) [1], but their power consumption $(gt500$ mW/lane excluding DSP) is prohibitive for applications requiring large port counts in short-reach chip-to-chip and chip-to-module links (such as OIF-CEI-112G-VSR/XSR/USR). This work demonstrates a dual PAM-4/NRZ RX implemented in 14nm FinFET and measured up to 100Gb/s in PAM-4 mode achieving pre-FEC BER $lt 10^{-12}$ across a 19.2dB-loss channel with low power. To achieve low BER with $gt16$ dB loss channel the RX uses a CTLE combined with a 1-tap speculative DFE. To minimize power consumption, the number of slicing levels to resolve the 1-tap PAM-4 DFE speculation is reduced from 12 to 8 by shaping the channel to a1 +0.5D response (h 0 +0.5 $ast$ h0) with CTLE and TXFFE. With a1 +0.5D channel, 4 out of 12 speculative decisions are overlapped. Moreover, comparators used for DFE speculation can be shared for phase detection in a baud-rate CDR scheme, extending the concept proposed in [2] to PAM-4. In NRZ mode, the RX features a fully speculative 3-tap DFE to equalize high loss channels $(gt35$ dB) at 56Gb/s. The RX incorporates the following key advances: (1) a trans-admittance trans-impedance (TAS-TIS) CTLE circuit resulting in a low-power and compact analog-front-end (AFE), (2) a 1-tap PAM-4 speculative DFE based on a1 +0.5D response, and (3) a CMOS quadrature-DLL (QDLL) generating quadrature clock phases resulting in a low jitter/power clock path.
{"title":"6.1 A 100Gb/s 1.1pJ/b PAM-4 RX with Dual-Mode 1-Tap PAM-4 / 3-Tap NRZ Speculative DFE in 14nm CMOS FinFET","authors":"A. Cevrero, Ilter Özkaya, P. Francese, M. Brändli, C. Menolfi, T. Morf, M. Kossel, L. Kull, D. Luu, M. Dazzi, T. Toifl","doi":"10.1109/ISSCC.2019.8662495","DOIUrl":"https://doi.org/10.1109/ISSCC.2019.8662495","url":null,"abstract":"The growing demand for higher data rates in wireline communications has led to emerging standards in the 100Gb/s+ range using PAM-4 signaling. ADC-based receivers have demonstrated robust operation over channels with high losses $(gt20$ dB) [1], but their power consumption $(gt500$ mW/lane excluding DSP) is prohibitive for applications requiring large port counts in short-reach chip-to-chip and chip-to-module links (such as OIF-CEI-112G-VSR/XSR/USR). This work demonstrates a dual PAM-4/NRZ RX implemented in 14nm FinFET and measured up to 100Gb/s in PAM-4 mode achieving pre-FEC BER $lt 10^{-12}$ across a 19.2dB-loss channel with low power. To achieve low BER with $gt16$ dB loss channel the RX uses a CTLE combined with a 1-tap speculative DFE. To minimize power consumption, the number of slicing levels to resolve the 1-tap PAM-4 DFE speculation is reduced from 12 to 8 by shaping the channel to a1 +0.5D response (h 0 +0.5 $ast$ h0) with CTLE and TXFFE. With a1 +0.5D channel, 4 out of 12 speculative decisions are overlapped. Moreover, comparators used for DFE speculation can be shared for phase detection in a baud-rate CDR scheme, extending the concept proposed in [2] to PAM-4. In NRZ mode, the RX features a fully speculative 3-tap DFE to equalize high loss channels $(gt35$ dB) at 56Gb/s. The RX incorporates the following key advances: (1) a trans-admittance trans-impedance (TAS-TIS) CTLE circuit resulting in a low-power and compact analog-front-end (AFE), (2) a 1-tap PAM-4 speculative DFE based on a1 +0.5D response, and (3) a CMOS quadrature-DLL (QDLL) generating quadrature clock phases resulting in a low jitter/power clock path.","PeriodicalId":265551,"journal":{"name":"2019 IEEE International Solid- State Circuits Conference - (ISSCC)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133010491","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-02-01DOI: 10.1109/ISSCC.2019.8662488
Fei Song, Yu Zhao, Bart Wu, L. Tang, Leon Lin, B. Razavi
The next-generation 802.11ax WLAN standard improves the throughput by supporting 1024-QAM in a channel bandwidth of 160MHz, demanding extremely low jitter values for the transmitter (Tx) and the receiver (Rx) synthesizers. Recent work has achieved rms jitter below 200fs [1]–[4] with the latest rms jitter reported at 75fs [5]. The work in [5] faces a number of challenges if applied to 802.11ax: (1) with a VCO frequency of 5.7 to 7.3GHz, the circuit is prone to pulling by the PA, especially because it incorporates a single spiral inductor (rather than an 8shaped inductor); (2) it does not provide quadrature outputs, and (3) it relies on a 10b digital-to-time converter (DTC) without calibration of its nonlinearity, which folds high-frequency $Delta Sigma-text { modulator } (Delta Sigma M)$ noise unless extremely tight matching is guaranteed. Similarly, the design in [2] is prone to pulling as well.
{"title":"16.5 A Fractional-N Synthesizer with 110fsrms Jitter and a Reference Quadrupler for Wideband 802.11ax","authors":"Fei Song, Yu Zhao, Bart Wu, L. Tang, Leon Lin, B. Razavi","doi":"10.1109/ISSCC.2019.8662488","DOIUrl":"https://doi.org/10.1109/ISSCC.2019.8662488","url":null,"abstract":"The next-generation 802.11ax WLAN standard improves the throughput by supporting 1024-QAM in a channel bandwidth of 160MHz, demanding extremely low jitter values for the transmitter (Tx) and the receiver (Rx) synthesizers. Recent work has achieved rms jitter below 200fs [1]–[4] with the latest rms jitter reported at 75fs [5]. The work in [5] faces a number of challenges if applied to 802.11ax: (1) with a VCO frequency of 5.7 to 7.3GHz, the circuit is prone to pulling by the PA, especially because it incorporates a single spiral inductor (rather than an 8shaped inductor); (2) it does not provide quadrature outputs, and (3) it relies on a 10b digital-to-time converter (DTC) without calibration of its nonlinearity, which folds high-frequency $Delta Sigma-text { modulator } (Delta Sigma M)$ noise unless extremely tight matching is guaranteed. Similarly, the design in [2] is prone to pulling as well.","PeriodicalId":265551,"journal":{"name":"2019 IEEE International Solid- State Circuits Conference - (ISSCC)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132447340","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-02-01DOI: 10.1109/isscc.2019.8662513
Wireless Subcommittee
Wireless technologies continue to penetrate and support a wide range of application areas. This session includes state-of-the-art improvements in wake-up radios enabling ultra-low-power and increased blocker rejection, a highly efficient Bluetooth Low Energy transmitter, and a wireless power transfer system supporting enhanced data rates. Furthermore techniques to boost wireless performance are presented, including non-magnetic circulators for improved full-duplex communications at mm-wave and RF frequencies, a wideband blocker-tolerant receiver with low LO leakage and a modified Cartesian feedback transmitter that addresses the noise-linearity trade-off of the conventional architecture. Session Chair: Danielle Griffith Texas Instruments, Dallas, TX Associate Chair: Alan Wong EnSilica, Abingdon, United Kingdom
无线技术不断渗透并支持广泛的应用领域。本次会议包括最先进的唤醒无线电的改进，支持超低功耗和增加阻塞抑制，高效的蓝牙低能量发射器，以及支持增强数据速率的无线电力传输系统。此外，还介绍了提高无线性能的技术，包括用于改进毫米波和RF频率下全双工通信的非磁性环行器，具有低LO泄漏的宽带抗干扰接收器和改进的笛卡尔反馈发射器，该发射器解决了传统架构的噪声线性权衡。会议主席:Danielle Griffith Texas Instruments, Dallas, TX副主席:Alan Wong EnSilica, Abingdon，英国
{"title":"ISSCC 2019 Session 28 Overview: Techniques for Low-Power & High-Performance Wireless","authors":"Wireless Subcommittee","doi":"10.1109/isscc.2019.8662513","DOIUrl":"https://doi.org/10.1109/isscc.2019.8662513","url":null,"abstract":"Wireless technologies continue to penetrate and support a wide range of application areas. This session includes state-of-the-art improvements in wake-up radios enabling ultra-low-power and increased blocker rejection, a highly efficient Bluetooth Low Energy transmitter, and a wireless power transfer system supporting enhanced data rates. Furthermore techniques to boost wireless performance are presented, including non-magnetic circulators for improved full-duplex communications at mm-wave and RF frequencies, a wideband blocker-tolerant receiver with low LO leakage and a modified Cartesian feedback transmitter that addresses the noise-linearity trade-off of the conventional architecture. Session Chair: Danielle Griffith Texas Instruments, Dallas, TX Associate Chair: Alan Wong EnSilica, Abingdon, United Kingdom","PeriodicalId":265551,"journal":{"name":"2019 IEEE International Solid- State Circuits Conference - (ISSCC)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131903802","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-02-01DOI: 10.1109/ISSCC.2019.8662432
Casey Hardy, Hanh-Phuc Le
The annual increase in performance and feature density of mobile products has driven the need for batteries with higher capacity and thus higher power-delivery solutions to maintain sensible charging times. The USB-C power-delivery specification was developed to meet these higher demands by enabling the input supply VBUS voltage at a higher setting, e.g., 9V, to allow higher power delivery, up to 100W, while minimizing current levels and associated IR drops across the USB-C cable. To bridge the increased gap from this input voltage to charge one-and two-cell battery products, a power-and space-efficient DC-DC converter is desirable.
{"title":"8.3 A 10.9W 93.4%-Efficient (27W 97%-Efficient) Flying-Inductor Hybrid DC-DC Converter Suitable for 1-Cell (2-Cell) Battery Charging Applications","authors":"Casey Hardy, Hanh-Phuc Le","doi":"10.1109/ISSCC.2019.8662432","DOIUrl":"https://doi.org/10.1109/ISSCC.2019.8662432","url":null,"abstract":"The annual increase in performance and feature density of mobile products has driven the need for batteries with higher capacity and thus higher power-delivery solutions to maintain sensible charging times. The USB-C power-delivery specification was developed to meet these higher demands by enabling the input supply VBUS voltage at a higher setting, e.g., 9V, to allow higher power delivery, up to 100W, while minimizing current levels and associated IR drops across the USB-C cable. To bridge the increased gap from this input voltage to charge one-and two-cell battery products, a power-and space-efficient DC-DC converter is desirable.","PeriodicalId":265551,"journal":{"name":"2019 IEEE International Solid- State Circuits Conference - (ISSCC)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114367975","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-02-01DOI: 10.1109/ISSCC.2019.8662489
C. Hung, A. Lin, B. Peng, Hua Wang, Jui-Lin Hsu, Yen-Ju Lu, W. Hsu, J. Zhan, B. Juan, Chi-Hang Lok, Sam Lee, P. Hsiao, Qiang Zhou, Mark Wei, H. Chu, Yu-Lun Chen, Chao-Ching Hung, K. Fong, Po-Chun Huang, Pi-Chiao Chen, Sheng-Yuan Su, Yan-Jiun Chen, Kehou Chen, C. Tung, Yibin Hsieh, Tzung-Chuen Tsai, Yi-fu Chen, W. Hsin, Liang Guo, Hanfei Liu, D. Jin
The future of driving extends from physical mobility and enjoyment today to having more services enabled by wireless connectivity, clean and green technologies, secure transactions, and so forth. Whether the ownership is based on physical vehicles or services, or whether the drivers are human or robots, one demand that will never change is to have better safety at affordable cost. Among available sensor technologies for the advanced-driver-assistance-system (ADAS), radar is indispensable due to its unique capability in robustness against environmental impacts, long-range detection, sufficient range resolution, and simultaneous multi-depth detection. Those are very crucial since camera, Lidar and ultrasonic sensors perform poorly under severe weather conditions, and an autonomous vehicle would become partially blinded without radars. There are several automotive radar applications such as front radars responsible for autonomous cruise control and automatic emergency braking, as well as corner radars responsible for blind-spot detection (BSD), cross-traffic alert (CTA), and the like. A new class of applications comprehending ultra-short range sensing and 360° surround view for parking assistance, door-opening alert, etc. is emerging. In this paper, requirements of the new applications will be examined, which will be further broken into system and circuit specification. A new system including application-driven algorithm, hardware and software designs will be presented to fulfill the new demands.
{"title":"9.1 Toward Automotive Surround-View Radars","authors":"C. Hung, A. Lin, B. Peng, Hua Wang, Jui-Lin Hsu, Yen-Ju Lu, W. Hsu, J. Zhan, B. Juan, Chi-Hang Lok, Sam Lee, P. Hsiao, Qiang Zhou, Mark Wei, H. Chu, Yu-Lun Chen, Chao-Ching Hung, K. Fong, Po-Chun Huang, Pi-Chiao Chen, Sheng-Yuan Su, Yan-Jiun Chen, Kehou Chen, C. Tung, Yibin Hsieh, Tzung-Chuen Tsai, Yi-fu Chen, W. Hsin, Liang Guo, Hanfei Liu, D. Jin","doi":"10.1109/ISSCC.2019.8662489","DOIUrl":"https://doi.org/10.1109/ISSCC.2019.8662489","url":null,"abstract":"The future of driving extends from physical mobility and enjoyment today to having more services enabled by wireless connectivity, clean and green technologies, secure transactions, and so forth. Whether the ownership is based on physical vehicles or services, or whether the drivers are human or robots, one demand that will never change is to have better safety at affordable cost. Among available sensor technologies for the advanced-driver-assistance-system (ADAS), radar is indispensable due to its unique capability in robustness against environmental impacts, long-range detection, sufficient range resolution, and simultaneous multi-depth detection. Those are very crucial since camera, Lidar and ultrasonic sensors perform poorly under severe weather conditions, and an autonomous vehicle would become partially blinded without radars. There are several automotive radar applications such as front radars responsible for autonomous cruise control and automatic emergency braking, as well as corner radars responsible for blind-spot detection (BSD), cross-traffic alert (CTA), and the like. A new class of applications comprehending ultra-short range sensing and 360° surround view for parking assistance, door-opening alert, etc. is emerging. In this paper, requirements of the new applications will be examined, which will be further broken into system and circuit specification. A new system including application-driven algorithm, hardware and software designs will be presented to fulfill the new demands.","PeriodicalId":265551,"journal":{"name":"2019 IEEE International Solid- State Circuits Conference - (ISSCC)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115998777","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-02-01DOI: 10.1109/ISSCC.2019.8662402
Tony F. Wu, B. Le, R. Radway, Andrew Bartolo, William Hwang, Seung-Kook Jeong, Haitong Li, Pulkit Tandon, E. Vianello, P. Vivet, E. Nowak, Mary Wootters, H. Wong, M. Aly, E. Beigné, S. Mitra
Non-volatility is emerging as an essential on-chip memory characteristic across a wide range of application domains, from edge nodes for the Internet of Things (IoT) to large computing clusters. On-chip non-volatile memory (NVM) is critical for low-energy operation, real-time responses, privacy and security, operation in unpredictable environments, and fault-tolerance [1]. Existing on-chip NVMs (e.g., Flash, FRAM, EEPROM) suffer from high read/write energy/latency, density, and integration challenges [1]. For example, an ideal IoT edge system would employ fine-grained temporal power gating (i.e., shutdown) between active modes. However, existing on-chip Flash can have long latencies (> 23 ms latency for erase followed by write), while inter-sample arrival times can be short (e.g., 2ms in [2]).
{"title":"14.3 A 43pJ/Cycle Non-Volatile Microcontroller with 4.7μs Shutdown/Wake-up Integrating 2.3-bit/Cell Resistive RAM and Resilience Techniques","authors":"Tony F. Wu, B. Le, R. Radway, Andrew Bartolo, William Hwang, Seung-Kook Jeong, Haitong Li, Pulkit Tandon, E. Vianello, P. Vivet, E. Nowak, Mary Wootters, H. Wong, M. Aly, E. Beigné, S. Mitra","doi":"10.1109/ISSCC.2019.8662402","DOIUrl":"https://doi.org/10.1109/ISSCC.2019.8662402","url":null,"abstract":"Non-volatility is emerging as an essential on-chip memory characteristic across a wide range of application domains, from edge nodes for the Internet of Things (IoT) to large computing clusters. On-chip non-volatile memory (NVM) is critical for low-energy operation, real-time responses, privacy and security, operation in unpredictable environments, and fault-tolerance [1]. Existing on-chip NVMs (e.g., Flash, FRAM, EEPROM) suffer from high read/write energy/latency, density, and integration challenges [1]. For example, an ideal IoT edge system would employ fine-grained temporal power gating (i.e., shutdown) between active modes. However, existing on-chip Flash can have long latencies (> 23 ms latency for erase followed by write), while inter-sample arrival times can be short (e.g., 2ms in [2]).","PeriodicalId":265551,"journal":{"name":"2019 IEEE International Solid- State Circuits Conference - (ISSCC)","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124097567","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-02-01DOI: 10.1109/ISSCC.2019.8662441
Chen Xu, Y. Mo, Guanjing Ren, Weijian Ma, Xin Wang, Wenjie Shi, Ji-Ling Hou, Ke Shao, Haojie Wang, P. Xiao, Zexu Shao, Xiao Xie, Xiaoyong Wang, C. Yiu
Request for smart vision related applications, such as face identification, VR/AR, gesture recognition, 3D imaging, and artificial intelligence (AI), has driven demand for high-performance global-shutter (GS) sensors. Most commercially available GS sensors use a charge-domain storage gate implementation, which suffers from serious light leakage and leads to lower shutter efficiency. This situation worsens when using a BSI fabrication process [1]. In addition, the traditional frame-based or line-based HDR method utilizing multiple exposures adds motion artifact to fast-moving objects, which defeats the purpose of having a global shutter. Moreover, some smart vision applications such as QR 2D barcode scanners and 3D facial recognition with structured light method need image sensors to “read” a certain pattern and “understand” the information within. However, image sensors usually capture a full image that needs to be further transferred to and processed by a companion SoC. Higher resolution and increased complexity of the target pattern pose a growing challenge to transfer and process the entire image at real time, also the required high power consumption lowers handheld device’s battery life.
{"title":"5.1 A Stacked Global-Shutter CMOS Imager with SC-Type Hybrid-GS Pixel and Self-Knee Point Calibration Single Frame HDR and On-Chip Binarization Algorithm for Smart Vision Applications","authors":"Chen Xu, Y. Mo, Guanjing Ren, Weijian Ma, Xin Wang, Wenjie Shi, Ji-Ling Hou, Ke Shao, Haojie Wang, P. Xiao, Zexu Shao, Xiao Xie, Xiaoyong Wang, C. Yiu","doi":"10.1109/ISSCC.2019.8662441","DOIUrl":"https://doi.org/10.1109/ISSCC.2019.8662441","url":null,"abstract":"Request for smart vision related applications, such as face identification, VR/AR, gesture recognition, 3D imaging, and artificial intelligence (AI), has driven demand for high-performance global-shutter (GS) sensors. Most commercially available GS sensors use a charge-domain storage gate implementation, which suffers from serious light leakage and leads to lower shutter efficiency. This situation worsens when using a BSI fabrication process [1]. In addition, the traditional frame-based or line-based HDR method utilizing multiple exposures adds motion artifact to fast-moving objects, which defeats the purpose of having a global shutter. Moreover, some smart vision applications such as QR 2D barcode scanners and 3D facial recognition with structured light method need image sensors to “read” a certain pattern and “understand” the information within. However, image sensors usually capture a full image that needs to be further transferred to and processed by a companion SoC. Higher resolution and increased complexity of the target pattern pose a growing challenge to transfer and process the entire image at real time, also the required high power consumption lowers handheld device’s battery life.","PeriodicalId":265551,"journal":{"name":"2019 IEEE International Solid- State Circuits Conference - (ISSCC)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124498750","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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