Pub Date : 2003-07-07DOI: 10.1109/IPFA.2003.1222759
K. Manjularani, V. Ramgopal Rao, J. Vasi
In this paper, we study the reliability of n-channel Metal-Nitride-Silicon FETs fabricated using ultrathin Jet Vapor Deposited (JVD) Silicon Nitride gate dielectric under constant voltage stressing. Due to the stress, shifts in threshold voltage and transconductance as well as interface state generation are observed. Our study shows that degradation is polarity dependent. MNSFETs show lower degradation when the applied stress voltage is positive. We have also compared the performance of MNSFETs with conventional MOSFETs under identical stress conditions. Under positive stressing, MNSFETs clearly outperform the MOSFETs but under negative stressing MNSFETs show more degradation.
{"title":"Reliability of ultrathin JVD silicon nitride MNSFETs under high field stressing","authors":"K. Manjularani, V. Ramgopal Rao, J. Vasi","doi":"10.1109/IPFA.2003.1222759","DOIUrl":"https://doi.org/10.1109/IPFA.2003.1222759","url":null,"abstract":"In this paper, we study the reliability of n-channel Metal-Nitride-Silicon FETs fabricated using ultrathin Jet Vapor Deposited (JVD) Silicon Nitride gate dielectric under constant voltage stressing. Due to the stress, shifts in threshold voltage and transconductance as well as interface state generation are observed. Our study shows that degradation is polarity dependent. MNSFETs show lower degradation when the applied stress voltage is positive. We have also compared the performance of MNSFETs with conventional MOSFETs under identical stress conditions. Under positive stressing, MNSFETs clearly outperform the MOSFETs but under negative stressing MNSFETs show more degradation.","PeriodicalId":266326,"journal":{"name":"Proceedings of the 10th International Symposium on the Physical and Failure Analysis of Integrated Circuits. IPFA 2003","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2003-07-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129250113","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-07-07DOI: 10.1109/IPFA.2003.1222761
T. Beauchêne, D. Lewis, P. Perdu, F. Beaudoin, P. Fouillat, A. Touboul
Alternative localization techniques to classical methods such as liquid crystal or photoemission microscopes (PEM) are studied. The aim of this article is to illustrate the suitability of Optical Beam Induced Current (OBIC) methods to accurately localize and analyze ESD defects, and to provide a global OBIC methodology.
{"title":"ESD defect localisation using photovoltaic laser stimulation techniques: optimization and interpretation","authors":"T. Beauchêne, D. Lewis, P. Perdu, F. Beaudoin, P. Fouillat, A. Touboul","doi":"10.1109/IPFA.2003.1222761","DOIUrl":"https://doi.org/10.1109/IPFA.2003.1222761","url":null,"abstract":"Alternative localization techniques to classical methods such as liquid crystal or photoemission microscopes (PEM) are studied. The aim of this article is to illustrate the suitability of Optical Beam Induced Current (OBIC) methods to accurately localize and analyze ESD defects, and to provide a global OBIC methodology.","PeriodicalId":266326,"journal":{"name":"Proceedings of the 10th International Symposium on the Physical and Failure Analysis of Integrated Circuits. IPFA 2003","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2003-07-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128945754","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-07-07DOI: 10.1109/IPFA.2003.1222711
Huixian Wu, J. Cargo, A. Seier
Failure Analysis (FA) challenges and issues in several areas, such as physical FA, site identification, and backside FA will be addressed. New failure modes, reliability issues for advanced technology, especially for Cu/Low-k technology, and advanced FA techniques will also be discussed. For physical FA, we will discuss wet chemical etching, reactive ion etching (RIE), parallel polishing, chemical mechanical polishing (CMP) and combinations of these techniques. For site identification techniques, we will address photon based techniques, laser/electron beam based scanning systems, and electrical testing techniques. Backside FA techniques have become increasingly important for advanced technology. In this work, several backside sample preparation techniques and backside site identification techniques will also be discussed.
{"title":"Overview of Cu/low K technology failure analysis and reliability issues","authors":"Huixian Wu, J. Cargo, A. Seier","doi":"10.1109/IPFA.2003.1222711","DOIUrl":"https://doi.org/10.1109/IPFA.2003.1222711","url":null,"abstract":"Failure Analysis (FA) challenges and issues in several areas, such as physical FA, site identification, and backside FA will be addressed. New failure modes, reliability issues for advanced technology, especially for Cu/Low-k technology, and advanced FA techniques will also be discussed. For physical FA, we will discuss wet chemical etching, reactive ion etching (RIE), parallel polishing, chemical mechanical polishing (CMP) and combinations of these techniques. For site identification techniques, we will address photon based techniques, laser/electron beam based scanning systems, and electrical testing techniques. Backside FA techniques have become increasingly important for advanced technology. In this work, several backside sample preparation techniques and backside site identification techniques will also be discussed.","PeriodicalId":266326,"journal":{"name":"Proceedings of the 10th International Symposium on the Physical and Failure Analysis of Integrated Circuits. IPFA 2003","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2003-07-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128504024","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-07-07DOI: 10.1109/IPFA.2003.1222736
R. Desplats, G. Faggion, F. Beaudoin, P. Perdu, T. Lundquist, K. Shah, A. Chion, M. Vallet, P. Sardin
To reduce acquisition time with PICA (Picosecond Imaging Circuit Analysis), we have developed a Spatial Temporal Photon Correlation approach (STPC-3D) which reduces acquisition from hours to minutes. Applications are presented on several devices (i.e., Azuma 0.18 /spl mu/m-1.8 V, Lazarus 0.18 /spl mu/m-1.8 V and STm 0.12 /spl mu/m-1.2 V) showing transistors and their commutations.
{"title":"A new approach for faster IC analysis with PICA: STPC-3D","authors":"R. Desplats, G. Faggion, F. Beaudoin, P. Perdu, T. Lundquist, K. Shah, A. Chion, M. Vallet, P. Sardin","doi":"10.1109/IPFA.2003.1222736","DOIUrl":"https://doi.org/10.1109/IPFA.2003.1222736","url":null,"abstract":"To reduce acquisition time with PICA (Picosecond Imaging Circuit Analysis), we have developed a Spatial Temporal Photon Correlation approach (STPC-3D) which reduces acquisition from hours to minutes. Applications are presented on several devices (i.e., Azuma 0.18 /spl mu/m-1.8 V, Lazarus 0.18 /spl mu/m-1.8 V and STm 0.12 /spl mu/m-1.2 V) showing transistors and their commutations.","PeriodicalId":266326,"journal":{"name":"Proceedings of the 10th International Symposium on the Physical and Failure Analysis of Integrated Circuits. IPFA 2003","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2003-07-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117051652","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-07-07DOI: 10.1109/IPFA.2003.1222742
H. Yap, K. Yap, Y. Tan, K. Lo
In this study, we present data from alternative wafer level EM technique, poly-heated electromigration test on via chain structure. We show that there is a good correlation between conventional package level and poly-heated via test. We also present real case studies to illustrate poly-heated via test is an effective tool for process evaluation and monitoring.
{"title":"Wafer level electromigration testing on via/line structure with a poly-heated method in comparison to standard package level tests","authors":"H. Yap, K. Yap, Y. Tan, K. Lo","doi":"10.1109/IPFA.2003.1222742","DOIUrl":"https://doi.org/10.1109/IPFA.2003.1222742","url":null,"abstract":"In this study, we present data from alternative wafer level EM technique, poly-heated electromigration test on via chain structure. We show that there is a good correlation between conventional package level and poly-heated via test. We also present real case studies to illustrate poly-heated via test is an effective tool for process evaluation and monitoring.","PeriodicalId":266326,"journal":{"name":"Proceedings of the 10th International Symposium on the Physical and Failure Analysis of Integrated Circuits. IPFA 2003","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2003-07-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129869699","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-07-07DOI: 10.1109/IPFA.2003.1222733
Y. Rey-Tauriac, M. Taurin, H. Lhermite, O. Bonnaud
The reliability prediction of device is really important for power device for which the functioning conditions can be severe. First, this paper presents two-dimensional process and device simulation results of power VDMOS one-cell in a Bipolar/CMOS/DMOS technology. The VDMOS process simulation is divided in three bricks: buried layer, active zone and sinker, and for more accuracy it takes into account all thermal budget. For process simulation, good results on sheet resistance, lateral and vertical doping diffusions are compared to experimental results. Electrical simulations are performed using mobility models for conduction regime, and impact ionisation model for breakdown voltage; they are in good agreement with experimental ones, confirming the good choice of models and possibility of device optimisation with TCAD approach. VDMOS transistors for automotive applications are submitted to high temperatures which can degrade electrical parameters; electrical simulations of threshold voltage, on-resistance, and saturation current are performed using previous models in function of temperature in the range 323 K to 423 K. Moreover, in this work, using process and electrical simulations of vertical power MOS (VDMOS) adapted to the process developed by STMicroelectronics, we deduced by comparison with HTRB (High Temperature Reverse Bias) analysis, the contamination of gate oxide. This approach allows evaluating the contamination level especially, degradation coming from mobile ions.
{"title":"Reliability oriented process and device simulations of power VDMOS transistors in Bipolar/CMOS/DMOS technology","authors":"Y. Rey-Tauriac, M. Taurin, H. Lhermite, O. Bonnaud","doi":"10.1109/IPFA.2003.1222733","DOIUrl":"https://doi.org/10.1109/IPFA.2003.1222733","url":null,"abstract":"The reliability prediction of device is really important for power device for which the functioning conditions can be severe. First, this paper presents two-dimensional process and device simulation results of power VDMOS one-cell in a Bipolar/CMOS/DMOS technology. The VDMOS process simulation is divided in three bricks: buried layer, active zone and sinker, and for more accuracy it takes into account all thermal budget. For process simulation, good results on sheet resistance, lateral and vertical doping diffusions are compared to experimental results. Electrical simulations are performed using mobility models for conduction regime, and impact ionisation model for breakdown voltage; they are in good agreement with experimental ones, confirming the good choice of models and possibility of device optimisation with TCAD approach. VDMOS transistors for automotive applications are submitted to high temperatures which can degrade electrical parameters; electrical simulations of threshold voltage, on-resistance, and saturation current are performed using previous models in function of temperature in the range 323 K to 423 K. Moreover, in this work, using process and electrical simulations of vertical power MOS (VDMOS) adapted to the process developed by STMicroelectronics, we deduced by comparison with HTRB (High Temperature Reverse Bias) analysis, the contamination of gate oxide. This approach allows evaluating the contamination level especially, degradation coming from mobile ions.","PeriodicalId":266326,"journal":{"name":"Proceedings of the 10th International Symposium on the Physical and Failure Analysis of Integrated Circuits. IPFA 2003","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2003-07-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114552898","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-07-07DOI: 10.1109/IPFA.2003.1222751
Y. K. Lim, Suat Cheng Khoo, Kai Tern Sih, C. Seet, Beichao Zhang, T. Lee
Process variations such as post etch cleaning, pre-cleaning prior to Cu barrier/seed deposition and Cu annealing can yield significant differences in electromigration (EM) failure populations even while maintaining general microstructure consistency. In this paper, focus-ion-beam (FIB) cross-sectional imaging is used to reveal how bimodal EM failures originate. In addition, a novel integrated scheme with an optimized post etch clean after nitride breakthrough, in-situ H/sub 2/ contained precursor treatment prior to Cu barrier/seed deposition and an optimized Cu anneal condition is introduced to improve the electrical and eliminate the bimodal EM failures of Cu interconnects.
{"title":"A novel integrated scheme to improve the electrical and electromigration performance of Cu interconnects","authors":"Y. K. Lim, Suat Cheng Khoo, Kai Tern Sih, C. Seet, Beichao Zhang, T. Lee","doi":"10.1109/IPFA.2003.1222751","DOIUrl":"https://doi.org/10.1109/IPFA.2003.1222751","url":null,"abstract":"Process variations such as post etch cleaning, pre-cleaning prior to Cu barrier/seed deposition and Cu annealing can yield significant differences in electromigration (EM) failure populations even while maintaining general microstructure consistency. In this paper, focus-ion-beam (FIB) cross-sectional imaging is used to reveal how bimodal EM failures originate. In addition, a novel integrated scheme with an optimized post etch clean after nitride breakthrough, in-situ H/sub 2/ contained precursor treatment prior to Cu barrier/seed deposition and an optimized Cu anneal condition is introduced to improve the electrical and eliminate the bimodal EM failures of Cu interconnects.","PeriodicalId":266326,"journal":{"name":"Proceedings of the 10th International Symposium on the Physical and Failure Analysis of Integrated Circuits. IPFA 2003","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2003-07-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121982237","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-07-07DOI: 10.1109/IPFA.2003.1222748
N. Kongtongnok, S. Anuntapong
In this paper, the results of the fracture joint failure mechanism and pattern when perform board level reliability test by comparing between SnPb and Pb-free lead finished ICs. It is modelling simulation by using finite element method analysis.
{"title":"Studying of fracture joint failure mechanism on board level reliability test process comparing between SnPb and Sn lead finished ICs","authors":"N. Kongtongnok, S. Anuntapong","doi":"10.1109/IPFA.2003.1222748","DOIUrl":"https://doi.org/10.1109/IPFA.2003.1222748","url":null,"abstract":"In this paper, the results of the fracture joint failure mechanism and pattern when perform board level reliability test by comparing between SnPb and Pb-free lead finished ICs. It is modelling simulation by using finite element method analysis.","PeriodicalId":266326,"journal":{"name":"Proceedings of the 10th International Symposium on the Physical and Failure Analysis of Integrated Circuits. IPFA 2003","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2003-07-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130914587","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-07-07DOI: 10.1109/IPFA.2003.1222757
W. Loh, B.J. Cho, M. Li, D. Chan, C.H. Ang, Z.J. Zhen, D. Kwong
We report an area-dependent gate current increase in 13.4 /spl Aring/ oxide. Area dependence studies show that larger sample have smaller current density increases. Using leakage current density increase as failure criterion, it was shown that smaller area samples will have shorter lifetime. By using a discrete current formalism to describe the multiple degraded spots, it was shown that leakage current can be used to deduce that distribution statistics of the oxide and that the multiple spots distribution model can be described by Weibull's statistics.
{"title":"Progressive breakdown statistics in ultra-thin silicon dioxides","authors":"W. Loh, B.J. Cho, M. Li, D. Chan, C.H. Ang, Z.J. Zhen, D. Kwong","doi":"10.1109/IPFA.2003.1222757","DOIUrl":"https://doi.org/10.1109/IPFA.2003.1222757","url":null,"abstract":"We report an area-dependent gate current increase in 13.4 /spl Aring/ oxide. Area dependence studies show that larger sample have smaller current density increases. Using leakage current density increase as failure criterion, it was shown that smaller area samples will have shorter lifetime. By using a discrete current formalism to describe the multiple degraded spots, it was shown that leakage current can be used to deduce that distribution statistics of the oxide and that the multiple spots distribution model can be described by Weibull's statistics.","PeriodicalId":266326,"journal":{"name":"Proceedings of the 10th International Symposium on the Physical and Failure Analysis of Integrated Circuits. IPFA 2003","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2003-07-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114188543","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-07-07DOI: 10.1109/IPFA.2003.1222765
Z. Mai, Benjamin Lau, G. Qian, Jian Jun Shi, R. He, Jessica Chin
In this paper, we explained a failure analysis methodology to identify optical proximity correction issues in 0.13 /spl mu/m technology development. Here we used, the continue-on-failure wafer sort technology for yield analysis.
{"title":"Identify Optical Proximity Correction (OPC) issue in 0.13 /spl mu/m technology development","authors":"Z. Mai, Benjamin Lau, G. Qian, Jian Jun Shi, R. He, Jessica Chin","doi":"10.1109/IPFA.2003.1222765","DOIUrl":"https://doi.org/10.1109/IPFA.2003.1222765","url":null,"abstract":"In this paper, we explained a failure analysis methodology to identify optical proximity correction issues in 0.13 /spl mu/m technology development. Here we used, the continue-on-failure wafer sort technology for yield analysis.","PeriodicalId":266326,"journal":{"name":"Proceedings of the 10th International Symposium on the Physical and Failure Analysis of Integrated Circuits. IPFA 2003","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2003-07-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114113353","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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