Pub Date : 2003-07-07DOI: 10.1109/IPFA.2003.1222743
S. Phurikhup, S. Pruettipongsapuk, K. Sirivathanant
In this paper, we introduces a new , non-destructive inspection technique for die crack and crack pattern using a memory tester. The concept of the technique is based upon the fact that almost ninety percent of the space of a memory device consists of cell memories, thus if microcrack is present, the phenomenon would cause malfunctioning of the memory.
{"title":"Application of memory tester for non-destructive detection of micro-crack and crack patterns in flash memory devices","authors":"S. Phurikhup, S. Pruettipongsapuk, K. Sirivathanant","doi":"10.1109/IPFA.2003.1222743","DOIUrl":"https://doi.org/10.1109/IPFA.2003.1222743","url":null,"abstract":"In this paper, we introduces a new , non-destructive inspection technique for die crack and crack pattern using a memory tester. The concept of the technique is based upon the fact that almost ninety percent of the space of a memory device consists of cell memories, thus if microcrack is present, the phenomenon would cause malfunctioning of the memory.","PeriodicalId":266326,"journal":{"name":"Proceedings of the 10th International Symposium on the Physical and Failure Analysis of Integrated Circuits. IPFA 2003","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2003-07-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114751464","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-07-07DOI: 10.1109/IPFA.2003.1222767
K. Li, E. Er, S. Redkar
STEM imaging applications in deep-sub-micron failure analysis and process characterization have been discussed.
讨论了STEM成像在深亚微米失效分析和工艺表征中的应用。
{"title":"STEM imaging applications in deep-sub-micron failure analysis and process characterization","authors":"K. Li, E. Er, S. Redkar","doi":"10.1109/IPFA.2003.1222767","DOIUrl":"https://doi.org/10.1109/IPFA.2003.1222767","url":null,"abstract":"STEM imaging applications in deep-sub-micron failure analysis and process characterization have been discussed.","PeriodicalId":266326,"journal":{"name":"Proceedings of the 10th International Symposium on the Physical and Failure Analysis of Integrated Circuits. IPFA 2003","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2003-07-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126250891","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-07-07DOI: 10.1109/IPFA.2003.1222764
M. Bailon, A. Tarun, M. Nery, J. Munoz
We demonstrate how the Infrared Emission Microscope was used to localize defects in standard I/O pins of integrated circuits and how emission images were used to verify electrical fail signatures. The paper also discusses a method that can be used to improve the localization of electrical failures.
{"title":"Localization of electrical failures from the backside of the die: Failure Analysis case studies using infrared emission microscope","authors":"M. Bailon, A. Tarun, M. Nery, J. Munoz","doi":"10.1109/IPFA.2003.1222764","DOIUrl":"https://doi.org/10.1109/IPFA.2003.1222764","url":null,"abstract":"We demonstrate how the Infrared Emission Microscope was used to localize defects in standard I/O pins of integrated circuits and how emission images were used to verify electrical fail signatures. The paper also discusses a method that can be used to improve the localization of electrical failures.","PeriodicalId":266326,"journal":{"name":"Proceedings of the 10th International Symposium on the Physical and Failure Analysis of Integrated Circuits. IPFA 2003","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2003-07-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123613321","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-07-07DOI: 10.1109/IPFA.2003.1222766
W. Zhang, S. Ng, D. Cheong, S. Lim
In this paper, application of EFTEM, combined with EDAX in STEM mode, is addressed to structural and chemical characterization in 0.25 /spl mu/m technology node.
{"title":"Application of energy-filtering TEM in contrast enhancement and elemental identification in IC failure analysis","authors":"W. Zhang, S. Ng, D. Cheong, S. Lim","doi":"10.1109/IPFA.2003.1222766","DOIUrl":"https://doi.org/10.1109/IPFA.2003.1222766","url":null,"abstract":"In this paper, application of EFTEM, combined with EDAX in STEM mode, is addressed to structural and chemical characterization in 0.25 /spl mu/m technology node.","PeriodicalId":266326,"journal":{"name":"Proceedings of the 10th International Symposium on the Physical and Failure Analysis of Integrated Circuits. IPFA 2003","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2003-07-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128791401","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-07-07DOI: 10.1109/IPFA.2003.1222740
C. Tsang, Y. Su, V.N. Bliznetsov, G.T. Ang
We reported the failure analysis of 130 nm Cu/CVD low k film back-end-of-line (BEOL) process and successfully identified the root causes of failures leading to electrical yield loss of the process. We also demonstrated the significant yield enhancements through a) optimization of via & trench etch recipes and post-etch clean condition, b) tightened defectivity control and c) in-line monitoring control.
{"title":"130 nm process technology integration of advanced Cu/CVD low k dielectric material-case study of failure analysis and yield enhancement","authors":"C. Tsang, Y. Su, V.N. Bliznetsov, G.T. Ang","doi":"10.1109/IPFA.2003.1222740","DOIUrl":"https://doi.org/10.1109/IPFA.2003.1222740","url":null,"abstract":"We reported the failure analysis of 130 nm Cu/CVD low k film back-end-of-line (BEOL) process and successfully identified the root causes of failures leading to electrical yield loss of the process. We also demonstrated the significant yield enhancements through a) optimization of via & trench etch recipes and post-etch clean condition, b) tightened defectivity control and c) in-line monitoring control.","PeriodicalId":266326,"journal":{"name":"Proceedings of the 10th International Symposium on the Physical and Failure Analysis of Integrated Circuits. IPFA 2003","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2003-07-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129595652","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-07-07DOI: 10.1109/IPFA.2003.1222735
E. Zschech, E. Langer, M. Meyer
In this paper, we focussed about the failures in copper interconnects and on analytical techniques that are applied for physical failure analysis. Electromigration test structure after partial degradation by voiding was observed using SEM images.
{"title":"Failures in copper interconnects-localization, analysis and degradation mechanisms","authors":"E. Zschech, E. Langer, M. Meyer","doi":"10.1109/IPFA.2003.1222735","DOIUrl":"https://doi.org/10.1109/IPFA.2003.1222735","url":null,"abstract":"In this paper, we focussed about the failures in copper interconnects and on analytical techniques that are applied for physical failure analysis. Electromigration test structure after partial degradation by voiding was observed using SEM images.","PeriodicalId":266326,"journal":{"name":"Proceedings of the 10th International Symposium on the Physical and Failure Analysis of Integrated Circuits. IPFA 2003","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2003-07-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114227839","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-07-07DOI: 10.1109/IPFA.2003.1222752
S. Chung, Shih-Hung Chen, D. Lo
Interface characterization is fundamental to the understanding of device reliability as well as the process monitoring, in particular for the development of an efficient tool for analyzing the hot carrier reliability of ultra-thin gate oxide CMOS devices. This paper will cover an overview of advanced charge pumping (CP), DCIV, Gated-Diode (GD), techniques for the interface characterization of CMOS reliabilities. Its potential use for the device reliability study, and oxide quality monitoring for the state-of-the-art CMOS technology will be presented. More recent developments for nano-CMOS device applications will be demonstrated. Moreover, further development and the roadblocks of these techniques will be addressed.
{"title":"Interface characterization methodology for nano-CMOS reliability-process and device reliability monitors","authors":"S. Chung, Shih-Hung Chen, D. Lo","doi":"10.1109/IPFA.2003.1222752","DOIUrl":"https://doi.org/10.1109/IPFA.2003.1222752","url":null,"abstract":"Interface characterization is fundamental to the understanding of device reliability as well as the process monitoring, in particular for the development of an efficient tool for analyzing the hot carrier reliability of ultra-thin gate oxide CMOS devices. This paper will cover an overview of advanced charge pumping (CP), DCIV, Gated-Diode (GD), techniques for the interface characterization of CMOS reliabilities. Its potential use for the device reliability study, and oxide quality monitoring for the state-of-the-art CMOS technology will be presented. More recent developments for nano-CMOS device applications will be demonstrated. Moreover, further development and the roadblocks of these techniques will be addressed.","PeriodicalId":266326,"journal":{"name":"Proceedings of the 10th International Symposium on the Physical and Failure Analysis of Integrated Circuits. IPFA 2003","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2003-07-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134094400","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-07-07DOI: 10.1109/IPFA.2003.1222768
A. Firiti, D. Lewis, F. Beaudoin, P. Perdu, G. Haller, Y. Danto
First Photoelectric Laser Stimulation results (OBIC or LIVA) obtained with an upgraded version of a PHEMOS 1000 from Hamamatsu are presented. This technique is applied in a case study concerning ESD defect localization and is compared to the Thermal Laser Stimulation one.
{"title":"Implementing Thermal Laser and Photoelectric Laser Stimulation in a failure analysis laboratory","authors":"A. Firiti, D. Lewis, F. Beaudoin, P. Perdu, G. Haller, Y. Danto","doi":"10.1109/IPFA.2003.1222768","DOIUrl":"https://doi.org/10.1109/IPFA.2003.1222768","url":null,"abstract":"First Photoelectric Laser Stimulation results (OBIC or LIVA) obtained with an upgraded version of a PHEMOS 1000 from Hamamatsu are presented. This technique is applied in a case study concerning ESD defect localization and is compared to the Thermal Laser Stimulation one.","PeriodicalId":266326,"journal":{"name":"Proceedings of the 10th International Symposium on the Physical and Failure Analysis of Integrated Circuits. IPFA 2003","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2003-07-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132378687","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Real case studies of fast wafer level reliability (FWLR) EM test as process reliability monitor methodology","authors":"A. Yap, T.W.H. Ling, H. Yap, B. H. Lim, Y. Tan, K. Lo","doi":"10.1109/IPFA.2003.1222750","DOIUrl":"https://doi.org/10.1109/IPFA.2003.1222750","url":null,"abstract":"In this paper, we present real case studies to illustrate SWEAT and ISOT EM tests effectiveness as reliability screens and monitoring methodology.","PeriodicalId":266326,"journal":{"name":"Proceedings of the 10th International Symposium on the Physical and Failure Analysis of Integrated Circuits. IPFA 2003","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2003-07-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114022768","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-07-07DOI: 10.1109/IPFA.2003.1222744
L. Soon, D.T.M. Ling, M. Kuan, K. W. Yee, D. Cheong, G. Zhang
IR-OBIRCH (Infra-Red Optical Beam Induced Resistance Change) is a revolutionary new method for the localization of leakage current paths and detection of abnormal resistance in interconnects of ULSI devices. Application of this technique to the actual failure analysis of 0.25 /spl mu/m, 0.22 /spl mu/m & 0.18 /spl mu/m CMOS integrated circuits in volume production was demonstrated. It was found that IR-OBIRCH is a powerful fault isolation technique. Process defects detectable using this technique in our experience are: 1) Short circuits due to interconnect bridging. 2) Short circuits due to poly-gate bridging or poly-gate to source/drain bridging. 3) Resistive Vias due to the presence of micro-voids or residue at via/metal interface.
{"title":"Application of IR-OBIRCH to the failure analysis of CMOS integrated circuits","authors":"L. Soon, D.T.M. Ling, M. Kuan, K. W. Yee, D. Cheong, G. Zhang","doi":"10.1109/IPFA.2003.1222744","DOIUrl":"https://doi.org/10.1109/IPFA.2003.1222744","url":null,"abstract":"IR-OBIRCH (Infra-Red Optical Beam Induced Resistance Change) is a revolutionary new method for the localization of leakage current paths and detection of abnormal resistance in interconnects of ULSI devices. Application of this technique to the actual failure analysis of 0.25 /spl mu/m, 0.22 /spl mu/m & 0.18 /spl mu/m CMOS integrated circuits in volume production was demonstrated. It was found that IR-OBIRCH is a powerful fault isolation technique. Process defects detectable using this technique in our experience are: 1) Short circuits due to interconnect bridging. 2) Short circuits due to poly-gate bridging or poly-gate to source/drain bridging. 3) Resistive Vias due to the presence of micro-voids or residue at via/metal interface.","PeriodicalId":266326,"journal":{"name":"Proceedings of the 10th International Symposium on the Physical and Failure Analysis of Integrated Circuits. IPFA 2003","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2003-07-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116813962","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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