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Proceedings of the 10th International Symposium on the Physical and Failure Analysis of Integrated Circuits. IPFA 2003最新文献

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Application of memory tester for non-destructive detection of micro-crack and crack patterns in flash memory devices 记忆测试仪在快闪记忆装置微裂纹及裂纹模式无损检测中的应用
S. Phurikhup, S. Pruettipongsapuk, K. Sirivathanant
In this paper, we introduces a new , non-destructive inspection technique for die crack and crack pattern using a memory tester. The concept of the technique is based upon the fact that almost ninety percent of the space of a memory device consists of cell memories, thus if microcrack is present, the phenomenon would cause malfunctioning of the memory.
本文介绍了一种利用记忆测试仪对模具裂纹和裂纹模式进行无损检测的新技术。该技术的概念是基于这样一个事实,即几乎90%的存储设备的空间是由细胞存储器组成的,因此,如果微裂纹存在,这种现象将导致存储器的故障。
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引用次数: 0
STEM imaging applications in deep-sub-micron failure analysis and process characterization STEM成像在深亚微米失效分析和工艺表征中的应用
K. Li, E. Er, S. Redkar
STEM imaging applications in deep-sub-micron failure analysis and process characterization have been discussed.
讨论了STEM成像在深亚微米失效分析和工艺表征中的应用。
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引用次数: 2
Localization of electrical failures from the backside of the die: Failure Analysis case studies using infrared emission microscope 从模具背面定位电气故障:使用红外发射显微镜的故障分析案例研究
M. Bailon, A. Tarun, M. Nery, J. Munoz
We demonstrate how the Infrared Emission Microscope was used to localize defects in standard I/O pins of integrated circuits and how emission images were used to verify electrical fail signatures. The paper also discusses a method that can be used to improve the localization of electrical failures.
我们演示了如何使用红外发射显微镜来定位集成电路标准I/O引脚中的缺陷,以及如何使用发射图像来验证电气故障特征。本文还讨论了一种可用于提高电气故障定位的方法。
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引用次数: 0
Failures in copper interconnects-localization, analysis and degradation mechanisms 铜互连失效——定位、分析和退化机制
E. Zschech, E. Langer, M. Meyer
In this paper, we focussed about the failures in copper interconnects and on analytical techniques that are applied for physical failure analysis. Electromigration test structure after partial degradation by voiding was observed using SEM images.
在本文中,我们重点介绍了铜互连中的失效以及用于物理失效分析的分析技术。利用扫描电镜(SEM)观察了真空部分降解后的电迁移试验结构。
{"title":"Failures in copper interconnects-localization, analysis and degradation mechanisms","authors":"E. Zschech, E. Langer, M. Meyer","doi":"10.1109/IPFA.2003.1222735","DOIUrl":"https://doi.org/10.1109/IPFA.2003.1222735","url":null,"abstract":"In this paper, we focussed about the failures in copper interconnects and on analytical techniques that are applied for physical failure analysis. Electromigration test structure after partial degradation by voiding was observed using SEM images.","PeriodicalId":266326,"journal":{"name":"Proceedings of the 10th International Symposium on the Physical and Failure Analysis of Integrated Circuits. IPFA 2003","volume":"67 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-07-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114227839","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Application of energy-filtering TEM in contrast enhancement and elemental identification in IC failure analysis 能量滤波透射电镜在集成电路失效分析中的对比度增强和元素识别应用
W. Zhang, S. Ng, D. Cheong, S. Lim
In this paper, application of EFTEM, combined with EDAX in STEM mode, is addressed to structural and chemical characterization in 0.25 /spl mu/m technology node.
本文以0.25 /spl mu/m技术节点为研究对象,利用EFTEM结合STEM模式下的EDAX进行结构和化学表征。
{"title":"Application of energy-filtering TEM in contrast enhancement and elemental identification in IC failure analysis","authors":"W. Zhang, S. Ng, D. Cheong, S. Lim","doi":"10.1109/IPFA.2003.1222766","DOIUrl":"https://doi.org/10.1109/IPFA.2003.1222766","url":null,"abstract":"In this paper, application of EFTEM, combined with EDAX in STEM mode, is addressed to structural and chemical characterization in 0.25 /spl mu/m technology node.","PeriodicalId":266326,"journal":{"name":"Proceedings of the 10th International Symposium on the Physical and Failure Analysis of Integrated Circuits. IPFA 2003","volume":"192 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-07-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128791401","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Implementing Thermal Laser and Photoelectric Laser Stimulation in a failure analysis laboratory 在失效分析实验室实施热激光和光电激光刺激
A. Firiti, D. Lewis, F. Beaudoin, P. Perdu, G. Haller, Y. Danto
First Photoelectric Laser Stimulation results (OBIC or LIVA) obtained with an upgraded version of a PHEMOS 1000 from Hamamatsu are presented. This technique is applied in a case study concerning ESD defect localization and is compared to the Thermal Laser Stimulation one.
本文介绍了利用滨松公司的PHEMOS 1000升级版获得的光电激光刺激结果(OBIC或LIVA)。将该技术应用于ESD缺陷定位的案例研究中,并与热激光刺激技术进行了比较。
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引用次数: 8
130 nm process technology integration of advanced Cu/CVD low k dielectric material-case study of failure analysis and yield enhancement 先进Cu/CVD低k介电材料130nm工艺技术集成——失效分析与良率提升案例研究
C. Tsang, Y. Su, V.N. Bliznetsov, G.T. Ang
We reported the failure analysis of 130 nm Cu/CVD low k film back-end-of-line (BEOL) process and successfully identified the root causes of failures leading to electrical yield loss of the process. We also demonstrated the significant yield enhancements through a) optimization of via & trench etch recipes and post-etch clean condition, b) tightened defectivity control and c) in-line monitoring control.
本文报道了130 nm Cu/CVD低k膜BEOL工艺的失效分析,并成功地找出了导致该工艺电产率损失的失效根源。我们还通过a)优化通孔和沟槽蚀刻配方和蚀刻后清洁条件,b)加强缺陷控制和c)在线监测控制,证明了显著的产量提高。
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引用次数: 3
Interface characterization methodology for nano-CMOS reliability-process and device reliability monitors 纳米cmos可靠性-工艺和器件可靠性监视器的接口表征方法
S. Chung, Shih-Hung Chen, D. Lo
Interface characterization is fundamental to the understanding of device reliability as well as the process monitoring, in particular for the development of an efficient tool for analyzing the hot carrier reliability of ultra-thin gate oxide CMOS devices. This paper will cover an overview of advanced charge pumping (CP), DCIV, Gated-Diode (GD), techniques for the interface characterization of CMOS reliabilities. Its potential use for the device reliability study, and oxide quality monitoring for the state-of-the-art CMOS technology will be presented. More recent developments for nano-CMOS device applications will be demonstrated. Moreover, further development and the roadblocks of these techniques will be addressed.
接口表征是理解器件可靠性和过程监控的基础,特别是对于开发一种有效的工具来分析超薄栅氧化CMOS器件的热载流子可靠性。本文将概述先进的电荷泵浦(CP), DCIV,门控二极管(GD), CMOS可靠性的接口表征技术。将介绍其在器件可靠性研究和最先进CMOS技术的氧化物质量监测方面的潜在用途。将展示纳米cmos器件应用的最新发展。此外,还将讨论这些技术的进一步发展和障碍。
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引用次数: 1
Neutron induced oxide degradation in MOSFET structures MOSFET结构中中子诱导的氧化物降解
D. Sharma, A. Chandorkar, S. vaidya
In this paper, we have measured the intensity of gamma radiation accompanying neutrons at different neutron fluences at the irradiation position. MOS samples were subjected to neutron radiation in a swimming pool type of reactor and other samples from the same batch were exposed to an equivalent dose of accompanying gamma radiation using Co/sup 60/ gamma source. The difference in the damage caused by the neutrons. While executing this approach, major issues considered were, calibration of gamma radiation accompanying neutrons, consideration of energy spectrums of Co/sup 60/ and accompanying gamma, measurement of thermal and fast neutron flux at the irradiation position of the reactor and measurement of flux at the different power levels.
在本文中,我们测量了在辐照位置不同中子通量下伴随中子的伽马辐射强度。MOS样品在游泳池式反应堆中接受中子辐射,同一批次的其他样品使用Co/sup 60/ γ源接受等效剂量的伴随伽马辐射。中子造成的伤害的差异。在执行该方法时,考虑的主要问题是:伴随中子的伽马辐射的校准,Co/sup 60/和伴随伽马能谱的考虑,反应堆辐照位置热中子和快中子通量的测量以及不同功率水平下通量的测量。
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引用次数: 4
The effect of CHE and CHISEL programming operation on drain disturb in flash EEPROMs CHE和CHISEL编程操作对闪存eeprom漏极干扰的影响
D. Nair, N. Mohapatra, S. Mahapatra, S. Shukuri, J. Bude
In this paper, we report an extensive study of drain disturb in isolated cells under channel hot electron (CHE) and channel initiated secondary electron (CHISEL) has been identified to be initiated by band-to-band (BB) tunnelling as opposed to S/D leakage for CHE operation. This is verified by measurements under different temperature and on cells having different floating gate length (L/sub fg/). The effect of program/erase (P/E) cycling on drain distrubs is explored for different control gate bias (V/sub cg/) and V/sub d/. After cycling the program/disturb margin has been found to decrease for the charge gain mode, while it remains constant for the charge loss mode. The program/disturb margin for CHISEL operation is slightly lower compared to CHE operation under identical (initial) programming time (T/sub p/). However the margin becomes identical when compared after 100K P/E cycling.
在本文中,我们报告了一项广泛的研究,在通道热电子(CHE)和通道引发的二次电子(CHISEL)下,孤立细胞的漏极干扰被确定为由带对带(BB)隧穿引发,而不是通道操作的S/D泄漏。通过在不同温度和具有不同浮栅长度(L/sub fg/)的电池上的测量来验证这一点。在不同的控制栅极偏置(V/sub / cg/)和V/sub / d/下,探讨了程序/擦除(P/E)循环对漏极干扰的影响。循环后,程序/干扰余量在电荷增益模式下减小,而在电荷损失模式下保持恒定。在相同的(初始)编程时间(T/ p/)下,与CHE操作相比,CHISEL操作的程序/干扰余量略低。然而,在100K的市盈率循环之后,边际是相同的。
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引用次数: 4
期刊
Proceedings of the 10th International Symposium on the Physical and Failure Analysis of Integrated Circuits. IPFA 2003
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