Pub Date : 2003-07-07DOI: 10.1109/IPFA.2003.1222758
D. Nair, N. Mohapatra, S. Mahapatra, S. Shukuri, J. Bude
In this paper, we report an extensive study of drain disturb in isolated cells under channel hot electron (CHE) and channel initiated secondary electron (CHISEL) has been identified to be initiated by band-to-band (BB) tunnelling as opposed to S/D leakage for CHE operation. This is verified by measurements under different temperature and on cells having different floating gate length (L/sub fg/). The effect of program/erase (P/E) cycling on drain distrubs is explored for different control gate bias (V/sub cg/) and V/sub d/. After cycling the program/disturb margin has been found to decrease for the charge gain mode, while it remains constant for the charge loss mode. The program/disturb margin for CHISEL operation is slightly lower compared to CHE operation under identical (initial) programming time (T/sub p/). However the margin becomes identical when compared after 100K P/E cycling.
{"title":"The effect of CHE and CHISEL programming operation on drain disturb in flash EEPROMs","authors":"D. Nair, N. Mohapatra, S. Mahapatra, S. Shukuri, J. Bude","doi":"10.1109/IPFA.2003.1222758","DOIUrl":"https://doi.org/10.1109/IPFA.2003.1222758","url":null,"abstract":"In this paper, we report an extensive study of drain disturb in isolated cells under channel hot electron (CHE) and channel initiated secondary electron (CHISEL) has been identified to be initiated by band-to-band (BB) tunnelling as opposed to S/D leakage for CHE operation. This is verified by measurements under different temperature and on cells having different floating gate length (L/sub fg/). The effect of program/erase (P/E) cycling on drain distrubs is explored for different control gate bias (V/sub cg/) and V/sub d/. After cycling the program/disturb margin has been found to decrease for the charge gain mode, while it remains constant for the charge loss mode. The program/disturb margin for CHISEL operation is slightly lower compared to CHE operation under identical (initial) programming time (T/sub p/). However the margin becomes identical when compared after 100K P/E cycling.","PeriodicalId":266326,"journal":{"name":"Proceedings of the 10th International Symposium on the Physical and Failure Analysis of Integrated Circuits. IPFA 2003","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2003-07-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122132279","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-07-07DOI: 10.1109/IPFA.2003.1222756
D. Sharma, A. Chandorkar, S. vaidya
In this paper, we have measured the intensity of gamma radiation accompanying neutrons at different neutron fluences at the irradiation position. MOS samples were subjected to neutron radiation in a swimming pool type of reactor and other samples from the same batch were exposed to an equivalent dose of accompanying gamma radiation using Co/sup 60/ gamma source. The difference in the damage caused by the neutrons. While executing this approach, major issues considered were, calibration of gamma radiation accompanying neutrons, consideration of energy spectrums of Co/sup 60/ and accompanying gamma, measurement of thermal and fast neutron flux at the irradiation position of the reactor and measurement of flux at the different power levels.
{"title":"Neutron induced oxide degradation in MOSFET structures","authors":"D. Sharma, A. Chandorkar, S. vaidya","doi":"10.1109/IPFA.2003.1222756","DOIUrl":"https://doi.org/10.1109/IPFA.2003.1222756","url":null,"abstract":"In this paper, we have measured the intensity of gamma radiation accompanying neutrons at different neutron fluences at the irradiation position. MOS samples were subjected to neutron radiation in a swimming pool type of reactor and other samples from the same batch were exposed to an equivalent dose of accompanying gamma radiation using Co/sup 60/ gamma source. The difference in the damage caused by the neutrons. While executing this approach, major issues considered were, calibration of gamma radiation accompanying neutrons, consideration of energy spectrums of Co/sup 60/ and accompanying gamma, measurement of thermal and fast neutron flux at the irradiation position of the reactor and measurement of flux at the different power levels.","PeriodicalId":266326,"journal":{"name":"Proceedings of the 10th International Symposium on the Physical and Failure Analysis of Integrated Circuits. IPFA 2003","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2003-07-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117345283","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-07-07DOI: 10.1109/IPFA.2003.1222760
Wen-Yu Lo, M. Ker
An abnormal failure mechanism due to ESD stressing on the Non-Connected (NC) balls of a high-pin-count (>500 balls) BGA packaged IC is presented. Failure analyses including Scanning Electronic Microscopy (SEM) photographs and the measurement of current waveform during ESD zapping had been performed to give clear explanation on this unusual phenomenon. New protection solutions have been proposed to solve this problem in a BGA packaged IC product with an improvement ESD robustness, which can sustain 3-kV HBM and 300-V MM ESD stresses.
提出了一种高引脚数(>500球)BGA封装集成电路的非连接(NC)球在ESD应力作用下的异常失效机理。通过扫描电镜(SEM)照片和测量静电放电过程中的电流波形等故障分析，对这一异常现象进行了明确的解释。为了解决这一问题，BGA封装IC产品提出了新的保护方案，提高了ESD稳健性，可以承受3 kv HBM和300 v MM ESD应力。
{"title":"Analysis of abnormal ESD failure mechanism in high-pin-count BGA packaged ICs due to stressing non-connected balls","authors":"Wen-Yu Lo, M. Ker","doi":"10.1109/IPFA.2003.1222760","DOIUrl":"https://doi.org/10.1109/IPFA.2003.1222760","url":null,"abstract":"An abnormal failure mechanism due to ESD stressing on the Non-Connected (NC) balls of a high-pin-count (>500 balls) BGA packaged IC is presented. Failure analyses including Scanning Electronic Microscopy (SEM) photographs and the measurement of current waveform during ESD zapping had been performed to give clear explanation on this unusual phenomenon. New protection solutions have been proposed to solve this problem in a BGA packaged IC product with an improvement ESD robustness, which can sustain 3-kV HBM and 300-V MM ESD stresses.","PeriodicalId":266326,"journal":{"name":"Proceedings of the 10th International Symposium on the Physical and Failure Analysis of Integrated Circuits. IPFA 2003","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2003-07-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129745937","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-07-07DOI: 10.1109/IPFA.2003.1222739
P. Ho, K.-D. Lee, E. Ogawa, X. Lu, H. Matsuhashi
Electromigration (EM) reliability in Cu dual-damascene structures integrated with oxide and low-k ILD was investigated using a statistical approach. This approach is efficient in addressing early failures using multi-link structures to sample very large number of interconnect elements. In this paper, we summarize results first on early failures of Cu/oxide structures, then EM characteristics of Cu/low-k structures are discussed and compared with Cu/oxide structures. The integration of low-k ILD was found to degrade EM performance and to induce a new failure mechanism. These results can be attributed to the thermomechanical properties of the low-k ILD and its implication on EM reliability will be discussed.
{"title":"Electromigration reliability of Cu interconnects and the impact of low-k dielectrics","authors":"P. Ho, K.-D. Lee, E. Ogawa, X. Lu, H. Matsuhashi","doi":"10.1109/IPFA.2003.1222739","DOIUrl":"https://doi.org/10.1109/IPFA.2003.1222739","url":null,"abstract":"Electromigration (EM) reliability in Cu dual-damascene structures integrated with oxide and low-k ILD was investigated using a statistical approach. This approach is efficient in addressing early failures using multi-link structures to sample very large number of interconnect elements. In this paper, we summarize results first on early failures of Cu/oxide structures, then EM characteristics of Cu/low-k structures are discussed and compared with Cu/oxide structures. The integration of low-k ILD was found to degrade EM performance and to induce a new failure mechanism. These results can be attributed to the thermomechanical properties of the low-k ILD and its implication on EM reliability will be discussed.","PeriodicalId":266326,"journal":{"name":"Proceedings of the 10th International Symposium on the Physical and Failure Analysis of Integrated Circuits. IPFA 2003","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2003-07-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126335151","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-07-07DOI: 10.1109/IPFA.2003.1222753
L. Tang, K. Pey, C. Tung, M. Radhakrishnan, W. Lin
Numerous failure mechanisms associated with hard breakdowns (HBD) in ultrathin gate oxides were physically studied by high resolution TEM. Migration of silicide from silicided gate and source/drain regions, abnormal growth of dielectric-breakdown-induce-Si epitaxy (DBIE), poly-Si gate melt-down and recrystallization, severe damage in Si substrate and total epitaxy of poly-Si gate and Si substrate of the entire transistor are among the common microstructural damages observed in MOSFETs after hard breakdowns in gate oxides (Gox) were observed electrically. The type of catastrophic failures and its degree of damage are found to be strongly dependent on the allowable current density and total resistance of the breakdown path during the breakdown transient. The physical analysis data from TEM analysis allow us to establish the sequence of the physical damages associated with the Gox HBD in transistors. The proposed model is able to predict the next possible microstructural damage induced by HBD.
{"title":"Gate dielectric breakdown induced microstructural damages in MOSFETs","authors":"L. Tang, K. Pey, C. Tung, M. Radhakrishnan, W. Lin","doi":"10.1109/IPFA.2003.1222753","DOIUrl":"https://doi.org/10.1109/IPFA.2003.1222753","url":null,"abstract":"Numerous failure mechanisms associated with hard breakdowns (HBD) in ultrathin gate oxides were physically studied by high resolution TEM. Migration of silicide from silicided gate and source/drain regions, abnormal growth of dielectric-breakdown-induce-Si epitaxy (DBIE), poly-Si gate melt-down and recrystallization, severe damage in Si substrate and total epitaxy of poly-Si gate and Si substrate of the entire transistor are among the common microstructural damages observed in MOSFETs after hard breakdowns in gate oxides (Gox) were observed electrically. The type of catastrophic failures and its degree of damage are found to be strongly dependent on the allowable current density and total resistance of the breakdown path during the breakdown transient. The physical analysis data from TEM analysis allow us to establish the sequence of the physical damages associated with the Gox HBD in transistors. The proposed model is able to predict the next possible microstructural damage induced by HBD.","PeriodicalId":266326,"journal":{"name":"Proceedings of the 10th International Symposium on the Physical and Failure Analysis of Integrated Circuits. IPFA 2003","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2003-07-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123223590","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-07-07DOI: 10.1109/IPFA.2003.1222754
D. Chong, W. Yoo, C. Lek
Plasma process induced damage on rapid thermal nitrided oxide (RTNO) and decoupled plasma nitrided oxide (DPNO) gate dielectrics are evaluated. It is found that the level of plasma induced damage on DPNO is comparable to that of RTNO. Hence, we can conclude that the decoupled plasma nitridation (DPN) process does not introduce significant damage to the silicon dioxide gate dielectric. We also discovered that RTNO fares better than DPNO in term of plasma charging damage immunity when both gate dielectrics are subjected to simulated plasma charging stresses.
{"title":"Plasma charging damage immunities of rapid thermal nitrided oxide and decoupled plasma nitrided oxide","authors":"D. Chong, W. Yoo, C. Lek","doi":"10.1109/IPFA.2003.1222754","DOIUrl":"https://doi.org/10.1109/IPFA.2003.1222754","url":null,"abstract":"Plasma process induced damage on rapid thermal nitrided oxide (RTNO) and decoupled plasma nitrided oxide (DPNO) gate dielectrics are evaluated. It is found that the level of plasma induced damage on DPNO is comparable to that of RTNO. Hence, we can conclude that the decoupled plasma nitridation (DPN) process does not introduce significant damage to the silicon dioxide gate dielectric. We also discovered that RTNO fares better than DPNO in term of plasma charging damage immunity when both gate dielectrics are subjected to simulated plasma charging stresses.","PeriodicalId":266326,"journal":{"name":"Proceedings of the 10th International Symposium on the Physical and Failure Analysis of Integrated Circuits. IPFA 2003","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2003-07-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127825504","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-07-07DOI: 10.1109/IPFA.2003.1222713
V. Samper, A. Trigg
MEMS devices offer great potential benefits as sensors and actuators. By using and modifying the fabrication techniques originally developed for integrated circuits, microscopic devices can be formed which match or exceed the performance of their conventional counterparts in a smaller volume with lower weight and a greatly reduced cost. There are however considerable challenges in fabricating and packaging such devices and, in particular, there are many yield and reliability issues to be overcome. Some of the failure mechanisms are similar to those encountered in conventional integrated circuits while others are unique to MEMS devices. These failure mechanisms will be discussed and case studies used to illustrate some of the unique issues that need to be addressed.
{"title":"MEMS failure analysis and reliability","authors":"V. Samper, A. Trigg","doi":"10.1109/IPFA.2003.1222713","DOIUrl":"https://doi.org/10.1109/IPFA.2003.1222713","url":null,"abstract":"MEMS devices offer great potential benefits as sensors and actuators. By using and modifying the fabrication techniques originally developed for integrated circuits, microscopic devices can be formed which match or exceed the performance of their conventional counterparts in a smaller volume with lower weight and a greatly reduced cost. There are however considerable challenges in fabricating and packaging such devices and, in particular, there are many yield and reliability issues to be overcome. Some of the failure mechanisms are similar to those encountered in conventional integrated circuits while others are unique to MEMS devices. These failure mechanisms will be discussed and case studies used to illustrate some of the unique issues that need to be addressed.","PeriodicalId":266326,"journal":{"name":"Proceedings of the 10th International Symposium on the Physical and Failure Analysis of Integrated Circuits. IPFA 2003","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2003-07-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130039358","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-07-07DOI: 10.1109/IPFA.2003.1222714
W.F. Sun, L. Shi
A novel high-reliability HV-CMOS (High Voltage CMOS) compatible with 0.6/spl mu/m rules standard Bulk-Silicon (BS) CMOS process was proposed. The reliability of the HV-CMOS is greatly improved by adding the p-well to HV-PMOS (High Voltage PMOS) for etching the unwanted thick-gate-oxide film and that to HV-DNMOS (High Voltage Double-Diffusion NMOS) for preventing punch-through. The breakdown voltage of the presented HV-CMOS exceeds 100 V, which can be used in power driver ICs, etc.
提出了一种新的高可靠性HV-CMOS (High Voltage CMOS)，兼容0.6/spl mu/m规则的标准Bulk-Silicon (BS) CMOS工艺。通过在HV-PMOS(高压PMOS)和HV-DNMOS(高压双扩散NMOS)上添加p阱来蚀刻不需要的厚栅氧化膜，从而大大提高了HV-CMOS的可靠性。所提出的高压cmos击穿电压超过100 V，可用于功率驱动ic等。
{"title":"High reliability HV-CMOS transistors in standard CMOS technology","authors":"W.F. Sun, L. Shi","doi":"10.1109/IPFA.2003.1222714","DOIUrl":"https://doi.org/10.1109/IPFA.2003.1222714","url":null,"abstract":"A novel high-reliability HV-CMOS (High Voltage CMOS) compatible with 0.6/spl mu/m rules standard Bulk-Silicon (BS) CMOS process was proposed. The reliability of the HV-CMOS is greatly improved by adding the p-well to HV-PMOS (High Voltage PMOS) for etching the unwanted thick-gate-oxide film and that to HV-DNMOS (High Voltage Double-Diffusion NMOS) for preventing punch-through. The breakdown voltage of the presented HV-CMOS exceeds 100 V, which can be used in power driver ICs, etc.","PeriodicalId":266326,"journal":{"name":"Proceedings of the 10th International Symposium on the Physical and Failure Analysis of Integrated Circuits. IPFA 2003","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2003-07-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126013353","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-07-07DOI: 10.1109/IPFA.2003.1222745
D. Lu
Amine-induced photoresist poisoning is well known. However, the mechanism for the formation of this amine contamination is still not well understood. In this study, it has been found that wet cleaning of the oxide surface a small amount of hydrocarbons, which are responsible for the gradual accumulation of amine species via airborne molecular contamination.
{"title":"Study of oxide surface contamination using ToF-SIMS","authors":"D. Lu","doi":"10.1109/IPFA.2003.1222745","DOIUrl":"https://doi.org/10.1109/IPFA.2003.1222745","url":null,"abstract":"Amine-induced photoresist poisoning is well known. However, the mechanism for the formation of this amine contamination is still not well understood. In this study, it has been found that wet cleaning of the oxide surface a small amount of hydrocarbons, which are responsible for the gradual accumulation of amine species via airborne molecular contamination.","PeriodicalId":266326,"journal":{"name":"Proceedings of the 10th International Symposium on the Physical and Failure Analysis of Integrated Circuits. IPFA 2003","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2003-07-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114846211","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/IPFA.2003.1222709
Alastair Trigg, Daniel Chan, John Thong
The following topics were dealt: Failure analysis I; reliability and failure analysis in specialist devices; failure analysis II; advanced interconnects I; failure analysis III; packaging related failure mechanisms; advanced interconnects; dielectrics and hot carrier reliability I; dielectrics and hot carrier reliability II; EOS/ESD and CMOS latchup; failure analysis IV; failure analysis V.
{"title":"Proceedings of the 10th International Symposium on the Physical and Failure Analysis of Integrated Circuits. IPFA 2003","authors":"Alastair Trigg, Daniel Chan, John Thong","doi":"10.1109/IPFA.2003.1222709","DOIUrl":"https://doi.org/10.1109/IPFA.2003.1222709","url":null,"abstract":"The following topics were dealt: Failure analysis I; reliability and failure analysis in specialist devices; failure analysis II; advanced interconnects I; failure analysis III; packaging related failure mechanisms; advanced interconnects; dielectrics and hot carrier reliability I; dielectrics and hot carrier reliability II; EOS/ESD and CMOS latchup; failure analysis IV; failure analysis V.","PeriodicalId":266326,"journal":{"name":"Proceedings of the 10th International Symposium on the Physical and Failure Analysis of Integrated Circuits. IPFA 2003","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114162355","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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