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2017 IEEE International Solid-State Circuits Conference (ISSCC)最新文献

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5.3 A 95µW 24MHz digitally controlled crystal oscillator for IoT applications with 36nJ start-up energy and >13× start-up time reduction using a fully-autonomous dynamically-adjusted load 5.3一个95µW 24MHz数字控制晶体振荡器,用于物联网应用,使用全自动动态调节负载,启动能量36nJ,启动时间减少>13倍
Pub Date : 2017-02-01 DOI: 10.1109/ISSCC.2017.7870275
M. Ding, Yao-Hong Liu, Yan Zhang, Chuang Lu, P. Zhang, B. Busze, Christian Bachmann, K. Philips
Wireless sensor nodes (WSN) in IoT applications (e.g., Bluetooth Low Energy, BLE) rely on heavily duty-cycling the wireless transceivers to reduce the overall system power consumption [1]. This requires swift start-up behavior of the transceiver. The crystal oscillator (XO) generates a stable reference clock for the PLL to synthesize a carrier and to derive clocks for all other parts of the transceiver SoC, e.g., ADC and the digital baseband. The typical start-up time (Ts) of an XO is relatively long (∼ms) due to a high quality factor of the crystal quartz. This leads to a significant (up to 30%) power overhead for a highly duty-cycled transceiver with a short packet format, e.g., the packet length is as short as 128µs in BLE (Fig. 5.3.1). A reduction of Ts of the XO is necessary, at the same time, the power overhead to enable a fast start-up should be minimized in order to reduce the overall energy consumption (Fig. 5.3.1).
物联网应用中的无线传感器节点(WSN)(例如,蓝牙低功耗,BLE)严重依赖无线收发器的占空比来降低整体系统功耗[1]。这需要收发器的快速启动行为。晶体振荡器(XO)为锁相环生成稳定的参考时钟,用于合成载波,并为收发器SoC的所有其他部分(例如ADC和数字基带)导出时钟。由于晶体石英的高质量因子,XO的典型启动时间(Ts)相对较长(~ ms)。这将导致具有短数据包格式的高占空比收发器的显著(高达30%)功率开销,例如,在BLE中数据包长度短至128µs(图5.3.1)。降低XO的Ts是必要的,同时,为了降低总体能耗,应该最小化实现快速启动的功率开销(图5.3.1)。
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引用次数: 23
29.3 A 40Gb/s PAM-4 transmitter based on a ring-resonator optical DAC in 45nm SOI CMOS 29.3基于45nm SOI CMOS环形谐振光DAC的40Gb/s PAM-4发射机
Pub Date : 2017-02-01 DOI: 10.1109/ISSCC.2017.7870473
S. Moazeni, Sen Lin, M. Wade, L. Alloatti, Rajeev J Ram, M. Popović, V. Stojanović
Silicon photonics is a rapidly maturing technology, promising to realize low-cost and energy-efficient optical links for rack-to-rack, within-rack datacenter applications, and supercomputer interconnects. Recently, the possibility of implementing ultra-power-efficient silicon photonic links using an unmodified state-of-the-art 45nm SOI CMOS process has been demonstrated [1]. This approach enabled the fabrication of millions of transistors and hundreds of photonic devices in the same chip to improve processor-memory link bandwidth, and opened a path to solving this traditional computation bottleneck.
硅光子学是一项迅速成熟的技术,有望实现低成本和节能的光链路,用于机架到机架、机架内数据中心应用和超级计算机互连。最近,已经证明了使用未经修改的最先进的45nm SOI CMOS工艺实现超节能硅光子链路的可能性[1]。这种方法使得在同一芯片上制造数百万个晶体管和数百个光子器件,从而提高了处理器-存储器链路带宽,为解决这一传统的计算瓶颈开辟了一条道路。
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引用次数: 11
22.4 A reconfigurable bidirectional wireless power transceiver with maximum-current charging mode and 58.6% battery-to-battery efficiency 22.4可重构双向无线电源收发器,最大电流充电模式,电池对电池效率58.6%
Pub Date : 2017-02-01 DOI: 10.1109/ISSCC.2017.7870418
Mo Huang, Yan Lu, U. Seng-Pan, R. Martins
Wireless power transfer (WPT) is currently on the critical point of an explosive growth. Here, as projected in Fig. 22.4.1, we propose a future WPT eco-system of consumer electronics, which includes three layers: 1) wireless charging pads being the fundamental energy plants that can charge a wireless power bank and mobile devices; 2) wireless power banks that get energy from plants and feed mobile devices; and 3) power hungry mobile devices that get energy from all the other sources. To enable the mobile devices charging others without additional hardware, we propose a reconfigurable bidirectional 6.78MHz WPT transceiver (TRX) that reuses the LC resonant tank and 4 area-consuming power transistors for the differential Class-D power amplifier (PA) and the full-wave rectifier. With such WPT TRX embedded, one can provide a first-aid to his/her smart watch or friend's device of which the battery is dying.
无线电力传输(WPT)目前正处于爆炸式增长的临界点。在这里,如图22.4.1所示,我们提出了一个未来的消费电子产品WPT生态系统,它包括三层:1)无线充电板是基本的能源工厂,可以为无线充电宝和移动设备充电;2)从植物获取能量并为移动设备供电的无线充电宝;3)耗电的移动设备从其他所有来源获取能量。为了使移动设备无需额外硬件即可充电,我们提出了一种可重构的双向6.78MHz WPT收发器(TRX),该收发器重复使用LC谐振槽和4个面积消耗功率晶体管作为差分d类功率放大器(PA)和全波整流器。有了这样的WPT TRX,就可以为自己的智能手表或朋友的设备提供电池即将耗尽的急救。
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引用次数: 18
27.7 A 30.5mm3 fully packaged implantable device with duplex ultrasonic data and power links achieving 95kb/s with <10−4 BER at 8.5cm depth 27.7 30.5mm3全封装植入式装置,具有双工超声数据和电源链路,在8.5cm深度下达到95kb/s, BER <10−4
Pub Date : 2017-02-01 DOI: 10.1109/ISSCC.2017.7870460
T. Chang, Max L. Wang, Jayant Charthad, Marcus J. Weber, A. Arbabian
The next generation of implantable medical devices focuses on minimally invasive miniaturized solutions that operate reliably at large depths, provide duplex communication for closed-loop therapies, and enable multi-access for a network of implants to gather information or provide systemic interventions. Using ultrasound (US), power and data can be efficiently transferred through the body as its wavelength at MHz is comparable to a mm-sized receiver, resulting in improved focusing, coupling, and acoustic-to-electrical conversion efficiency. Furthermore, thanks to the low propagation loss (∼1dB/cm/MHz) and 7.2mW/mm2 safety limit, several mW of power is obtainable at the receiver, enabling high-power, complicated functionalities.
下一代植入式医疗设备的重点是微创小型化解决方案,这些解决方案可在大深度可靠地运行,为闭环治疗提供双工通信,并使植入物网络能够进行多通道访问,以收集信息或提供系统干预。利用超声波(US),能量和数据可以有效地通过身体传输,因为其MHz波长与毫米大小的接收器相当,从而改善聚焦、耦合和声电转换效率。此外,由于低传播损耗(约1dB/cm/MHz)和7.2mW/mm2的安全限制,接收器可获得数mW的功率,从而实现高功率,复杂的功能。
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引用次数: 40
9.3 A BJT-based temperature sensor with a packaging-robust inaccuracy of ±0.3°C (3σ) from −55°C to +125°C after heater-assisted voltage calibration 9.3基于bjt的温度传感器,加热辅助电压校准后,在- 55°C至+125°C范围内,封装稳扎性误差为±0.3°C (3σ)
Pub Date : 2017-02-01 DOI: 10.1109/ISSCC.2017.7870311
B. Yousefzadeh, K. Makinwa
This paper presents a BJT-based temperature sensor, which can be accurately trimmed in both ceramic and plastic packages, on the basis of purely electrical measurements at room temperature. This is achieved by combining the voltage-calibration technique from [1] with an on-chip heater, which can heat the sensing BJTs from room temperature to ∼85°C in 0.5s. Measurements show that the sensor can then be trimmed to an inaccuracy of ±0.3°C (3σ) over the military range (−55 to +125°C). This is similar to the inaccuracy obtained after conventional temperature calibration, i.e., at well-defined temperatures, but requires much less calibration time and infrastructure.
本文介绍了一种基于bjt的温度传感器,它可以在室温下的纯电测量基础上精确地在陶瓷和塑料封装中进行修整。这是通过将[1]中的电压校准技术与片上加热器相结合来实现的,该加热器可以在0.5s内将感测bjt从室温加热到~ 85°C。测量表明,传感器可以在军用范围内(- 55至+125°C)修剪到±0.3°C (3σ)的不精度。这与传统温度校准后获得的不准确性相似,即在定义明确的温度下,但需要的校准时间和基础设施要少得多。
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引用次数: 19
24.4 A 0.18V 382µW bluetooth low-energy (BLE) receiver with 1.33nW sleep power for energy-harvesting applications in 28nm CMOS 24.4 A 0.18V 382µW蓝牙低功耗(BLE)接收器,1.33nW休眠功率,用于28nm CMOS的能量收集应用
Pub Date : 2017-02-01 DOI: 10.1109/ISSCC.2017.7870437
Wei-Han Yu, Haidong Yi, Pui-in Mak, Jun Yin, R. Martins
For true mobility, wearable electronics should be self-powered by the environment. On-body thermoelectric (∼50µW/cm2) is a maturing energy source but delivers a deeply low and inconstant output voltage (0.05 to 0.3V) hindering its utility. With the limited power efficiency of ultra-low-voltage (ULV) boost converters (64% in [1]), there is a rising interest in developing ULV radios that can operate directly at the energy-harvester output, reducing the waste of energy and active-sleep latency. The 2.4GHz receiver in [2] validates 0.3V operation, but is a non-standard design without I/Q demodulation. Also, its focus is on the active power (1.6mW) assuming its 0.3V supply is constant.
为了实现真正的移动性,可穿戴电子设备应该能够根据环境自行供电。体上热电(~ 50 μ W/cm2)是一种成熟的能源,但其输出电压极低且不恒定(0.05至0.3V),阻碍了其实用性。由于超低电压(ULV)升压转换器的功率效率有限([1]中为64%),人们对开发可以直接在能量收集器输出处工作的超低电压无线电越来越感兴趣,从而减少了能量浪费和主动睡眠延迟。[2]中的2.4GHz接收器验证了0.3V的工作,但是非标准设计,没有I/Q解调。此外,它的重点是有功功率(1.6mW),假设它的0.3V电源是恒定的。
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引用次数: 29
21.2 A 1.4mΩ-sensitivity 94dB-dynamic-range electrical impedance tomography SoC and 48-channel Hub SoC for 3D lung ventilation monitoring system 21.2用于三维肺通气监测系统的1.4mΩ-sensitivity 94db动态范围电阻抗断层成像SoC和48通道Hub SoC
Pub Date : 2017-02-01 DOI: 10.1109/ISSCC.2017.7870407
Minseo Kim, Hyunki Kim, Jaeeun Jang, Jihee Lee, Jaehyuk Lee, Jiwon Lee, Kyungrog Lee, Kwantae Kim, Yongsu Lee, H. Yoo
Electrical impedance tomography (EIT) has been studied to monitor lung ventilation because it is the only real-time lung imaging method without large equipment [1–2]. However, previous EIT systems just provided 2D cross-sectional image with limited spatial information of the lung and unneglectable volume detection error depending on the location of 2D EIT belt relative to the patient's lung. In spite of its importance, the 3D-EIT has not been realized in lung monitoring because it has many design challenges such as noises incurred by complicated wiring, long cable length, wide variation in electrode contact and signal, and large personal-to-person impedance variation. In this paper, we present a portable 3D-EIT SoC for real-time lung ventilation monitoring with following 5 features: 1) The active electrodes (AEs) system to reduce coupling noise, 2) High output impedance current stimulator to inject stable current, 3) Impedance spectroscopy to enable both time-difference (TD) EIT and frequency-difference (FD) EIT, and to select an optimal frequency for TD-EIT, 4) Wide-dynamic range front-end circuit to detect variable ranges of signal with high-input impedance and CMRR, 5) Calibration to reduce the electrical characteristics variations of AEs.
电阻抗断层扫描(EIT)是唯一一种无需大型设备的实时肺成像方法,因此被研究用于监测肺通气[1-2]。然而,以往的EIT系统仅提供二维横截面图像,肺的空间信息有限,并且依赖于二维EIT带相对于患者肺的位置而产生不可忽视的体积检测误差。尽管3D-EIT很重要,但由于其布线复杂、电缆长度长、电极接触和信号变化大、人与人之间的阻抗变化大等设计难题,3D-EIT尚未在肺部监测中实现。在本文中,我们提出了一种用于实时肺通气监测的便携式3D-EIT SoC,具有以下5个特点:1)主动电极(AEs)系统降低耦合噪声;2)高输出阻抗电流刺激器注入稳定电流;3)阻抗谱法实现时差(TD)和频差(FD) EIT,并为TD-EIT选择最佳频率;4)宽动态范围前端电路检测具有高输入阻抗和CMRR的可变范围信号;5)校准以减少AEs的电特性变化。
{"title":"21.2 A 1.4mΩ-sensitivity 94dB-dynamic-range electrical impedance tomography SoC and 48-channel Hub SoC for 3D lung ventilation monitoring system","authors":"Minseo Kim, Hyunki Kim, Jaeeun Jang, Jihee Lee, Jaehyuk Lee, Jiwon Lee, Kyungrog Lee, Kwantae Kim, Yongsu Lee, H. Yoo","doi":"10.1109/ISSCC.2017.7870407","DOIUrl":"https://doi.org/10.1109/ISSCC.2017.7870407","url":null,"abstract":"Electrical impedance tomography (EIT) has been studied to monitor lung ventilation because it is the only real-time lung imaging method without large equipment [1–2]. However, previous EIT systems just provided 2D cross-sectional image with limited spatial information of the lung and unneglectable volume detection error depending on the location of 2D EIT belt relative to the patient's lung. In spite of its importance, the 3D-EIT has not been realized in lung monitoring because it has many design challenges such as noises incurred by complicated wiring, long cable length, wide variation in electrode contact and signal, and large personal-to-person impedance variation. In this paper, we present a portable 3D-EIT SoC for real-time lung ventilation monitoring with following 5 features: 1) The active electrodes (AEs) system to reduce coupling noise, 2) High output impedance current stimulator to inject stable current, 3) Impedance spectroscopy to enable both time-difference (TD) EIT and frequency-difference (FD) EIT, and to select an optimal frequency for TD-EIT, 4) Wide-dynamic range front-end circuit to detect variable ranges of signal with high-input impedance and CMRR, 5) Calibration to reduce the electrical characteristics variations of AEs.","PeriodicalId":269679,"journal":{"name":"2017 IEEE International Solid-State Circuits Conference (ISSCC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133175460","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
11.4 A 512Gb 3b/cell 64-stacked WL 3D V-NAND flash memory 11.4 512Gb 3b/cell 64堆叠WL 3D V-NAND闪存
Pub Date : 2017-02-01 DOI: 10.1109/ISSCC.2017.7870331
Chulbum Kim, Ji-Ho Cho, Woopyo Jeong, I. Park, Hyun-wook Park, Doo-Hyun Kim, D. Kang, Sunghoon Lee, Ji-Sang Lee, Wontae Kim, Jiyoon Park, Yang-Lo Ahn, Jiyoung Lee, Jonghoon Lee, Seungbum Kim, Hyun-Jun Yoon, Jaedoeg Yu, Nayoung Choi, Yelim Kwon, Nahyun Kim, Hwajun Jang, Jong-Yeol Park, Seunghwan Song, Yongha Park, Jinbae Bang, Sangki Hong, B. Jeong, Hyun-Jin Kim, Chunan Lee, Young-Sun Min, Inryul Lee, In-Mo Kim, Sung-Hoon Kim, Dongkyu Yoon, KiSeung Kim, Youngdon Choi, Moosung Kim, Hyunggon Kim, Pansuk Kwak, Jeong-Don Ihm, D. Byeon, Jin-Yub Lee, Ki-Tae Park, K. Kyung
The advent of emerging technologies such as cloud computing, big data, the internet of things and mobile computing is producing a tremendous amount of data. In the era of big data, storage devices with versatile characteristics are required for ultra-fast processing, higher capacity storage, lower cost, and lower power operation. SSDs employing 3D NAND are a promising to meet these requirements. Since the introduction of 3D NAND technology to marketplace in 2014 [1], the memory array size has nearly doubled every year [2,3]. To continue scaling 3D NAND array density, it is essential to scale down vertically to minimize total mold height. However, vertical scaling results in critical problems such as increasing WL capacitance and non-uniformity of stacked WLs due to variation in the channel hole diameter. To tackle these issues, this work proposes schemes for programming speed improvement and power reduction, and on-chip processing algorithms for error correction.
云计算、大数据、物联网、移动计算等新兴技术不断涌现,产生了海量数据。在大数据时代,对具有多用途特性的存储设备提出了超快处理、高容量存储、低成本、低功耗的要求。采用3D NAND的固态硬盘有望满足这些要求。自2014年3D NAND技术推出以来[1],存储器阵列的尺寸几乎每年翻一番[2,3]。为了继续缩放3D NAND阵列密度,必须垂直缩放以最小化总模具高度。然而,由于通道孔径的变化,垂直缩放会导致WL电容的增加和堆叠WL的不均匀性等关键问题。为了解决这些问题,本工作提出了提高编程速度和降低功耗的方案,以及用于纠错的片上处理算法。
{"title":"11.4 A 512Gb 3b/cell 64-stacked WL 3D V-NAND flash memory","authors":"Chulbum Kim, Ji-Ho Cho, Woopyo Jeong, I. Park, Hyun-wook Park, Doo-Hyun Kim, D. Kang, Sunghoon Lee, Ji-Sang Lee, Wontae Kim, Jiyoon Park, Yang-Lo Ahn, Jiyoung Lee, Jonghoon Lee, Seungbum Kim, Hyun-Jun Yoon, Jaedoeg Yu, Nayoung Choi, Yelim Kwon, Nahyun Kim, Hwajun Jang, Jong-Yeol Park, Seunghwan Song, Yongha Park, Jinbae Bang, Sangki Hong, B. Jeong, Hyun-Jin Kim, Chunan Lee, Young-Sun Min, Inryul Lee, In-Mo Kim, Sung-Hoon Kim, Dongkyu Yoon, KiSeung Kim, Youngdon Choi, Moosung Kim, Hyunggon Kim, Pansuk Kwak, Jeong-Don Ihm, D. Byeon, Jin-Yub Lee, Ki-Tae Park, K. Kyung","doi":"10.1109/ISSCC.2017.7870331","DOIUrl":"https://doi.org/10.1109/ISSCC.2017.7870331","url":null,"abstract":"The advent of emerging technologies such as cloud computing, big data, the internet of things and mobile computing is producing a tremendous amount of data. In the era of big data, storage devices with versatile characteristics are required for ultra-fast processing, higher capacity storage, lower cost, and lower power operation. SSDs employing 3D NAND are a promising to meet these requirements. Since the introduction of 3D NAND technology to marketplace in 2014 [1], the memory array size has nearly doubled every year [2,3]. To continue scaling 3D NAND array density, it is essential to scale down vertically to minimize total mold height. However, vertical scaling results in critical problems such as increasing WL capacitance and non-uniformity of stacked WLs due to variation in the channel hole diameter. To tackle these issues, this work proposes schemes for programming speed improvement and power reduction, and on-chip processing algorithms for error correction.","PeriodicalId":269679,"journal":{"name":"2017 IEEE International Solid-State Circuits Conference (ISSCC)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133183200","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 59
4.1 A 640×480 dynamic vision sensor with a 9µm pixel and 300Meps address-event representation 4.1 640×480动态视觉传感器,9µm像素,300Meps地址事件表示
Pub Date : 2017-02-01 DOI: 10.1109/ISSCC.2017.7870263
Bongki Son, Yunjae Suh, Sungho Kim, Heejae Jung, Jun-Seok Kim, Chang-Woo Shin, Keunju Park, Kyoobin Lee, Jin Man Park, J. Woo, Yohan J. Roh, Hyunku Lee, Y. Wang, I. Ovsiannikov, H. Ryu
We report a VGA dynamic vision sensor (DVS) with a 9µm pixel, developed through a digital as well as an analog implementation. DVS systems in the literature try to increase spatial resolution up to QVGA [1–2] and data rates up to 50 million events per second (Meps) (self-acknowledged) [3], but they are still inadequate for high-performance applications such as gesture recognition, drones, automotive, etc. Moreover, the smallest reported pixel of 18.5µm is too large for economical mass production [3]. This paper reports a 640×480 VGA-resolution DVS system with a 9µm pixel pitch supporting a data rate of 300Meps for sufficient event transfer in spite of higher resolution. Maintaining acceptable pixel performance, the pixel circuitry is carefully designed and optimized using a BSI CIS process. To acquire data (i.e., pixel events) at high speed even with high resolution (e.g., VGA), a fully synthesized word-serial group address-event representation (G-AER) is implemented, which handles massive events in parallel by binding neighboring 8 pixels into a group. In addition, a 10b programmable bias generator dedicated to a DVS system provides easy controllability of pixel biases and event thresholds.
我们报告了一种9µm像素的VGA动态视觉传感器(DVS),通过数字和模拟实现开发。文献中的分布式交换机系统试图将空间分辨率提高到QVGA[1-2],数据速率高达每秒5000万事件(Meps)(自我承认)[3],但它们仍然不足以用于高性能应用,如手势识别、无人机、汽车等。此外,最小的报道像素为18.5µm,对于经济批量生产来说太大了[3]。本文报道了一个640×480 vga分辨率分布式交换机系统,其像素间距为9µm,支持300Meps的数据速率,尽管分辨率更高,但仍能实现足够的事件传输。保持可接受的像素性能,像素电路是精心设计和优化使用BSI CIS过程。为了在高分辨率(如VGA)下高速获取数据(即像素事件),实现了一种完全合成的字串行组地址事件表示(G-AER),它通过将相邻的8个像素绑定到一个组中并行处理大量事件。此外,专用于分布式交换机系统的10b可编程偏置发生器提供了易于控制的像素偏置和事件阈值。
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引用次数: 136
27.6 Single-chip 3072ch 2D array IC with RX analog and all-digital TX beamformer for 3D ultrasound imaging 27.6单片3072ch 2D阵列IC,带有RX模拟和全数字TX波束形成器,用于3D超声成像
Pub Date : 2017-02-01 DOI: 10.1109/ISSCC.2017.7870459
Y. Katsube, Shinya Kajiyama, Takuma Nishimoto, T. Nakagawa, Yasuyuki Okuma, Yohei Nakamura, T. Terada, Yutaka Igarashi, T. Yamawaki, T. Yazaki, Y. Hayashi, Kazuhiro Amino, Takuya Kaneko, Hiroki Tanaka
A diagnostic ultrasound (US) system transmits acoustic waves at several to tens of MHz into the human body for clinical purposes and detects the reflected waves to observe the internal organs without having a medical operation or radiation exposure. The system is composed of a main unit and probe connected via coaxial cables. The probe is very small because medical technicians laboriously grab and manipulate it for a long time. To avoid image obscurity depending on medical technicians, high-speed and high-resolution 3D/4D imaging is necessary. For this reason, several thousands of lead bulk piezoelectric material transducers (TD) need to be squeezed into the small probe. Since the number of cables is limited to several hundreds, the probe needs to include beamforming functionality and a 2D array IC [1–6], which includes thousands of US transceivers.
诊断超声(US)系统将几至几十兆赫的声波传输到人体,用于临床目的,并检测反射波以观察内部器官,而无需医疗手术或辐射暴露。该系统由一个主单元和通过同轴电缆连接的探头组成。由于医疗技术人员需要长时间费力地抓取和操作探针,因此探针非常小。为了避免医疗技术人员的图像模糊,需要高速和高分辨率的3D/4D成像。为此,需要将数千个铅块压电材料换能器(TD)压缩到小探头中。由于电缆的数量限制在几百条,探头需要包括波束形成功能和一个2D阵列IC[1-6],其中包括数千个美国收发器。
{"title":"27.6 Single-chip 3072ch 2D array IC with RX analog and all-digital TX beamformer for 3D ultrasound imaging","authors":"Y. Katsube, Shinya Kajiyama, Takuma Nishimoto, T. Nakagawa, Yasuyuki Okuma, Yohei Nakamura, T. Terada, Yutaka Igarashi, T. Yamawaki, T. Yazaki, Y. Hayashi, Kazuhiro Amino, Takuya Kaneko, Hiroki Tanaka","doi":"10.1109/ISSCC.2017.7870459","DOIUrl":"https://doi.org/10.1109/ISSCC.2017.7870459","url":null,"abstract":"A diagnostic ultrasound (US) system transmits acoustic waves at several to tens of MHz into the human body for clinical purposes and detects the reflected waves to observe the internal organs without having a medical operation or radiation exposure. The system is composed of a main unit and probe connected via coaxial cables. The probe is very small because medical technicians laboriously grab and manipulate it for a long time. To avoid image obscurity depending on medical technicians, high-speed and high-resolution 3D/4D imaging is necessary. For this reason, several thousands of lead bulk piezoelectric material transducers (TD) need to be squeezed into the small probe. Since the number of cables is limited to several hundreds, the probe needs to include beamforming functionality and a 2D array IC [1–6], which includes thousands of US transceivers.","PeriodicalId":269679,"journal":{"name":"2017 IEEE International Solid-State Circuits Conference (ISSCC)","volume":"160 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127670265","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
期刊
2017 IEEE International Solid-State Circuits Conference (ISSCC)
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