Pub Date : 2017-02-01DOI: 10.1109/ISSCC.2017.7870474
Ashwin Ramachandran, A. Natarajan, Tejasvi Anand
Asymmetric links such as memory interfaces and display drivers require the transmitter to perform necessary equalization, while the receiver remains simple and has minimal or no equalization capability. Traditionally, FFE-based equalization techniques on power-efficient voltage-mode drivers have been used on the transmit end. Based on the FFE tap resolution requirement, the output driver and pre-driver are divided into multiple segments. Although such a segmented FFE implementation helps to maintain a constant output termination impedance (50Ω) across all tap settings, it comes at the cost of (a) increased signaling power, and (b) increased switching power since multiple segments are required to achieve desired linearity [1]. Phase domain equalization techniques, such as pulse width modulation (PWM), can equalize the channel without increasing signaling power or segmenting the output driver. However, PWM encoding requires the insertion of a precise narrow pulse in every data bit, which necessitates very wide bandwidth in the high-speed data path, resulting in poor energy efficiency [2] and difficulty in scaling PWM encoding to higher data rates [3]. For example, creating a 10% duty cycle on a 64Gb/s PWM data stream would require a pulse width of 1.5ps with less than 1ps of rise/fall time at the transmitter output. Other phase domain pre-emphasis techniques are ineffective for high-loss channels [4]. In view of these limitations, we present a new phase-domain equalization technique: integrated pulse width modulation (iPWM) in a 16Gb/s transceiver, which can equalize 19dB of channel loss, while consuming 57.3mW power. Compared to state-of-the-art PWM designs, the proposed iPWM scheme achieves 36× better energy efficiency for the same data rate [2], and 3.2× higher data rate for the same energy efficiency [3].
{"title":"29.4 A 16Gb/s 3.6pJ/b wireline transceiver with phase domain equalization scheme: Integrated pulse width modulation (iPWM) in 65nm CMOS","authors":"Ashwin Ramachandran, A. Natarajan, Tejasvi Anand","doi":"10.1109/ISSCC.2017.7870474","DOIUrl":"https://doi.org/10.1109/ISSCC.2017.7870474","url":null,"abstract":"Asymmetric links such as memory interfaces and display drivers require the transmitter to perform necessary equalization, while the receiver remains simple and has minimal or no equalization capability. Traditionally, FFE-based equalization techniques on power-efficient voltage-mode drivers have been used on the transmit end. Based on the FFE tap resolution requirement, the output driver and pre-driver are divided into multiple segments. Although such a segmented FFE implementation helps to maintain a constant output termination impedance (50Ω) across all tap settings, it comes at the cost of (a) increased signaling power, and (b) increased switching power since multiple segments are required to achieve desired linearity [1]. Phase domain equalization techniques, such as pulse width modulation (PWM), can equalize the channel without increasing signaling power or segmenting the output driver. However, PWM encoding requires the insertion of a precise narrow pulse in every data bit, which necessitates very wide bandwidth in the high-speed data path, resulting in poor energy efficiency [2] and difficulty in scaling PWM encoding to higher data rates [3]. For example, creating a 10% duty cycle on a 64Gb/s PWM data stream would require a pulse width of 1.5ps with less than 1ps of rise/fall time at the transmitter output. Other phase domain pre-emphasis techniques are ineffective for high-loss channels [4]. In view of these limitations, we present a new phase-domain equalization technique: integrated pulse width modulation (iPWM) in a 16Gb/s transceiver, which can equalize 19dB of channel loss, while consuming 57.3mW power. Compared to state-of-the-art PWM designs, the proposed iPWM scheme achieves 36× better energy efficiency for the same data rate [2], and 3.2× higher data rate for the same energy efficiency [3].","PeriodicalId":269679,"journal":{"name":"2017 IEEE International Solid-State Circuits Conference (ISSCC)","volume":"69 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130538558","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-02-01DOI: 10.1109/ISSCC.2017.7870460
T. Chang, Max L. Wang, Jayant Charthad, Marcus J. Weber, A. Arbabian
The next generation of implantable medical devices focuses on minimally invasive miniaturized solutions that operate reliably at large depths, provide duplex communication for closed-loop therapies, and enable multi-access for a network of implants to gather information or provide systemic interventions. Using ultrasound (US), power and data can be efficiently transferred through the body as its wavelength at MHz is comparable to a mm-sized receiver, resulting in improved focusing, coupling, and acoustic-to-electrical conversion efficiency. Furthermore, thanks to the low propagation loss (∼1dB/cm/MHz) and 7.2mW/mm2 safety limit, several mW of power is obtainable at the receiver, enabling high-power, complicated functionalities.
{"title":"27.7 A 30.5mm3 fully packaged implantable device with duplex ultrasonic data and power links achieving 95kb/s with <10−4 BER at 8.5cm depth","authors":"T. Chang, Max L. Wang, Jayant Charthad, Marcus J. Weber, A. Arbabian","doi":"10.1109/ISSCC.2017.7870460","DOIUrl":"https://doi.org/10.1109/ISSCC.2017.7870460","url":null,"abstract":"The next generation of implantable medical devices focuses on minimally invasive miniaturized solutions that operate reliably at large depths, provide duplex communication for closed-loop therapies, and enable multi-access for a network of implants to gather information or provide systemic interventions. Using ultrasound (US), power and data can be efficiently transferred through the body as its wavelength at MHz is comparable to a mm-sized receiver, resulting in improved focusing, coupling, and acoustic-to-electrical conversion efficiency. Furthermore, thanks to the low propagation loss (∼1dB/cm/MHz) and 7.2mW/mm2 safety limit, several mW of power is obtainable at the receiver, enabling high-power, complicated functionalities.","PeriodicalId":269679,"journal":{"name":"2017 IEEE International Solid-State Circuits Conference (ISSCC)","volume":"72 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127340510","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-02-01DOI: 10.1109/ISSCC.2017.7870458
Man-Chia Chen, A. Perez, Sri-Rajasekhar Kothapalli, P. Cathelin, A. Cathelin, S. Gambhir, B. Murmann
A variety of emerging applications in medical ultrasound rely on 3D volumetric imaging, calling for dense 2D transducer arrays with thousands of elements. Due to this high channel count, the traditional per-element cable interface used for 1D arrays is no longer viable. To address this issue, recent work has proven the viability of flip-chip bonding [1] or direct transducer integration [2]. This shifts the burden to a CMOS substrate, which must provide dense signal conditioning and processing before the massively parallel image data can be pushed off chip. A common approach for data reduction is to employ subarray beamforming (BF), which applies delay and sum operations within a group of pixels. To implement such functionality within the tight pixel pitch, prior works have implemented the delays using simple S/H circuits [2] or analog filters [3], and typically suffer from a combination of issues related to limited delay, coarse delay resolution and limited SNR.
{"title":"27.5 A pixel-pitch-matched ultrasound receiver for 3D photoacoustic imaging with integrated delta-sigma beamformer in 28nm UTBB FDSOI","authors":"Man-Chia Chen, A. Perez, Sri-Rajasekhar Kothapalli, P. Cathelin, A. Cathelin, S. Gambhir, B. Murmann","doi":"10.1109/ISSCC.2017.7870458","DOIUrl":"https://doi.org/10.1109/ISSCC.2017.7870458","url":null,"abstract":"A variety of emerging applications in medical ultrasound rely on 3D volumetric imaging, calling for dense 2D transducer arrays with thousands of elements. Due to this high channel count, the traditional per-element cable interface used for 1D arrays is no longer viable. To address this issue, recent work has proven the viability of flip-chip bonding [1] or direct transducer integration [2]. This shifts the burden to a CMOS substrate, which must provide dense signal conditioning and processing before the massively parallel image data can be pushed off chip. A common approach for data reduction is to employ subarray beamforming (BF), which applies delay and sum operations within a group of pixels. To implement such functionality within the tight pixel pitch, prior works have implemented the delays using simple S/H circuits [2] or analog filters [3], and typically suffer from a combination of issues related to limited delay, coarse delay resolution and limited SNR.","PeriodicalId":269679,"journal":{"name":"2017 IEEE International Solid-State Circuits Conference (ISSCC)","volume":"244 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122636964","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-02-01DOI: 10.1109/ISSCC.2017.7870316
Hui Jiang, K. Makinwa, S. Nihtianov
Wheatstone bridge sensors are often used in precision instrumentation and measurement systems, e.g., for μK-resolution temperature sensing in wafer steppers [1] and mPa-resolution differential pressure sensing in precision air gauges [2]. Since they output small differential signals superimposed on a large common-mode (CM) voltage, typical bridge readout ICs (ROICs) consist of an instrumentation amplifier (IA) followed by an ADC [1]. This paper describes a low-noise energy-efficient ROIC, which achieves a 3.7nV/√Hz input-referred noise PSD and a power efficiency factor (PEF) of 44.1. The latter represents a 5× improvement on the state of the art [3].
{"title":"9.8 An energy-efficient 3.7nV/√Hz bridge-readout IC with a stable bridge offset compensation scheme","authors":"Hui Jiang, K. Makinwa, S. Nihtianov","doi":"10.1109/ISSCC.2017.7870316","DOIUrl":"https://doi.org/10.1109/ISSCC.2017.7870316","url":null,"abstract":"Wheatstone bridge sensors are often used in precision instrumentation and measurement systems, e.g., for μK-resolution temperature sensing in wafer steppers [1] and mPa-resolution differential pressure sensing in precision air gauges [2]. Since they output small differential signals superimposed on a large common-mode (CM) voltage, typical bridge readout ICs (ROICs) consist of an instrumentation amplifier (IA) followed by an ADC [1]. This paper describes a low-noise energy-efficient ROIC, which achieves a 3.7nV/√Hz input-referred noise PSD and a power efficiency factor (PEF) of 44.1. The latter represents a 5× improvement on the state of the art [3].","PeriodicalId":269679,"journal":{"name":"2017 IEEE International Solid-State Circuits Conference (ISSCC)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125783409","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-02-01DOI: 10.1109/ISSCC.2017.7870247
D. Chowdhury, Sraavan R. Mundlapudi, A. Afsahi
Envelope tracking (ET) has become popular for enhancing battery life in mobile communication devices that employ high peak-to-average power ratio (PAPR) signals. Most of the published ET systems have focused either on narrow-bandwidth standards, 20MHz WLAN, or LTE [1–3]. However, as the demand for higher bandwidths and data-rates increases, so does the need for wideband ET solutions. Furthermore, to support modulations with different PAPR and transmit powers, the PA will likely require seamless switching between a continuous ET mode and a fixed-supply mode (as with a low drop-out regulator, i.e. a LDO). Hence, fast reconfigurability is needed, which most published ET systems lack. This paper describes a fully integrated, reconfigurable WLAN ET system with digital baseband in a 28nm CMOS technology for bandwidths up to 40MHz. The ET modulator directly interfaces with a battery (Vbat) and is fully integrated within a complete WLAN transceiver with RF, digital, and frequency synthesizer circuitry.
{"title":"2.2 A fully integrated reconfigurable wideband envelope-tracking SoC for high-bandwidth WLAN applications in a 28nm CMOS technology","authors":"D. Chowdhury, Sraavan R. Mundlapudi, A. Afsahi","doi":"10.1109/ISSCC.2017.7870247","DOIUrl":"https://doi.org/10.1109/ISSCC.2017.7870247","url":null,"abstract":"Envelope tracking (ET) has become popular for enhancing battery life in mobile communication devices that employ high peak-to-average power ratio (PAPR) signals. Most of the published ET systems have focused either on narrow-bandwidth standards, 20MHz WLAN, or LTE [1–3]. However, as the demand for higher bandwidths and data-rates increases, so does the need for wideband ET solutions. Furthermore, to support modulations with different PAPR and transmit powers, the PA will likely require seamless switching between a continuous ET mode and a fixed-supply mode (as with a low drop-out regulator, i.e. a LDO). Hence, fast reconfigurability is needed, which most published ET systems lack. This paper describes a fully integrated, reconfigurable WLAN ET system with digital baseband in a 28nm CMOS technology for bandwidths up to 40MHz. The ET modulator directly interfaces with a battery (Vbat) and is fully integrated within a complete WLAN transceiver with RF, digital, and frequency synthesizer circuitry.","PeriodicalId":269679,"journal":{"name":"2017 IEEE International Solid-State Circuits Conference (ISSCC)","volume":"217 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123025116","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-02-01DOI: 10.1109/ISSCC.2017.7870418
Mo Huang, Yan Lu, U. Seng-Pan, R. Martins
Wireless power transfer (WPT) is currently on the critical point of an explosive growth. Here, as projected in Fig. 22.4.1, we propose a future WPT eco-system of consumer electronics, which includes three layers: 1) wireless charging pads being the fundamental energy plants that can charge a wireless power bank and mobile devices; 2) wireless power banks that get energy from plants and feed mobile devices; and 3) power hungry mobile devices that get energy from all the other sources. To enable the mobile devices charging others without additional hardware, we propose a reconfigurable bidirectional 6.78MHz WPT transceiver (TRX) that reuses the LC resonant tank and 4 area-consuming power transistors for the differential Class-D power amplifier (PA) and the full-wave rectifier. With such WPT TRX embedded, one can provide a first-aid to his/her smart watch or friend's device of which the battery is dying.
{"title":"22.4 A reconfigurable bidirectional wireless power transceiver with maximum-current charging mode and 58.6% battery-to-battery efficiency","authors":"Mo Huang, Yan Lu, U. Seng-Pan, R. Martins","doi":"10.1109/ISSCC.2017.7870418","DOIUrl":"https://doi.org/10.1109/ISSCC.2017.7870418","url":null,"abstract":"Wireless power transfer (WPT) is currently on the critical point of an explosive growth. Here, as projected in Fig. 22.4.1, we propose a future WPT eco-system of consumer electronics, which includes three layers: 1) wireless charging pads being the fundamental energy plants that can charge a wireless power bank and mobile devices; 2) wireless power banks that get energy from plants and feed mobile devices; and 3) power hungry mobile devices that get energy from all the other sources. To enable the mobile devices charging others without additional hardware, we propose a reconfigurable bidirectional 6.78MHz WPT transceiver (TRX) that reuses the LC resonant tank and 4 area-consuming power transistors for the differential Class-D power amplifier (PA) and the full-wave rectifier. With such WPT TRX embedded, one can provide a first-aid to his/her smart watch or friend's device of which the battery is dying.","PeriodicalId":269679,"journal":{"name":"2017 IEEE International Solid-State Circuits Conference (ISSCC)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127129933","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-02-01DOI: 10.1109/ISSCC.2017.7870407
Minseo Kim, Hyunki Kim, Jaeeun Jang, Jihee Lee, Jaehyuk Lee, Jiwon Lee, Kyungrog Lee, Kwantae Kim, Yongsu Lee, H. Yoo
Electrical impedance tomography (EIT) has been studied to monitor lung ventilation because it is the only real-time lung imaging method without large equipment [1–2]. However, previous EIT systems just provided 2D cross-sectional image with limited spatial information of the lung and unneglectable volume detection error depending on the location of 2D EIT belt relative to the patient's lung. In spite of its importance, the 3D-EIT has not been realized in lung monitoring because it has many design challenges such as noises incurred by complicated wiring, long cable length, wide variation in electrode contact and signal, and large personal-to-person impedance variation. In this paper, we present a portable 3D-EIT SoC for real-time lung ventilation monitoring with following 5 features: 1) The active electrodes (AEs) system to reduce coupling noise, 2) High output impedance current stimulator to inject stable current, 3) Impedance spectroscopy to enable both time-difference (TD) EIT and frequency-difference (FD) EIT, and to select an optimal frequency for TD-EIT, 4) Wide-dynamic range front-end circuit to detect variable ranges of signal with high-input impedance and CMRR, 5) Calibration to reduce the electrical characteristics variations of AEs.
{"title":"21.2 A 1.4mΩ-sensitivity 94dB-dynamic-range electrical impedance tomography SoC and 48-channel Hub SoC for 3D lung ventilation monitoring system","authors":"Minseo Kim, Hyunki Kim, Jaeeun Jang, Jihee Lee, Jaehyuk Lee, Jiwon Lee, Kyungrog Lee, Kwantae Kim, Yongsu Lee, H. Yoo","doi":"10.1109/ISSCC.2017.7870407","DOIUrl":"https://doi.org/10.1109/ISSCC.2017.7870407","url":null,"abstract":"Electrical impedance tomography (EIT) has been studied to monitor lung ventilation because it is the only real-time lung imaging method without large equipment [1–2]. However, previous EIT systems just provided 2D cross-sectional image with limited spatial information of the lung and unneglectable volume detection error depending on the location of 2D EIT belt relative to the patient's lung. In spite of its importance, the 3D-EIT has not been realized in lung monitoring because it has many design challenges such as noises incurred by complicated wiring, long cable length, wide variation in electrode contact and signal, and large personal-to-person impedance variation. In this paper, we present a portable 3D-EIT SoC for real-time lung ventilation monitoring with following 5 features: 1) The active electrodes (AEs) system to reduce coupling noise, 2) High output impedance current stimulator to inject stable current, 3) Impedance spectroscopy to enable both time-difference (TD) EIT and frequency-difference (FD) EIT, and to select an optimal frequency for TD-EIT, 4) Wide-dynamic range front-end circuit to detect variable ranges of signal with high-input impedance and CMRR, 5) Calibration to reduce the electrical characteristics variations of AEs.","PeriodicalId":269679,"journal":{"name":"2017 IEEE International Solid-State Circuits Conference (ISSCC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133175460","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-02-01DOI: 10.1109/ISSCC.2017.7870331
Chulbum Kim, Ji-Ho Cho, Woopyo Jeong, I. Park, Hyun-wook Park, Doo-Hyun Kim, D. Kang, Sunghoon Lee, Ji-Sang Lee, Wontae Kim, Jiyoon Park, Yang-Lo Ahn, Jiyoung Lee, Jonghoon Lee, Seungbum Kim, Hyun-Jun Yoon, Jaedoeg Yu, Nayoung Choi, Yelim Kwon, Nahyun Kim, Hwajun Jang, Jong-Yeol Park, Seunghwan Song, Yongha Park, Jinbae Bang, Sangki Hong, B. Jeong, Hyun-Jin Kim, Chunan Lee, Young-Sun Min, Inryul Lee, In-Mo Kim, Sung-Hoon Kim, Dongkyu Yoon, KiSeung Kim, Youngdon Choi, Moosung Kim, Hyunggon Kim, Pansuk Kwak, Jeong-Don Ihm, D. Byeon, Jin-Yub Lee, Ki-Tae Park, K. Kyung
The advent of emerging technologies such as cloud computing, big data, the internet of things and mobile computing is producing a tremendous amount of data. In the era of big data, storage devices with versatile characteristics are required for ultra-fast processing, higher capacity storage, lower cost, and lower power operation. SSDs employing 3D NAND are a promising to meet these requirements. Since the introduction of 3D NAND technology to marketplace in 2014 [1], the memory array size has nearly doubled every year [2,3]. To continue scaling 3D NAND array density, it is essential to scale down vertically to minimize total mold height. However, vertical scaling results in critical problems such as increasing WL capacitance and non-uniformity of stacked WLs due to variation in the channel hole diameter. To tackle these issues, this work proposes schemes for programming speed improvement and power reduction, and on-chip processing algorithms for error correction.
{"title":"11.4 A 512Gb 3b/cell 64-stacked WL 3D V-NAND flash memory","authors":"Chulbum Kim, Ji-Ho Cho, Woopyo Jeong, I. Park, Hyun-wook Park, Doo-Hyun Kim, D. Kang, Sunghoon Lee, Ji-Sang Lee, Wontae Kim, Jiyoon Park, Yang-Lo Ahn, Jiyoung Lee, Jonghoon Lee, Seungbum Kim, Hyun-Jun Yoon, Jaedoeg Yu, Nayoung Choi, Yelim Kwon, Nahyun Kim, Hwajun Jang, Jong-Yeol Park, Seunghwan Song, Yongha Park, Jinbae Bang, Sangki Hong, B. Jeong, Hyun-Jin Kim, Chunan Lee, Young-Sun Min, Inryul Lee, In-Mo Kim, Sung-Hoon Kim, Dongkyu Yoon, KiSeung Kim, Youngdon Choi, Moosung Kim, Hyunggon Kim, Pansuk Kwak, Jeong-Don Ihm, D. Byeon, Jin-Yub Lee, Ki-Tae Park, K. Kyung","doi":"10.1109/ISSCC.2017.7870331","DOIUrl":"https://doi.org/10.1109/ISSCC.2017.7870331","url":null,"abstract":"The advent of emerging technologies such as cloud computing, big data, the internet of things and mobile computing is producing a tremendous amount of data. In the era of big data, storage devices with versatile characteristics are required for ultra-fast processing, higher capacity storage, lower cost, and lower power operation. SSDs employing 3D NAND are a promising to meet these requirements. Since the introduction of 3D NAND technology to marketplace in 2014 [1], the memory array size has nearly doubled every year [2,3]. To continue scaling 3D NAND array density, it is essential to scale down vertically to minimize total mold height. However, vertical scaling results in critical problems such as increasing WL capacitance and non-uniformity of stacked WLs due to variation in the channel hole diameter. To tackle these issues, this work proposes schemes for programming speed improvement and power reduction, and on-chip processing algorithms for error correction.","PeriodicalId":269679,"journal":{"name":"2017 IEEE International Solid-State Circuits Conference (ISSCC)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133183200","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-02-01DOI: 10.1109/ISSCC.2017.7870263
Bongki Son, Yunjae Suh, Sungho Kim, Heejae Jung, Jun-Seok Kim, Chang-Woo Shin, Keunju Park, Kyoobin Lee, Jin Man Park, J. Woo, Yohan J. Roh, Hyunku Lee, Y. Wang, I. Ovsiannikov, H. Ryu
We report a VGA dynamic vision sensor (DVS) with a 9µm pixel, developed through a digital as well as an analog implementation. DVS systems in the literature try to increase spatial resolution up to QVGA [1–2] and data rates up to 50 million events per second (Meps) (self-acknowledged) [3], but they are still inadequate for high-performance applications such as gesture recognition, drones, automotive, etc. Moreover, the smallest reported pixel of 18.5µm is too large for economical mass production [3]. This paper reports a 640×480 VGA-resolution DVS system with a 9µm pixel pitch supporting a data rate of 300Meps for sufficient event transfer in spite of higher resolution. Maintaining acceptable pixel performance, the pixel circuitry is carefully designed and optimized using a BSI CIS process. To acquire data (i.e., pixel events) at high speed even with high resolution (e.g., VGA), a fully synthesized word-serial group address-event representation (G-AER) is implemented, which handles massive events in parallel by binding neighboring 8 pixels into a group. In addition, a 10b programmable bias generator dedicated to a DVS system provides easy controllability of pixel biases and event thresholds.
{"title":"4.1 A 640×480 dynamic vision sensor with a 9µm pixel and 300Meps address-event representation","authors":"Bongki Son, Yunjae Suh, Sungho Kim, Heejae Jung, Jun-Seok Kim, Chang-Woo Shin, Keunju Park, Kyoobin Lee, Jin Man Park, J. Woo, Yohan J. Roh, Hyunku Lee, Y. Wang, I. Ovsiannikov, H. Ryu","doi":"10.1109/ISSCC.2017.7870263","DOIUrl":"https://doi.org/10.1109/ISSCC.2017.7870263","url":null,"abstract":"We report a VGA dynamic vision sensor (DVS) with a 9µm pixel, developed through a digital as well as an analog implementation. DVS systems in the literature try to increase spatial resolution up to QVGA [1–2] and data rates up to 50 million events per second (Meps) (self-acknowledged) [3], but they are still inadequate for high-performance applications such as gesture recognition, drones, automotive, etc. Moreover, the smallest reported pixel of 18.5µm is too large for economical mass production [3]. This paper reports a 640×480 VGA-resolution DVS system with a 9µm pixel pitch supporting a data rate of 300Meps for sufficient event transfer in spite of higher resolution. Maintaining acceptable pixel performance, the pixel circuitry is carefully designed and optimized using a BSI CIS process. To acquire data (i.e., pixel events) at high speed even with high resolution (e.g., VGA), a fully synthesized word-serial group address-event representation (G-AER) is implemented, which handles massive events in parallel by binding neighboring 8 pixels into a group. In addition, a 10b programmable bias generator dedicated to a DVS system provides easy controllability of pixel biases and event thresholds.","PeriodicalId":269679,"journal":{"name":"2017 IEEE International Solid-State Circuits Conference (ISSCC)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127670110","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-02-01DOI: 10.1109/ISSCC.2017.7870459
Y. Katsube, Shinya Kajiyama, Takuma Nishimoto, T. Nakagawa, Yasuyuki Okuma, Yohei Nakamura, T. Terada, Yutaka Igarashi, T. Yamawaki, T. Yazaki, Y. Hayashi, Kazuhiro Amino, Takuya Kaneko, Hiroki Tanaka
A diagnostic ultrasound (US) system transmits acoustic waves at several to tens of MHz into the human body for clinical purposes and detects the reflected waves to observe the internal organs without having a medical operation or radiation exposure. The system is composed of a main unit and probe connected via coaxial cables. The probe is very small because medical technicians laboriously grab and manipulate it for a long time. To avoid image obscurity depending on medical technicians, high-speed and high-resolution 3D/4D imaging is necessary. For this reason, several thousands of lead bulk piezoelectric material transducers (TD) need to be squeezed into the small probe. Since the number of cables is limited to several hundreds, the probe needs to include beamforming functionality and a 2D array IC [1–6], which includes thousands of US transceivers.
{"title":"27.6 Single-chip 3072ch 2D array IC with RX analog and all-digital TX beamformer for 3D ultrasound imaging","authors":"Y. Katsube, Shinya Kajiyama, Takuma Nishimoto, T. Nakagawa, Yasuyuki Okuma, Yohei Nakamura, T. Terada, Yutaka Igarashi, T. Yamawaki, T. Yazaki, Y. Hayashi, Kazuhiro Amino, Takuya Kaneko, Hiroki Tanaka","doi":"10.1109/ISSCC.2017.7870459","DOIUrl":"https://doi.org/10.1109/ISSCC.2017.7870459","url":null,"abstract":"A diagnostic ultrasound (US) system transmits acoustic waves at several to tens of MHz into the human body for clinical purposes and detects the reflected waves to observe the internal organs without having a medical operation or radiation exposure. The system is composed of a main unit and probe connected via coaxial cables. The probe is very small because medical technicians laboriously grab and manipulate it for a long time. To avoid image obscurity depending on medical technicians, high-speed and high-resolution 3D/4D imaging is necessary. For this reason, several thousands of lead bulk piezoelectric material transducers (TD) need to be squeezed into the small probe. Since the number of cables is limited to several hundreds, the probe needs to include beamforming functionality and a 2D array IC [1–6], which includes thousands of US transceivers.","PeriodicalId":269679,"journal":{"name":"2017 IEEE International Solid-State Circuits Conference (ISSCC)","volume":"160 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127670265","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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