Pub Date : 2017-02-01DOI: 10.1109/ISSCC.2017.7870379
Chuang Lu, A. Ba, Yao-Hong Liu, Xiaoyang Wang, Christian Bachmann, K. Philips
Wearable/implantable devices, e.g., heart-rate-monitor straps and implanted wireless sensors, need to be ultra-low-power (ULP), compact, and also robust against the proximity effect, which can significantly degrade the antenna and front-end performance and hence battery lifetime. A fully integrated adaptive front-end with a tunable matching network (TMN) using low-power and fast impedance detection is highly desirable for robust and efficient operation.
{"title":"17.4 A sub-mW antenna-impedance detection using electrical balance for single-step on-chip tunable matching in wearable/implantable applications","authors":"Chuang Lu, A. Ba, Yao-Hong Liu, Xiaoyang Wang, Christian Bachmann, K. Philips","doi":"10.1109/ISSCC.2017.7870379","DOIUrl":"https://doi.org/10.1109/ISSCC.2017.7870379","url":null,"abstract":"Wearable/implantable devices, e.g., heart-rate-monitor straps and implanted wireless sensors, need to be ultra-low-power (ULP), compact, and also robust against the proximity effect, which can significantly degrade the antenna and front-end performance and hence battery lifetime. A fully integrated adaptive front-end with a tunable matching network (TMN) using low-power and fast impedance detection is highly desirable for robust and efficient operation.","PeriodicalId":269679,"journal":{"name":"2017 IEEE International Solid-State Circuits Conference (ISSCC)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121364367","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-02-01DOI: 10.1109/ISSCC.2017.7870341
Enrico Roverato, M. Kosunen, Koen Cornelissens, S. Vatti, Paul Stynen, Kaoutar Bertrand, T. Korhonen, H. Samsom, P. Vandenameele, J. Ryynänen
The crowded radio spectrum allocated for 3G/4G mobile communication, together with the growing demand for higher data-rates, has led to the situation where transceivers need to support FDD operation in multiple frequency bands with different TX-RX duplex spacing. In order to reduce costs and enable SAW-less operation, many recent transmitter implementations have thus targeted stringent out-of-band (OOB) emission levels. Analog-intensive TX architectures achieve low OOB noise at the price of large area consumption, as complex reconstruction filters are used to suppress DAC quantization noise and image replicas [1,2]. On the other hand, due to the lack of analog filtering, digital-intensive TX architectures need 12–14b DAC resolution for low OOB noise, which complicates DAC design and typically requires DPD or calibration [3–5]. This work presents an RF transmitter implementing a fully digital solution to the aforementioned challenge. Instead of using bulky analog filtering or high resolution DAC, the disclosed TX employs digital ΔΣ modulation and mismatch shaping to attenuate the DAC noise at a programmable duplex distance. This solution enables −160dBc/Hz noise in the RX-band, by using only a 10b DAC without DPD, calibration or analog filtering.
{"title":"13.4 All-digital RF transmitter in 28nm CMOS with programmable RX-band noise shaping","authors":"Enrico Roverato, M. Kosunen, Koen Cornelissens, S. Vatti, Paul Stynen, Kaoutar Bertrand, T. Korhonen, H. Samsom, P. Vandenameele, J. Ryynänen","doi":"10.1109/ISSCC.2017.7870341","DOIUrl":"https://doi.org/10.1109/ISSCC.2017.7870341","url":null,"abstract":"The crowded radio spectrum allocated for 3G/4G mobile communication, together with the growing demand for higher data-rates, has led to the situation where transceivers need to support FDD operation in multiple frequency bands with different TX-RX duplex spacing. In order to reduce costs and enable SAW-less operation, many recent transmitter implementations have thus targeted stringent out-of-band (OOB) emission levels. Analog-intensive TX architectures achieve low OOB noise at the price of large area consumption, as complex reconstruction filters are used to suppress DAC quantization noise and image replicas [1,2]. On the other hand, due to the lack of analog filtering, digital-intensive TX architectures need 12–14b DAC resolution for low OOB noise, which complicates DAC design and typically requires DPD or calibration [3–5]. This work presents an RF transmitter implementing a fully digital solution to the aforementioned challenge. Instead of using bulky analog filtering or high resolution DAC, the disclosed TX employs digital ΔΣ modulation and mismatch shaping to attenuate the DAC noise at a programmable duplex distance. This solution enables −160dBc/Hz noise in the RX-band, by using only a 10b DAC without DPD, calibration or analog filtering.","PeriodicalId":269679,"journal":{"name":"2017 IEEE International Solid-State Circuits Conference (ISSCC)","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117168730","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-02-01DOI: 10.1109/ISSCC.2017.7870387
Tong Zhang, A. Najafi, Chenxin Su, J. Rudell
Full-duplex (FD) radio communication potentially doubles the spectral efficiency in the densely occupied RF spectrum (100MHz to 5GHz). However, significant challenges remain, particularly the presence of a strong transmitter (TX) self-interference (SI) coupling to the receiver (RX). Numerous recent efforts on mitigating SI have focused on using active cancellation techniques [1–5]. However, these methods are challenged by either a degradation in noise performance [2], high power consumption [1,4], large silicon area [5], the inability to adequately cancel a high-output-power TX signal [3–4], or achieve a relatively narrow cancellation bandwidth [3,5]. Moreover, other sources of SI are presented to the RX, including the effects of 1) in-band TX thermal noise, which can exceed the RX noise floor, 2) the RX LO phase noise (PN), which reciprocally mixes with SI, further degrading the C/I ratio. This paper presents several circuit-level techniques, which contribute toward reducing the interaction between the TX and RX in FD radios.
{"title":"18.1 A 1.7-to-2.2GHz full-duplex transceiver system with >50dB self-interference cancellation over 42MHz bandwidth","authors":"Tong Zhang, A. Najafi, Chenxin Su, J. Rudell","doi":"10.1109/ISSCC.2017.7870387","DOIUrl":"https://doi.org/10.1109/ISSCC.2017.7870387","url":null,"abstract":"Full-duplex (FD) radio communication potentially doubles the spectral efficiency in the densely occupied RF spectrum (100MHz to 5GHz). However, significant challenges remain, particularly the presence of a strong transmitter (TX) self-interference (SI) coupling to the receiver (RX). Numerous recent efforts on mitigating SI have focused on using active cancellation techniques [1–5]. However, these methods are challenged by either a degradation in noise performance [2], high power consumption [1,4], large silicon area [5], the inability to adequately cancel a high-output-power TX signal [3–4], or achieve a relatively narrow cancellation bandwidth [3,5]. Moreover, other sources of SI are presented to the RX, including the effects of 1) in-band TX thermal noise, which can exceed the RX noise floor, 2) the RX LO phase noise (PN), which reciprocally mixes with SI, further degrading the C/I ratio. This paper presents several circuit-level techniques, which contribute toward reducing the interaction between the TX and RX in FD radios.","PeriodicalId":269679,"journal":{"name":"2017 IEEE International Solid-State Circuits Conference (ISSCC)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116294187","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-02-01DOI: 10.1109/ISSCC.2017.7870424
M. Brox, M. Balakrishnan, M. Broschwitz, Cristian Chetreanu, S. Dietrich, F. Funfrock, Marcos Alvarez Gonzalez, Thomas Hein, Eugen Huber, Daniel Lauber, M. Ivanov, Maksim Kuzmenka, Christian N. Mohr, Francisco Emiliano Munoz, Juan Ocon Garrido, Swetha Padaraju, Sven Piatkowski, Jan Pottgiesser, P. Pfefferl, M. Plan, Jens Polney, Stefan Rau, Michael Richter, Ronny Schneider, R. Seitter, W. Spirkl, M. Walter, Jörg Weller, F. Vitale
Over the last years, GDDR5 has emerged as the dominant standard for applications requiring high system bandwidth like graphic cards and game consoles. However, GDDR5 data rates are saturating due to limitations in the clock frequency and column-access cycle time (tCCD). To reach the data rate of 9Gb/s/pin [1], a GDDR5 DRAM has to be clocked at 2.25GHz and operate at a tCCD of 888ps. This combination makes the design of control logic, data path and memory core difficult in a typical DRAM process. Still, the industry is demanding higher system bandwidth to enable continuous improvements in the visual computing arena. For this purpose, an 8Gb GDDR5X DRAM has been developed reaching a data rate of 12Gb/s/pin, which surpasses the fastest published GDDR5 [1] by 33%. This paper introduces GDDR5X and discusses relevant circuit techniques in clock generation, receiver and transmitter design to enable the higher data rates on a conventional DRAM process.
{"title":"23.1 An 8Gb 12Gb/s/pin GDDR5X DRAM for cost-effective high-performance applications","authors":"M. Brox, M. Balakrishnan, M. Broschwitz, Cristian Chetreanu, S. Dietrich, F. Funfrock, Marcos Alvarez Gonzalez, Thomas Hein, Eugen Huber, Daniel Lauber, M. Ivanov, Maksim Kuzmenka, Christian N. Mohr, Francisco Emiliano Munoz, Juan Ocon Garrido, Swetha Padaraju, Sven Piatkowski, Jan Pottgiesser, P. Pfefferl, M. Plan, Jens Polney, Stefan Rau, Michael Richter, Ronny Schneider, R. Seitter, W. Spirkl, M. Walter, Jörg Weller, F. Vitale","doi":"10.1109/ISSCC.2017.7870424","DOIUrl":"https://doi.org/10.1109/ISSCC.2017.7870424","url":null,"abstract":"Over the last years, GDDR5 has emerged as the dominant standard for applications requiring high system bandwidth like graphic cards and game consoles. However, GDDR5 data rates are saturating due to limitations in the clock frequency and column-access cycle time (tCCD). To reach the data rate of 9Gb/s/pin [1], a GDDR5 DRAM has to be clocked at 2.25GHz and operate at a tCCD of 888ps. This combination makes the design of control logic, data path and memory core difficult in a typical DRAM process. Still, the industry is demanding higher system bandwidth to enable continuous improvements in the visual computing arena. For this purpose, an 8Gb GDDR5X DRAM has been developed reaching a data rate of 12Gb/s/pin, which surpasses the fastest published GDDR5 [1] by 33%. This paper introduces GDDR5X and discusses relevant circuit techniques in clock generation, receiver and transmitter design to enable the higher data rates on a conventional DRAM process.","PeriodicalId":269679,"journal":{"name":"2017 IEEE International Solid-State Circuits Conference (ISSCC)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114668613","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-02-01DOI: 10.1109/ISSCC.2017.7870481
Meng-Fan Chang, J. Deguchi, V. De, M. Motomura, S. Shiratake, M. Verhelst
This forum brings together experts in software applications, system architectures, and chip designs to explore cognitive computing approaches over the near-, mid-, and long-term.
本次论坛汇集了软件应用、系统架构和芯片设计方面的专家，探讨了近期、中期和长期的认知计算方法。
{"title":"F3: Beyond the horizon of conventional computing: From deep learning to neuromorphic systems","authors":"Meng-Fan Chang, J. Deguchi, V. De, M. Motomura, S. Shiratake, M. Verhelst","doi":"10.1109/ISSCC.2017.7870481","DOIUrl":"https://doi.org/10.1109/ISSCC.2017.7870481","url":null,"abstract":"This forum brings together experts in software applications, system architectures, and chip designs to explore cognitive computing approaches over the near-, mid-, and long-term.","PeriodicalId":269679,"journal":{"name":"2017 IEEE International Solid-State Circuits Conference (ISSCC)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126145153","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-02-01DOI: 10.1109/ISSCC.2017.7870442
Jian Pang, S. Maki, Seitaro Kawai, Noriaki Nagashima, Yuuki Seo, Masato Dome, Hisashi Kato, M. Katsuragi, K. Kimura, Satoshi Kondo, Y. Terashima, Hanli Liu, T. Siriburanon, A. Narayanan, Nurul Fajri, T. Kaneko, Toru Yoshioka, Bangan Liu, Yun Wang, Rui Wu, Ning Li, K. K. Tokgoz, M. Miyahara, K. Okada, A. Matsuzawa
The 60GHz carrier with 9GHz bandwidth enables ultra-high-speed wireless communication in recent years [1–4]. To meet the demand from rapidly-increasing data traffic, the IEEE802.11ay standard is one of the most promising candidates aiming for 100Gb/s data-rate. Both higher-order digital modulation such as 128QAM and channel bonding at 60GHz are considered to be used in the IEEE802.11ay standard. However, the more severe requirements of LO feedthrough (LOFT) and image-rejection ratio (IMRR) have to be satisfied, so much higher accuracy in built-in calibration circuitry is required across the entire 9GHz spectrum for LOFT and I/Q imbalance calibration to achieve the required EVM.
{"title":"24.9 A 128-QAM 60GHz CMOS transceiver for IEEE802.11ay with calibration of LO feedthrough and I/Q imbalance","authors":"Jian Pang, S. Maki, Seitaro Kawai, Noriaki Nagashima, Yuuki Seo, Masato Dome, Hisashi Kato, M. Katsuragi, K. Kimura, Satoshi Kondo, Y. Terashima, Hanli Liu, T. Siriburanon, A. Narayanan, Nurul Fajri, T. Kaneko, Toru Yoshioka, Bangan Liu, Yun Wang, Rui Wu, Ning Li, K. K. Tokgoz, M. Miyahara, K. Okada, A. Matsuzawa","doi":"10.1109/ISSCC.2017.7870442","DOIUrl":"https://doi.org/10.1109/ISSCC.2017.7870442","url":null,"abstract":"The 60GHz carrier with 9GHz bandwidth enables ultra-high-speed wireless communication in recent years [1–4]. To meet the demand from rapidly-increasing data traffic, the IEEE802.11ay standard is one of the most promising candidates aiming for 100Gb/s data-rate. Both higher-order digital modulation such as 128QAM and channel bonding at 60GHz are considered to be used in the IEEE802.11ay standard. However, the more severe requirements of LO feedthrough (LOFT) and image-rejection ratio (IMRR) have to be satisfied, so much higher accuracy in built-in calibration circuitry is required across the entire 9GHz spectrum for LOFT and I/Q imbalance calibration to achieve the required EVM.","PeriodicalId":269679,"journal":{"name":"2017 IEEE International Solid-State Circuits Conference (ISSCC)","volume":"173 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127130226","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-02-01DOI: 10.1109/ISSCC.2017.7870469
K. Yoshioka, Tomohiko Sugimoto, N. Waki, Sinnyoung Kim, Daisuke Kurose, Hirotomo Ishii, M. Furuta, A. Sai, T. Itakura
Wireless standards, e.g. 802.11ac Wave 2 and 802.11ax draft, aim to boost user throughput to cope with growing data traffic. High-speed (fs>100MS/s) and high-resolution (ENOB>9.5b) ADCs are essential for leading-edge wireless SoCs, given the bandwidth and PAPR specifications. Also, low power dissipation (FoM<20fJ/conv) is crucial for mobile applications. A number of pipelined-SAR ADCs have been presented which satisfy these design targets [1–3]. However, in deep submicron CMOS, design of a high DC-gain opamp for the MDAC is a serious obstacle due to reduced intrinsic transistor gain and sub-1V supply voltage. Hence, all designs utilize digital calibration to counter gain error and tolerate the use of a low-gain amplifier. Calibration times of at least several tens of ms are required, resulting in lengthy start-up times and reduced SoC power efficiency. Moreover, such calibration cannot track sudden supply voltage variations and suppressing such fluctuations with bypass capacitors significantly impacts chip cost [1–2]. Furthermore, amplifier non-linearity remains unsolved; with lower supply voltages, the limited amplifier swing tightens SAR noise requirements.
{"title":"28.7 A 0.7V 12b 160MS/s 12.8fJ/conv-step pipelined-SAR ADC in 28nm CMOS with digital amplifier technique","authors":"K. Yoshioka, Tomohiko Sugimoto, N. Waki, Sinnyoung Kim, Daisuke Kurose, Hirotomo Ishii, M. Furuta, A. Sai, T. Itakura","doi":"10.1109/ISSCC.2017.7870469","DOIUrl":"https://doi.org/10.1109/ISSCC.2017.7870469","url":null,"abstract":"Wireless standards, e.g. 802.11ac Wave 2 and 802.11ax draft, aim to boost user throughput to cope with growing data traffic. High-speed (fs>100MS/s) and high-resolution (ENOB>9.5b) ADCs are essential for leading-edge wireless SoCs, given the bandwidth and PAPR specifications. Also, low power dissipation (FoM<20fJ/conv) is crucial for mobile applications. A number of pipelined-SAR ADCs have been presented which satisfy these design targets [1–3]. However, in deep submicron CMOS, design of a high DC-gain opamp for the MDAC is a serious obstacle due to reduced intrinsic transistor gain and sub-1V supply voltage. Hence, all designs utilize digital calibration to counter gain error and tolerate the use of a low-gain amplifier. Calibration times of at least several tens of ms are required, resulting in lengthy start-up times and reduced SoC power efficiency. Moreover, such calibration cannot track sudden supply voltage variations and suppressing such fluctuations with bypass capacitors significantly impacts chip cost [1–2]. Furthermore, amplifier non-linearity remains unsolved; with lower supply voltages, the limited amplifier swing tightens SAR noise requirements.","PeriodicalId":269679,"journal":{"name":"2017 IEEE International Solid-State Circuits Conference (ISSCC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126359320","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-02-01DOI: 10.1109/ISSCC.2017.7870403
Doyun Kim, Jonghwan Kim, Hyunju Ham, Mingoo Seok
In today's system-on-chip designs, a low-drop-out voltage regulator (LDO) is one of the most popular choices to create a distinct voltage domain owing to its high power density. Many LDOs, however, need a large output capacitor (COUT) to compensate a fast load current (ILOAD) change, increasing the number of pins and off-chip components. In synchronous digital LDO designs, high frequency can miniaturize COUT, but it inevitably causes power inefficiency [2]. A recent work has instead employed an event-driven (ED) control scheme to alleviate the COUT requirement, demonstrating a 400µA-class digital LDO with a COUT of 400pF [1]. The ED scheme is promising, but it is still desirable to develop an LDO which can support a larger ILOAD with a smaller COUT. This is indeed a daunting challenge since a substantial reduction in feedback latency (TLAT) is necessary to retain the same level of output voltage change (ΔVOUT) with a smaller COUT. In this work, to shorten latency, we propose to infuse fine-grained parallelism into ED control systems and develop a fully integrated digital LDO. The prototyped LDO can support 1.44mA ILOAD at 0.5V VIN, 0.45V VSP, and 99.2% peak current efficiency. The LDO shows less than 34mV (7.6%) ΔVOUT with a 0.1nF COUT when ΔILOAD is ±1.44mA.
{"title":"20.6 A 0.5V-VIN 1.44mA-class event-driven digital LDO with a fully integrated 100pF output capacitor","authors":"Doyun Kim, Jonghwan Kim, Hyunju Ham, Mingoo Seok","doi":"10.1109/ISSCC.2017.7870403","DOIUrl":"https://doi.org/10.1109/ISSCC.2017.7870403","url":null,"abstract":"In today's system-on-chip designs, a low-drop-out voltage regulator (LDO) is one of the most popular choices to create a distinct voltage domain owing to its high power density. Many LDOs, however, need a large output capacitor (C<inf>OUT</inf>) to compensate a fast load current (I<inf>LOAD</inf>) change, increasing the number of pins and off-chip components. In synchronous digital LDO designs, high frequency can miniaturize C<inf>OUT</inf>, but it inevitably causes power inefficiency [2]. A recent work has instead employed an event-driven (ED) control scheme to alleviate the C<inf>OUT</inf> requirement, demonstrating a 400µA-class digital LDO with a C<inf>OUT</inf> of 400pF [1]. The ED scheme is promising, but it is still desirable to develop an LDO which can support a larger I<inf>LOAD</inf> with a smaller C<inf>OUT</inf>. This is indeed a daunting challenge since a substantial reduction in feedback latency (T<inf>LAT</inf>) is necessary to retain the same level of output voltage change (ΔV<inf>OUT</inf>) with a smaller C<inf>OUT</inf>. In this work, to shorten latency, we propose to infuse fine-grained parallelism into ED control systems and develop a fully integrated digital LDO. The prototyped LDO can support 1.44mA I<inf>LOAD</inf> at 0.5V V<inf>IN</inf>, 0.45V V<inf>SP</inf>, and 99.2% peak current efficiency. The LDO shows less than 34mV (7.6%) ΔV<inf>OUT</inf> with a 0.1nF C<inf>OUT</inf> when ΔI<inf>LOAD</inf> is ±1.44mA.","PeriodicalId":269679,"journal":{"name":"2017 IEEE International Solid-State Circuits Conference (ISSCC)","volume":"295 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123489061","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-02-01DOI: 10.1109/ISSCC.2017.7870369
H. Shibata, V. Kozlov, Zexi Ji, A. Ganesan, Haiyang Zhu, D. Paterson
In traditional ADCs the input signal is sampled at the front-end by a switched-capacitor circuit and all internal signals are processed in discrete-time (DT) even though the front-end sampler introduces artifacts such as aliasing, noise folding, and high-peak ADC driving current to charge the input sampling capacitor. In ΔΣ ADCs, those issues are resolved by replacing the DT loop filter with a continuous-time (CT) implementation which relaxes the pre-filter and driver requirements in the signal chain thus reducing the overall signal chain power consumption. CTΔΣs also introduce additional benefits such as 2–3× higher clocking capability in the same process node and low-power internal opamps due to relaxed noise, loading, and gain bandwidth requirements. Since these CT benefits are not exclusive to the ΔΣ architecture, other ADC architectures could similarly benefit by replacing DT blocks with CT ones. This paper presents a CT pipeline ADC, which processes the input and residue signals with CT circuitry throughout all the pipeline stages. The combination of CT signal processing with the pipeline architecture realizes an ADC system inheriting the CT benefits while achieving a digitization bandwidth (BW) more than 2× greater than that of CT ΔΣ ADCs, which is comparable to DT pipeline ADCs in the same process node.
{"title":"16.2 A 9GS/s 1GHz-BW oversampled continuous-time pipeline ADC achieving −161dBFS/Hz NSD","authors":"H. Shibata, V. Kozlov, Zexi Ji, A. Ganesan, Haiyang Zhu, D. Paterson","doi":"10.1109/ISSCC.2017.7870369","DOIUrl":"https://doi.org/10.1109/ISSCC.2017.7870369","url":null,"abstract":"In traditional ADCs the input signal is sampled at the front-end by a switched-capacitor circuit and all internal signals are processed in discrete-time (DT) even though the front-end sampler introduces artifacts such as aliasing, noise folding, and high-peak ADC driving current to charge the input sampling capacitor. In ΔΣ ADCs, those issues are resolved by replacing the DT loop filter with a continuous-time (CT) implementation which relaxes the pre-filter and driver requirements in the signal chain thus reducing the overall signal chain power consumption. CTΔΣs also introduce additional benefits such as 2–3× higher clocking capability in the same process node and low-power internal opamps due to relaxed noise, loading, and gain bandwidth requirements. Since these CT benefits are not exclusive to the ΔΣ architecture, other ADC architectures could similarly benefit by replacing DT blocks with CT ones. This paper presents a CT pipeline ADC, which processes the input and residue signals with CT circuitry throughout all the pipeline stages. The combination of CT signal processing with the pipeline architecture realizes an ADC system inheriting the CT benefits while achieving a digitization bandwidth (BW) more than 2× greater than that of CT ΔΣ ADCs, which is comparable to DT pipeline ADCs in the same process node.","PeriodicalId":269679,"journal":{"name":"2017 IEEE International Solid-State Circuits Conference (ISSCC)","volume":"302 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123786424","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-02-01DOI: 10.1109/ISSCC.2017.7870345
Jong Seok Park, Yanjie Wang, S. Pellerano, C. Hull, Hua Wang
Modern wireless systems often support multi-standards with spectrum-efficient modulation schemes such as 64QAM and 256QAM and high data-rates. This poses stringent requirements on RF Power Amplifiers (PAs) for their carrier bandwidth, linearity, modulation rate, and efficiency. Several multiband Analog PAs (APAs) and Digital PAs (DPAs) are recently reported. However, multiband APAs often suffer from low power efficiency [1]. Although current-mode DPAs achieve high efficiency, high output power (Pout), and compact designs [2], they typically exhibit excessive AM-PM distortions intrinsically due to the digital power cell operations. Thus, current-mode DPAs often need frequency-dependent AM-PM look-up-tables for pre-distortion and/or real-time phase cancellation, resulting in additional overhead and difficult implementation for high modulation rates [3,4].
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