Pub Date : 2001-10-21DOI: 10.1109/GAAS.2001.964390
M. Ray, D. Hill, O. Hartin, K. Johnson, P. Li
Thermal characteristics of typical InP/InGaAs and InGaP/GaAs HBTs were compared by simulation. Parameters such as emitter dimensions, number of emitters, emitter pitch, and thickness of device layers were varied over ranges of interest. Despite the higher thermal conductivity of the InP substrate compared to GaAs, thermal resistance of InP/InGaAs HBTs was generally higher than that of comparable InGaP/GaAs HBTs because of the very low thermal conductivity of InGaAs. Approaches for minimizing this adverse effect are discussed.
{"title":"Thermal impact of InGaAs on InP based HBTs","authors":"M. Ray, D. Hill, O. Hartin, K. Johnson, P. Li","doi":"10.1109/GAAS.2001.964390","DOIUrl":"https://doi.org/10.1109/GAAS.2001.964390","url":null,"abstract":"Thermal characteristics of typical InP/InGaAs and InGaP/GaAs HBTs were compared by simulation. Parameters such as emitter dimensions, number of emitters, emitter pitch, and thickness of device layers were varied over ranges of interest. Despite the higher thermal conductivity of the InP substrate compared to GaAs, thermal resistance of InP/InGaAs HBTs was generally higher than that of comparable InGaP/GaAs HBTs because of the very low thermal conductivity of InGaAs. Approaches for minimizing this adverse effect are discussed.","PeriodicalId":269944,"journal":{"name":"GaAs IC Symposium. IEEE Gallium Arsenide Integrated Circuit Symposium. 23rd Annual Technical Digest 2001 (Cat. No.01CH37191)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129962807","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-10-21DOI: 10.1109/GAAS.2001.964360
S. Masuda, T. Hirose, S. Yokokawa, M. Nishi, S. Iijima, K. Ono, Y. Watanabe
We developed for the first time a flip-chip multi-layer MMIC design technology that is based on thin-film inverted microstrip lines for use in low-cost W-band transceivers. This technology enables the minimization of chip size and the realization of a practical MMIC design, including the assembly issues in the W-band. A fabricated receiver amplifier occupying an area 1.5/spl times/0.35 mm experimentally achieved a gain of 27 dB and the transmitter power amplifier exhibited an output power of 14.5 dBm at 76 GHz, respectively. To our knowledge, this is the highest value ever reported at this frequency for a flip-chip multilayer MMIC amplifier.
{"title":"A new flip-chip MMIC technology with multi-layer transmission line structure for low-cost W-band transceivers","authors":"S. Masuda, T. Hirose, S. Yokokawa, M. Nishi, S. Iijima, K. Ono, Y. Watanabe","doi":"10.1109/GAAS.2001.964360","DOIUrl":"https://doi.org/10.1109/GAAS.2001.964360","url":null,"abstract":"We developed for the first time a flip-chip multi-layer MMIC design technology that is based on thin-film inverted microstrip lines for use in low-cost W-band transceivers. This technology enables the minimization of chip size and the realization of a practical MMIC design, including the assembly issues in the W-band. A fabricated receiver amplifier occupying an area 1.5/spl times/0.35 mm experimentally achieved a gain of 27 dB and the transmitter power amplifier exhibited an output power of 14.5 dBm at 76 GHz, respectively. To our knowledge, this is the highest value ever reported at this frequency for a flip-chip multilayer MMIC amplifier.","PeriodicalId":269944,"journal":{"name":"GaAs IC Symposium. IEEE Gallium Arsenide Integrated Circuit Symposium. 23rd Annual Technical Digest 2001 (Cat. No.01CH37191)","volume":"2003 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125784387","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-10-21DOI: 10.1109/GAAS.2001.964369
O. Hartin, M. Ray, P. Li, K. Johnson
There is significant advantage to simulation-assisted device development in compound semiconductors At Motorola, 2D and 3D physics-based TCAD is heavily integrated into device development for communications. Effective simulation methods have been developed that allow us to reduce development cycle time, and cycles of learning to achieve cost competitive III-V market leading technologies. Our methodology includes analytical analysis, calibration to measured data, parameter study, and optimization of DC, small signal AC, RF, and thermal performance. This methodology has been used in pHEMT, HBT, and HIGFET development Application development, such as the pHEMT-based RF switch, has also used device simulation heavily. The fundamentals of this methodology will be discussed and examples from the technology areas will be presented.
{"title":"Compound semiconductor physical device simulation for technology development at Motorola","authors":"O. Hartin, M. Ray, P. Li, K. Johnson","doi":"10.1109/GAAS.2001.964369","DOIUrl":"https://doi.org/10.1109/GAAS.2001.964369","url":null,"abstract":"There is significant advantage to simulation-assisted device development in compound semiconductors At Motorola, 2D and 3D physics-based TCAD is heavily integrated into device development for communications. Effective simulation methods have been developed that allow us to reduce development cycle time, and cycles of learning to achieve cost competitive III-V market leading technologies. Our methodology includes analytical analysis, calibration to measured data, parameter study, and optimization of DC, small signal AC, RF, and thermal performance. This methodology has been used in pHEMT, HBT, and HIGFET development Application development, such as the pHEMT-based RF switch, has also used device simulation heavily. The fundamentals of this methodology will be discussed and examples from the technology areas will be presented.","PeriodicalId":269944,"journal":{"name":"GaAs IC Symposium. IEEE Gallium Arsenide Integrated Circuit Symposium. 23rd Annual Technical Digest 2001 (Cat. No.01CH37191)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116842553","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/GAAS.2001.964386
H. Huang, Y. Wang
Very high performance InGaP/InGaAs/GaAs PHEMT is demonstrated. The fabricated InGaP gated PHEMT device with 0.25/spl times/160 /spl mu/m/sup 2/ of gate dimension shows a 304 mA/mm of saturation drain current at V/sub Gs/=0V, V/sub DS/=2 V and a 320 mS/mm of extrinsic transconductance. Noise figure at 12 GHz is measured to be 0.46 dB with a 13 dB associated gain. With such a high gain and low noise, the drain-to-gate breakdown can be as high as 10 V. Standard deviation in the threshold voltage of 22 mV across a 4-inch wafer can be achieved using a highly selective wet recess etching process.
{"title":"Super low noise InGaP gated PHEMT","authors":"H. Huang, Y. Wang","doi":"10.1109/GAAS.2001.964386","DOIUrl":"https://doi.org/10.1109/GAAS.2001.964386","url":null,"abstract":"Very high performance InGaP/InGaAs/GaAs PHEMT is demonstrated. The fabricated InGaP gated PHEMT device with 0.25/spl times/160 /spl mu/m/sup 2/ of gate dimension shows a 304 mA/mm of saturation drain current at V/sub Gs/=0V, V/sub DS/=2 V and a 320 mS/mm of extrinsic transconductance. Noise figure at 12 GHz is measured to be 0.46 dB with a 13 dB associated gain. With such a high gain and low noise, the drain-to-gate breakdown can be as high as 10 V. Standard deviation in the threshold voltage of 22 mV across a 4-inch wafer can be achieved using a highly selective wet recess etching process.","PeriodicalId":269944,"journal":{"name":"GaAs IC Symposium. IEEE Gallium Arsenide Integrated Circuit Symposium. 23rd Annual Technical Digest 2001 (Cat. No.01CH37191)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122444317","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/GAAS.2001.964389
H. Sugahara, S. Kimura, K. Murata, E. Sano
A key technology for realizing small, low-cost IC modules for over-40-Gb/s optical communication systems has been developed. The technology mainly features 8-mm-square leadless chip carrier (LCC) packages and four-layer resin printed circuit boards (PCBs). It was applied to build a prototype multichip 1:4 DEMUX module operating at 45 Gb/s.
{"title":"Over-40-Gb/s IC module technology using 8-mm-square leadless chip carrier packages mounted on four-layer resin printed circuit boards","authors":"H. Sugahara, S. Kimura, K. Murata, E. Sano","doi":"10.1109/GAAS.2001.964389","DOIUrl":"https://doi.org/10.1109/GAAS.2001.964389","url":null,"abstract":"A key technology for realizing small, low-cost IC modules for over-40-Gb/s optical communication systems has been developed. The technology mainly features 8-mm-square leadless chip carrier (LCC) packages and four-layer resin printed circuit boards (PCBs). It was applied to build a prototype multichip 1:4 DEMUX module operating at 45 Gb/s.","PeriodicalId":269944,"journal":{"name":"GaAs IC Symposium. IEEE Gallium Arsenide Integrated Circuit Symposium. 23rd Annual Technical Digest 2001 (Cat. No.01CH37191)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128755050","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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