Pub Date : 2001-10-21DOI: 10.1109/GAAS.2001.964371
Y. Chou, D. Leung, R. Lai, J. Scarpulla, M. Biedenbender, R. Grundbacher, D. Eng, P. Liu, A. Oki, D. Streit
High reliability performance of a Q-band low-noise MMIC amplifier fabricated using 0.1 /spl mu/m production AlGaAs/InGaAs/GaAs HEMT process technology is reported. Operating at an accelerated DC bias condition of Vds=4.2 V and Ids=150 mA/mm, two-stage balanced amplifiers were lifetested at three temperatures (T/sub ambient/=255/spl deg/C, T/sub ambient/=270/spl deg/C, and T/sub ambient/=285/spl deg/C) in air ambient. After stress, MMIC amplifiers were brought down to room temperature and small-signal microwave characteristics were measured. Failure time for each temperature was determined using /spl Delta/S21=-1.0 dB measured at room temperature as the failure criteria. The activation energy (Ea) is 1.7 eV, achieving a projected median-time-to-failure (MTF) of 6/spl times/10/sup 9/ hours at a 125/spl deg/C junction temperature. This is the state-of-art of 0.1 /spl mu/m HEMT reliability based on S21 failure criteria of MMIC amplifiers under DC stress at high junction temperature in air ambient. This result demonstrates a robust HEMT technology which is immune to the stress effects of high electric field under high temperature operation, and demonstrates the suitability of the HEMTs for non-hermetic commercial applications.
{"title":"High reliability non-hermetic 0.1 /spl mu/m GaAs pseudomorphic HEMT MMIC amplifiers","authors":"Y. Chou, D. Leung, R. Lai, J. Scarpulla, M. Biedenbender, R. Grundbacher, D. Eng, P. Liu, A. Oki, D. Streit","doi":"10.1109/GAAS.2001.964371","DOIUrl":"https://doi.org/10.1109/GAAS.2001.964371","url":null,"abstract":"High reliability performance of a Q-band low-noise MMIC amplifier fabricated using 0.1 /spl mu/m production AlGaAs/InGaAs/GaAs HEMT process technology is reported. Operating at an accelerated DC bias condition of Vds=4.2 V and Ids=150 mA/mm, two-stage balanced amplifiers were lifetested at three temperatures (T/sub ambient/=255/spl deg/C, T/sub ambient/=270/spl deg/C, and T/sub ambient/=285/spl deg/C) in air ambient. After stress, MMIC amplifiers were brought down to room temperature and small-signal microwave characteristics were measured. Failure time for each temperature was determined using /spl Delta/S21=-1.0 dB measured at room temperature as the failure criteria. The activation energy (Ea) is 1.7 eV, achieving a projected median-time-to-failure (MTF) of 6/spl times/10/sup 9/ hours at a 125/spl deg/C junction temperature. This is the state-of-art of 0.1 /spl mu/m HEMT reliability based on S21 failure criteria of MMIC amplifiers under DC stress at high junction temperature in air ambient. This result demonstrates a robust HEMT technology which is immune to the stress effects of high electric field under high temperature operation, and demonstrates the suitability of the HEMTs for non-hermetic commercial applications.","PeriodicalId":269944,"journal":{"name":"GaAs IC Symposium. IEEE Gallium Arsenide Integrated Circuit Symposium. 23rd Annual Technical Digest 2001 (Cat. No.01CH37191)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128309569","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-10-21DOI: 10.1109/GAAS.2001.964384
S. Hsu, D. Pavlidis
AlGaN/GaN MODFETs (0.25/spl times/200 /spl mu/m/sup 2/) with low noise, high breakdown and power characteristics have been evaluated. A noise figure of 1.9 dB with 16.2 dB associated gain was obtained at a quiescent point of I/sub DS/=30 mA. and V/sub DS/=10 at 10 GHz. The maximum power measured was 22.9 dBm (/spl sim/1 W/mrn) and PAE was 21.9% at 8.4 GHz at the same bias condition. In addition, a maximum breakdown voltage (V/sub BD/) of /spl sim/115 V at I/sub D/=20 /spl mu/A and I/sub G//spl sim/30 /spl mu/A was measured. A MODFET noise model and its correlation with gate leakage current are also investigated.
{"title":"Low noise AlGaN/GaN MODFETs with high breakdown and power characteristics","authors":"S. Hsu, D. Pavlidis","doi":"10.1109/GAAS.2001.964384","DOIUrl":"https://doi.org/10.1109/GAAS.2001.964384","url":null,"abstract":"AlGaN/GaN MODFETs (0.25/spl times/200 /spl mu/m/sup 2/) with low noise, high breakdown and power characteristics have been evaluated. A noise figure of 1.9 dB with 16.2 dB associated gain was obtained at a quiescent point of I/sub DS/=30 mA. and V/sub DS/=10 at 10 GHz. The maximum power measured was 22.9 dBm (/spl sim/1 W/mrn) and PAE was 21.9% at 8.4 GHz at the same bias condition. In addition, a maximum breakdown voltage (V/sub BD/) of /spl sim/115 V at I/sub D/=20 /spl mu/A and I/sub G//spl sim/30 /spl mu/A was measured. A MODFET noise model and its correlation with gate leakage current are also investigated.","PeriodicalId":269944,"journal":{"name":"GaAs IC Symposium. IEEE Gallium Arsenide Integrated Circuit Symposium. 23rd Annual Technical Digest 2001 (Cat. No.01CH37191)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120908702","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-10-21DOI: 10.1109/GAAS.2001.964349
P. Savary, A. Girardot, G. Montoriol, F. Dupis, B. Thibaud, R. Jaoui, L. Chapoux, V. Esnault, L. Cornibert, O. Izumi, D. Hill, M. Sadaka, H. Henry, E. Yu, M. Tutt, M. Majerus, R. Uscola, F. Clayton, C. Rampley, S. Klingbeil, K. Rajagopalan, A. Mitra, A. Reyes
A heterojunction bipolar transistor (HBT) technology utilizing InGaP/GaAs and carbon-doped base has been established in Motorola's high-volume 6" GaAs facility. The technology has been used to develop an integrated dual band (824-849 MHz and 1850-1910 MHz) power amplifier IC with multi-mode operation for 2.5G portable wireless. Both three-stage amplifiers have 30 dB gain, and provide an EDGE (8-PSK) signal at 28 dBm, an NADC signal at 30 dBm, and a GMSK signal at 32 dBm in their respective frequency bands, using a single 3.5 V source. All matching elements external to the chip are included in a low cost epoxy substrate which is 9/spl times/12/spl times/1.6 mm/sup 3/. Prospects of using this technology in W-CDMA applications have also been explored. A prototype achieves an ACPR of -41 dBc at 28 dBm output power with an efficiency of 36%.
{"title":"Dual-band multi-mode power amplifier module using a third generation HBT technology","authors":"P. Savary, A. Girardot, G. Montoriol, F. Dupis, B. Thibaud, R. Jaoui, L. Chapoux, V. Esnault, L. Cornibert, O. Izumi, D. Hill, M. Sadaka, H. Henry, E. Yu, M. Tutt, M. Majerus, R. Uscola, F. Clayton, C. Rampley, S. Klingbeil, K. Rajagopalan, A. Mitra, A. Reyes","doi":"10.1109/GAAS.2001.964349","DOIUrl":"https://doi.org/10.1109/GAAS.2001.964349","url":null,"abstract":"A heterojunction bipolar transistor (HBT) technology utilizing InGaP/GaAs and carbon-doped base has been established in Motorola's high-volume 6\" GaAs facility. The technology has been used to develop an integrated dual band (824-849 MHz and 1850-1910 MHz) power amplifier IC with multi-mode operation for 2.5G portable wireless. Both three-stage amplifiers have 30 dB gain, and provide an EDGE (8-PSK) signal at 28 dBm, an NADC signal at 30 dBm, and a GMSK signal at 32 dBm in their respective frequency bands, using a single 3.5 V source. All matching elements external to the chip are included in a low cost epoxy substrate which is 9/spl times/12/spl times/1.6 mm/sup 3/. Prospects of using this technology in W-CDMA applications have also been explored. A prototype achieves an ACPR of -41 dBc at 28 dBm output power with an efficiency of 36%.","PeriodicalId":269944,"journal":{"name":"GaAs IC Symposium. IEEE Gallium Arsenide Integrated Circuit Symposium. 23rd Annual Technical Digest 2001 (Cat. No.01CH37191)","volume":"58 27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127039216","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-10-21DOI: 10.1109/GAAS.2001.964355
H. Nosaka, K. Ishii, T. Enoki
Clock and data recovery (CDR) with a novel two-mode phase comparator (PC) is proposed. The 10-Gbit/s CDR IC stably operates both for consecutive identical digits (CIDs) and for data transition density variations. This advancement is achieved by the novel two-mode PC, which enables us to optimize phase-locked loop parameters for various data patterns. Experimental results show that the jitter generation of the CDR IC is less than 7 ps/sub pp/ for a 2/sup 7/-1 pseudorandom bit sequence with up to 1024 CIDs. They also show that the jitter transfer and jitter tolerance are not affected by the data transition density factors between 1/8 and 1/2.
{"title":"A data-pattern independent clock and data recovery IC with a two-mode phase comparator","authors":"H. Nosaka, K. Ishii, T. Enoki","doi":"10.1109/GAAS.2001.964355","DOIUrl":"https://doi.org/10.1109/GAAS.2001.964355","url":null,"abstract":"Clock and data recovery (CDR) with a novel two-mode phase comparator (PC) is proposed. The 10-Gbit/s CDR IC stably operates both for consecutive identical digits (CIDs) and for data transition density variations. This advancement is achieved by the novel two-mode PC, which enables us to optimize phase-locked loop parameters for various data patterns. Experimental results show that the jitter generation of the CDR IC is less than 7 ps/sub pp/ for a 2/sup 7/-1 pseudorandom bit sequence with up to 1024 CIDs. They also show that the jitter transfer and jitter tolerance are not affected by the data transition density factors between 1/8 and 1/2.","PeriodicalId":269944,"journal":{"name":"GaAs IC Symposium. IEEE Gallium Arsenide Integrated Circuit Symposium. 23rd Annual Technical Digest 2001 (Cat. No.01CH37191)","volume":"77 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130469483","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-10-21DOI: 10.1109/GAAS.2001.964336
L.W. Yang, P. Chao, L. Wu
The authors consider the market perspectives of the Asia Pacific area, describe a business model based on the track records of silicon IC manufacturing, and highlight technology challenges.
作者考虑了亚太地区的市场前景，描述了基于硅集成电路制造记录的商业模式，并强调了技术挑战。
{"title":"The challenge of GaAs IC manufacturing in Taiwan for Asian Pacific wireless market","authors":"L.W. Yang, P. Chao, L. Wu","doi":"10.1109/GAAS.2001.964336","DOIUrl":"https://doi.org/10.1109/GAAS.2001.964336","url":null,"abstract":"The authors consider the market perspectives of the Asia Pacific area, describe a business model based on the track records of silicon IC manufacturing, and highlight technology challenges.","PeriodicalId":269944,"journal":{"name":"GaAs IC Symposium. IEEE Gallium Arsenide Integrated Circuit Symposium. 23rd Annual Technical Digest 2001 (Cat. No.01CH37191)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130378853","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-10-21DOI: 10.1109/GAAS.2001.964375
S. Hsu, D. Pavlidis
High frequency noise characteristics of InP/InGaAs HBTs with various emitter geometries were investigated. A minimum noise figure (F/sub min/) of 1.51 dB and associated gain (G/sub a/) of 9.6 dB at a frequency of 10 GHz and a DC power consumption of only 1.6 mW (V/sub CE/ = 1.6 V, I/sub C/ = 1 mA) at 10 GHz were obtained. The dependence of noise characteristics on bias and geometry is also reported. The dominant noise sources in these HBTs were analyzed and an optimum emitter area of 1.2 /spl times/ 20 /spl mu/m/sup 2/ was found to present minimum noise figure and equivalent noise resistance.
{"title":"Low noise, high-speed InP/InGaAs HBTs","authors":"S. Hsu, D. Pavlidis","doi":"10.1109/GAAS.2001.964375","DOIUrl":"https://doi.org/10.1109/GAAS.2001.964375","url":null,"abstract":"High frequency noise characteristics of InP/InGaAs HBTs with various emitter geometries were investigated. A minimum noise figure (F/sub min/) of 1.51 dB and associated gain (G/sub a/) of 9.6 dB at a frequency of 10 GHz and a DC power consumption of only 1.6 mW (V/sub CE/ = 1.6 V, I/sub C/ = 1 mA) at 10 GHz were obtained. The dependence of noise characteristics on bias and geometry is also reported. The dominant noise sources in these HBTs were analyzed and an optimum emitter area of 1.2 /spl times/ 20 /spl mu/m/sup 2/ was found to present minimum noise figure and equivalent noise resistance.","PeriodicalId":269944,"journal":{"name":"GaAs IC Symposium. IEEE Gallium Arsenide Integrated Circuit Symposium. 23rd Annual Technical Digest 2001 (Cat. No.01CH37191)","volume":"146 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128919139","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-10-21DOI: 10.1109/GAAS.2001.964348
Xian-jie Li, J. Ao, Rong Wang, Wei-Ji Liu, Zhigong Wang, Q. Zeng, Shiyong Liu, Chun-Guang Liang
An 850 nm wavelength monolithic integrated photoreceiver with a novel single-power-supplied transimpedance amplifier is reported based on 0.8 /spl mu/m depleted GaAs PHEMT technology. The IC consists of an MSM photodetector and a transimpedance amplifier with a 50 ohm-matched differential output. The MSM PD on the chip shows a dark current of 2.0 nA as well as a responsivity of 0.30 A/W under a bias of 3.5 V. The TIA shows a transimpedance gain of more than 58 dB/spl Omega/ with a -3 dB bandwidth of 2.0 GHz. Opening eye diagrams are demonstrated at bit-rates of 1.25 Gbit/s and 2.5 Gbit/s under a +5 V supply.
{"title":"An 850 nm wavelength monolithic integrated photoreceiver with a single-power-supplied transimpedance amplifier based on GaAs PHEMT technology","authors":"Xian-jie Li, J. Ao, Rong Wang, Wei-Ji Liu, Zhigong Wang, Q. Zeng, Shiyong Liu, Chun-Guang Liang","doi":"10.1109/GAAS.2001.964348","DOIUrl":"https://doi.org/10.1109/GAAS.2001.964348","url":null,"abstract":"An 850 nm wavelength monolithic integrated photoreceiver with a novel single-power-supplied transimpedance amplifier is reported based on 0.8 /spl mu/m depleted GaAs PHEMT technology. The IC consists of an MSM photodetector and a transimpedance amplifier with a 50 ohm-matched differential output. The MSM PD on the chip shows a dark current of 2.0 nA as well as a responsivity of 0.30 A/W under a bias of 3.5 V. The TIA shows a transimpedance gain of more than 58 dB/spl Omega/ with a -3 dB bandwidth of 2.0 GHz. Opening eye diagrams are demonstrated at bit-rates of 1.25 Gbit/s and 2.5 Gbit/s under a +5 V supply.","PeriodicalId":269944,"journal":{"name":"GaAs IC Symposium. IEEE Gallium Arsenide Integrated Circuit Symposium. 23rd Annual Technical Digest 2001 (Cat. No.01CH37191)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114577195","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-10-21DOI: 10.1109/GAAS.2001.964394
J. Carroll, C. Campbell
The development of a high voltage, wideband E/O modulator driver IC is described. The DC coupled, single-ended amplifier exhibits a 3 dB-bandwidth of 11.5 GHz, 9.5 dB small signal gain, and 14-V/sub pp/ output voltage swing. The IC utilizes a 0.25 /spl mu/m pHEMT production process and provides sufficient bandwidth and output power for 10 Gbit/s high voltage E/O modulator applications.
{"title":"A 14-V/sub pp/ 10 Gbit/s E/O modulator driver IC","authors":"J. Carroll, C. Campbell","doi":"10.1109/GAAS.2001.964394","DOIUrl":"https://doi.org/10.1109/GAAS.2001.964394","url":null,"abstract":"The development of a high voltage, wideband E/O modulator driver IC is described. The DC coupled, single-ended amplifier exhibits a 3 dB-bandwidth of 11.5 GHz, 9.5 dB small signal gain, and 14-V/sub pp/ output voltage swing. The IC utilizes a 0.25 /spl mu/m pHEMT production process and provides sufficient bandwidth and output power for 10 Gbit/s high voltage E/O modulator applications.","PeriodicalId":269944,"journal":{"name":"GaAs IC Symposium. IEEE Gallium Arsenide Integrated Circuit Symposium. 23rd Annual Technical Digest 2001 (Cat. No.01CH37191)","volume":"232 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116045685","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-10-21DOI: 10.1109/GAAS.2001.964357
N. Suematsu, S. Shinjo
Aiming for 2-5GHz band transceiver system on a chip, the integration of RF section has been developed by using conventional CMOS/BiCMOS (SiGeCMOS) process. The attempts to integrate power amplifiers (PA's) have been successful for low transmit power system such as Bluetooth, but these attempts are very limited due to the poor power handling capability of FET's in CMOS and the distortion characteristics of BJT's(HBT's) in BiCMOS. From the point of view of a circuit designer, this paper reviews the recent research activities of CMOS/BiCMOS PA's in Japan, and also describes the details of (1) the feasibility study of PA's using conventional CMOS process, and (2) the circuitry trials of distortion reduction for BJT(HBT) PA's.
{"title":"CMOS/BiCMOS power amplifier technology trend in Japan","authors":"N. Suematsu, S. Shinjo","doi":"10.1109/GAAS.2001.964357","DOIUrl":"https://doi.org/10.1109/GAAS.2001.964357","url":null,"abstract":"Aiming for 2-5GHz band transceiver system on a chip, the integration of RF section has been developed by using conventional CMOS/BiCMOS (SiGeCMOS) process. The attempts to integrate power amplifiers (PA's) have been successful for low transmit power system such as Bluetooth, but these attempts are very limited due to the poor power handling capability of FET's in CMOS and the distortion characteristics of BJT's(HBT's) in BiCMOS. From the point of view of a circuit designer, this paper reviews the recent research activities of CMOS/BiCMOS PA's in Japan, and also describes the details of (1) the feasibility study of PA's using conventional CMOS process, and (2) the circuitry trials of distortion reduction for BJT(HBT) PA's.","PeriodicalId":269944,"journal":{"name":"GaAs IC Symposium. IEEE Gallium Arsenide Integrated Circuit Symposium. 23rd Annual Technical Digest 2001 (Cat. No.01CH37191)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131322199","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-10-21DOI: 10.1109/GAAS.2001.964382
M.H. Miles
Portable electronics such as cellular telephones and laptop computers have produced a surge in battery development and the introduction of rechargeable lithium battery systems. The most dramatic improvement in rechargeable battery technology was the introduction of the lithium-ion battery in 1990. Today, the sale of lithium-ion systems dominates the rechargeable battery market. The cell voltage for any battery system is determined by the selection of the anode and cathode materials, and the electrolyte determines the chemistry of the system and the rate of the electrode reactions. Applications of lithium batteries range from cardiac pacemakers to thermal batteries for military operations. Various types of lithium batteries are discussed. The next major improvement in lithium battery technology will likely be the use of solid polymer electrolytes that provide a truly all-solid-state battery.
{"title":"Recent advances in lithium battery technology","authors":"M.H. Miles","doi":"10.1109/GAAS.2001.964382","DOIUrl":"https://doi.org/10.1109/GAAS.2001.964382","url":null,"abstract":"Portable electronics such as cellular telephones and laptop computers have produced a surge in battery development and the introduction of rechargeable lithium battery systems. The most dramatic improvement in rechargeable battery technology was the introduction of the lithium-ion battery in 1990. Today, the sale of lithium-ion systems dominates the rechargeable battery market. The cell voltage for any battery system is determined by the selection of the anode and cathode materials, and the electrolyte determines the chemistry of the system and the rate of the electrode reactions. Applications of lithium batteries range from cardiac pacemakers to thermal batteries for military operations. Various types of lithium batteries are discussed. The next major improvement in lithium battery technology will likely be the use of solid polymer electrolytes that provide a truly all-solid-state battery.","PeriodicalId":269944,"journal":{"name":"GaAs IC Symposium. IEEE Gallium Arsenide Integrated Circuit Symposium. 23rd Annual Technical Digest 2001 (Cat. No.01CH37191)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131869854","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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