Pub Date : 2020-10-21DOI: 10.1109/ISOCC50952.2020.9333113
Alaaddin Al-Shidaifat, C. Jayawickrama, Yechan Jung, S. Lee, Hanjung Song, N. Kahraman
This work is proposed chaotic true random number generator (TRNG) based on chaotic PWM sequence generator. The chaos CMOS circuit presents here is the chaotic sequence generator. The main components of the chaotic PWM circuit is chaotic sequence generator for chaotic triangular waveforms. The chaotic TRNG was designed by using 0.18μm CMOS process. The full system is prose to be a implementation of IoT secure data communication system using chaotic security.
{"title":"Chaotic True Random Number Generator for Secure Communication Applications","authors":"Alaaddin Al-Shidaifat, C. Jayawickrama, Yechan Jung, S. Lee, Hanjung Song, N. Kahraman","doi":"10.1109/ISOCC50952.2020.9333113","DOIUrl":"https://doi.org/10.1109/ISOCC50952.2020.9333113","url":null,"abstract":"This work is proposed chaotic true random number generator (TRNG) based on chaotic PWM sequence generator. The chaos CMOS circuit presents here is the chaotic sequence generator. The main components of the chaotic PWM circuit is chaotic sequence generator for chaotic triangular waveforms. The chaotic TRNG was designed by using 0.18μm CMOS process. The full system is prose to be a implementation of IoT secure data communication system using chaotic security.","PeriodicalId":270577,"journal":{"name":"2020 International SoC Design Conference (ISOCC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125473178","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-10-21DOI: 10.1109/ISOCC50952.2020.9333048
Thang Xuan Pham, Hanho Lee
In this paper, an efficient check node unit (CNU) architecture with a high output message compression ratio is introduced in order to reduce the hardware resources requirement for non-binary low-density parity-check (NB-LDPC) decoder. The new compression technique is proposed by observing the intrinsic message, where $boldsymbol{L}$ intrinsic messages are able to reduce to $S(S < L)$ group representative values. The hardware implementation results show that the proposed design is able to achieve the lowest hardware consumption and a better clock frequency compared with its predecessors.
{"title":"Efficient Check Node Unit Architecture for Non-binary Quasi-Cyclic LDPC Codes","authors":"Thang Xuan Pham, Hanho Lee","doi":"10.1109/ISOCC50952.2020.9333048","DOIUrl":"https://doi.org/10.1109/ISOCC50952.2020.9333048","url":null,"abstract":"In this paper, an efficient check node unit (CNU) architecture with a high output message compression ratio is introduced in order to reduce the hardware resources requirement for non-binary low-density parity-check (NB-LDPC) decoder. The new compression technique is proposed by observing the intrinsic message, where $boldsymbol{L}$ intrinsic messages are able to reduce to $S(S < L)$ group representative values. The hardware implementation results show that the proposed design is able to achieve the lowest hardware consumption and a better clock frequency compared with its predecessors.","PeriodicalId":270577,"journal":{"name":"2020 International SoC Design Conference (ISOCC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123389408","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-10-21DOI: 10.1109/ISOCC50952.2020.9333098
Takava Watanabe, Hiroki Nishikawa, H. Tomiyama
This paper presents scheduling of rigid tasks on heterogeneous multicore architecture. The proposed technique, based on integer linear programming, determines mapping of tasks and the type of cores to execute each task. The goal is minimization of the overall schedule length. Experimental results show the effectiveness of our scheduling technique.
{"title":"Scheduling of Rigid Tasks on Heterogeneous Multicores","authors":"Takava Watanabe, Hiroki Nishikawa, H. Tomiyama","doi":"10.1109/ISOCC50952.2020.9333098","DOIUrl":"https://doi.org/10.1109/ISOCC50952.2020.9333098","url":null,"abstract":"This paper presents scheduling of rigid tasks on heterogeneous multicore architecture. The proposed technique, based on integer linear programming, determines mapping of tasks and the type of cores to execute each task. The goal is minimization of the overall schedule length. Experimental results show the effectiveness of our scheduling technique.","PeriodicalId":270577,"journal":{"name":"2020 International SoC Design Conference (ISOCC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116592189","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-10-21DOI: 10.1109/ISOCC50952.2020.9332805
Souma Yamamoto, Kuswan Isam Ebisawa, Yudai Abe, Takashi Ida, Y. Shibasaki, N. Tsukiji, A. Kuwana, Haruo Kobayashi, Akira Suzuki, Yukichi Todoroki, Toshihiko Kakinoki, Nobuto Ono, Kazuhiro Miura
This paper analyzes our proposed temperature-insensitive MOS reference current source. It uses a self-bias circuit with feedback configuration, which may cause the circuit instability. Its stability condition has been investigated based on feedback theory as well as simulation.
{"title":"Operation and Stability Analysis of Temperature-Insensitive MOS Reference Current Source with Self-Bias Circuit","authors":"Souma Yamamoto, Kuswan Isam Ebisawa, Yudai Abe, Takashi Ida, Y. Shibasaki, N. Tsukiji, A. Kuwana, Haruo Kobayashi, Akira Suzuki, Yukichi Todoroki, Toshihiko Kakinoki, Nobuto Ono, Kazuhiro Miura","doi":"10.1109/ISOCC50952.2020.9332805","DOIUrl":"https://doi.org/10.1109/ISOCC50952.2020.9332805","url":null,"abstract":"This paper analyzes our proposed temperature-insensitive MOS reference current source. It uses a self-bias circuit with feedback configuration, which may cause the circuit instability. Its stability condition has been investigated based on feedback theory as well as simulation.","PeriodicalId":270577,"journal":{"name":"2020 International SoC Design Conference (ISOCC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123754001","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-10-21DOI: 10.1109/ISOCC50952.2020.9332988
Yixuan He, Minsu Choi, Kyung Ki Kim, Yong-Bin Kim
In this paper, we proposed a nano-power tunable bump circuit. It incorporates a novel source-degenerated transconductor using pseudo-resistor as source resistor to control the width of the bump. The presented circuit is simulated in Cadence using 180nm CMOS process under 1.8V power supply. The results show that the transconductance is tuned with pseudo-resistor and the bump circuit can operate with wide voltage range from 0.3V to 1.8V. Also, this circuit is compact and only dissipates 16.7nW power which makes it perfect for large-scale machine learning applications such as classifier and support vector machine.
{"title":"An Ultra-Low-Power Tunable Bump Circuit using Source-Degenerated Differential Transconductor","authors":"Yixuan He, Minsu Choi, Kyung Ki Kim, Yong-Bin Kim","doi":"10.1109/ISOCC50952.2020.9332988","DOIUrl":"https://doi.org/10.1109/ISOCC50952.2020.9332988","url":null,"abstract":"In this paper, we proposed a nano-power tunable bump circuit. It incorporates a novel source-degenerated transconductor using pseudo-resistor as source resistor to control the width of the bump. The presented circuit is simulated in Cadence using 180nm CMOS process under 1.8V power supply. The results show that the transconductance is tuned with pseudo-resistor and the bump circuit can operate with wide voltage range from 0.3V to 1.8V. Also, this circuit is compact and only dissipates 16.7nW power which makes it perfect for large-scale machine learning applications such as classifier and support vector machine.","PeriodicalId":270577,"journal":{"name":"2020 International SoC Design Conference (ISOCC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115179586","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-10-21DOI: 10.1109/ISOCC50952.2020.9333050
Naoto Yonemoto, Katsuya Nakabai, Y. Uwate, Y. Nishio
This paper considers synchronization phenomena in coupled two-degrees-of-freedom chaotic circuits by a resister. It is considered that studying various cases of synchronization phenomena when using chaotic circuits showing asynchronous simultaneous oscillation will be useful in clarifying non-linear phenomena that exist around us. By means of the circuit experiments and computer simulations, chaotic attractors and Lissajous figures are shown. From the results, synchronization phenomenon was confirmed between the circuits farthest from the connection part.
{"title":"Investigation of Synchronization Phenomena in Coupled Two-degrees-of-Freedom Chaotic Circuits","authors":"Naoto Yonemoto, Katsuya Nakabai, Y. Uwate, Y. Nishio","doi":"10.1109/ISOCC50952.2020.9333050","DOIUrl":"https://doi.org/10.1109/ISOCC50952.2020.9333050","url":null,"abstract":"This paper considers synchronization phenomena in coupled two-degrees-of-freedom chaotic circuits by a resister. It is considered that studying various cases of synchronization phenomena when using chaotic circuits showing asynchronous simultaneous oscillation will be useful in clarifying non-linear phenomena that exist around us. By means of the circuit experiments and computer simulations, chaotic attractors and Lissajous figures are shown. From the results, synchronization phenomenon was confirmed between the circuits farthest from the connection part.","PeriodicalId":270577,"journal":{"name":"2020 International SoC Design Conference (ISOCC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123066664","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-10-21DOI: 10.1109/ISOCC50952.2020.9332804
Manikanta Prahlad Manda, Chan Su Park, ByeongCheol Oh, Dai-Kyung Hyun, Hi-Seok Kim
We propose a simple and fast image thresholding approach for detecting pedestrians in an infrared thermal image. The approach uses the raised cosine distribution function as an analogous function to the one-dimensional histogram of the infrared thermal image. Experiments are conducted on the infrared thermal images gathered from the standard infrared image datasets to describe the performance of the proposed method. The performance is evaluated by comparing the results with state-of-art methods.
{"title":"Pedestrian Detection in Infrared Thermal Images Based on Raised Cosine Distribution","authors":"Manikanta Prahlad Manda, Chan Su Park, ByeongCheol Oh, Dai-Kyung Hyun, Hi-Seok Kim","doi":"10.1109/ISOCC50952.2020.9332804","DOIUrl":"https://doi.org/10.1109/ISOCC50952.2020.9332804","url":null,"abstract":"We propose a simple and fast image thresholding approach for detecting pedestrians in an infrared thermal image. The approach uses the raised cosine distribution function as an analogous function to the one-dimensional histogram of the infrared thermal image. Experiments are conducted on the infrared thermal images gathered from the standard infrared image datasets to describe the performance of the proposed method. The performance is evaluated by comparing the results with state-of-art methods.","PeriodicalId":270577,"journal":{"name":"2020 International SoC Design Conference (ISOCC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115135367","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-10-21DOI: 10.1109/ISOCC50952.2020.9332910
Changmin Ye, V. Kornijcuk, Jeeson Kim, D. Jeong
We propose a hardware-efficient method to implement sequence-predicting spiking neural networks (SPSNN) on a field-programmable gate array board. The SPSNN is capable of sequence-to-sequence prediction (associative recall) when fully trained using the learning by backpropagating action potential (LbAP) algorithm. The key to the hardware-efficiency lies in the rule-based event (routing) method in place of conventional lookup-table-based methods which are memory-hungry methods, particularly, when both forward and inverse lookups should be considered.
{"title":"FPGA implementation of sequence-to-sequence predicting spiking neural networks","authors":"Changmin Ye, V. Kornijcuk, Jeeson Kim, D. Jeong","doi":"10.1109/ISOCC50952.2020.9332910","DOIUrl":"https://doi.org/10.1109/ISOCC50952.2020.9332910","url":null,"abstract":"We propose a hardware-efficient method to implement sequence-predicting spiking neural networks (SPSNN) on a field-programmable gate array board. The SPSNN is capable of sequence-to-sequence prediction (associative recall) when fully trained using the learning by backpropagating action potential (LbAP) algorithm. The key to the hardware-efficiency lies in the rule-based event (routing) method in place of conventional lookup-table-based methods which are memory-hungry methods, particularly, when both forward and inverse lookups should be considered.","PeriodicalId":270577,"journal":{"name":"2020 International SoC Design Conference (ISOCC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133990523","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-10-21DOI: 10.1109/ISOCC50952.2020.9332924
Manhee Cho, Youngmin Kim
Content Addressable Memory (CAM) is a type of memory that searches its contents with data and outputs addresses of matching words. Conventional CAM designs used dynamic CMOS architecture for high match speed and high density, but such implementation requires use of system clocks, and thus suffer from timing violations and design limitations such as charge sharing. In this paper, we propose static based architecture for low-power high-speed Ternary CAM (TCAM), using Nanoelectromechanical (NEM) Memory Switch for nonvolatile data storage. We build 10-bits TCAM word array based on NEM Memory Switch with benefit of low power consumption and low chip density. We design the proposed TCAM architecture on commercial 65-nm process with 1.2 V operating voltage.
{"title":"Nanoelectromechanical Memory Switch based Ternary Content-Addressable Memory","authors":"Manhee Cho, Youngmin Kim","doi":"10.1109/ISOCC50952.2020.9332924","DOIUrl":"https://doi.org/10.1109/ISOCC50952.2020.9332924","url":null,"abstract":"Content Addressable Memory (CAM) is a type of memory that searches its contents with data and outputs addresses of matching words. Conventional CAM designs used dynamic CMOS architecture for high match speed and high density, but such implementation requires use of system clocks, and thus suffer from timing violations and design limitations such as charge sharing. In this paper, we propose static based architecture for low-power high-speed Ternary CAM (TCAM), using Nanoelectromechanical (NEM) Memory Switch for nonvolatile data storage. We build 10-bits TCAM word array based on NEM Memory Switch with benefit of low power consumption and low chip density. We design the proposed TCAM architecture on commercial 65-nm process with 1.2 V operating voltage.","PeriodicalId":270577,"journal":{"name":"2020 International SoC Design Conference (ISOCC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115919016","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-10-21DOI: 10.1109/ISOCC50952.2020.9333120
Joonhong Park, David Kim, Ree Jin Joe, JongWan Jo, Younggun Pu, Kangyoon Lee
This paper presents an integer-N Phase Locked Loop (PLL) for the use in RF wireless charger systems. The presented design supports 4.3 GHz to 6.3 GHz bands using a push-pull Class-C Voltage Controlled Oscillator (VCO) structure. The 2.4 GHz frequency is generated by dividing 4.8 GHz by 2 times to reduce current consumption. Reference spur levels are lower than -45 dBc. The PLL consumes less than 36 mW from a 1.8 V power supply with a settling time less than 40 µs and the area is 1200 µm × 1100 µm in the TSMC 180 nm CMOS process.
{"title":"Multi-band PLL for RF wireless charger at 2.4 GHz and 5.8 GHz","authors":"Joonhong Park, David Kim, Ree Jin Joe, JongWan Jo, Younggun Pu, Kangyoon Lee","doi":"10.1109/ISOCC50952.2020.9333120","DOIUrl":"https://doi.org/10.1109/ISOCC50952.2020.9333120","url":null,"abstract":"This paper presents an integer-N Phase Locked Loop (PLL) for the use in RF wireless charger systems. The presented design supports 4.3 GHz to 6.3 GHz bands using a push-pull Class-C Voltage Controlled Oscillator (VCO) structure. The 2.4 GHz frequency is generated by dividing 4.8 GHz by 2 times to reduce current consumption. Reference spur levels are lower than -45 dBc. The PLL consumes less than 36 mW from a 1.8 V power supply with a settling time less than 40 µs and the area is 1200 µm × 1100 µm in the TSMC 180 nm CMOS process.","PeriodicalId":270577,"journal":{"name":"2020 International SoC Design Conference (ISOCC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115691006","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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