Pub Date : 2020-10-21DOI: 10.1109/ISOCC50952.2020.9332944
Hyun Woo Oh, K. Cho, Seung Eun Lee
In this paper, we propose a 32-bit processor for the embedded system. In order to provide less area and low power operation, we adopt MIPS instruction set architecture (ISA) to our processor. The processor consists of five pipeline stages to reduce the critical path. In order to solve the data hazard in pipeline stages, we design the data forwarding unit and stall unit with optimized bubble insertion. The processor is implemented on a field programmable gate array (FPGA), and we verify the functionality of the processor and measure the performance by using the Dhrystone benchmark. The Dhrystone MIPS (DMIPS) is measured at 27.71 at 50 MHz operation.
{"title":"Design of 32-bit Processor for Embedded Systems","authors":"Hyun Woo Oh, K. Cho, Seung Eun Lee","doi":"10.1109/ISOCC50952.2020.9332944","DOIUrl":"https://doi.org/10.1109/ISOCC50952.2020.9332944","url":null,"abstract":"In this paper, we propose a 32-bit processor for the embedded system. In order to provide less area and low power operation, we adopt MIPS instruction set architecture (ISA) to our processor. The processor consists of five pipeline stages to reduce the critical path. In order to solve the data hazard in pipeline stages, we design the data forwarding unit and stall unit with optimized bubble insertion. The processor is implemented on a field programmable gate array (FPGA), and we verify the functionality of the processor and measure the performance by using the Dhrystone benchmark. The Dhrystone MIPS (DMIPS) is measured at 27.71 at 50 MHz operation.","PeriodicalId":270577,"journal":{"name":"2020 International SoC Design Conference (ISOCC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114631817","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-10-21DOI: 10.1109/ISOCC50952.2020.9333087
Adrian G. Caburnay, Jonathan Gabriel S.A. Reyes, A. Ballesil-Alvarez, M. T. D. Leon, J. Hizon, M. Rosales, Christopher G. Santos, Maria Patricia Rouelli G. Sabino
The effects of varying the Spin Transfer Torque (STT) and Spin Orbit Torque (SOT) currents in a 512KB STT-Assisted SOT MRAM cache to its total cache area, write latency and energy consumption were investigated. The lowest cache write latencies can be achieved when the transistor widths are approximately equal. Out of all transistor sizings, the lowest write latency is 2.95ns with a corresponding cache area of 2.2756mm2. Meanwhile the lowest energy consumption is 441.777 pJ which is when the transistor widths are at their minimum.
{"title":"Design Space Exploration of a 512KB STT-Assisted SOT MRAM Cache","authors":"Adrian G. Caburnay, Jonathan Gabriel S.A. Reyes, A. Ballesil-Alvarez, M. T. D. Leon, J. Hizon, M. Rosales, Christopher G. Santos, Maria Patricia Rouelli G. Sabino","doi":"10.1109/ISOCC50952.2020.9333087","DOIUrl":"https://doi.org/10.1109/ISOCC50952.2020.9333087","url":null,"abstract":"The effects of varying the Spin Transfer Torque (STT) and Spin Orbit Torque (SOT) currents in a 512KB STT-Assisted SOT MRAM cache to its total cache area, write latency and energy consumption were investigated. The lowest cache write latencies can be achieved when the transistor widths are approximately equal. Out of all transistor sizings, the lowest write latency is 2.95ns with a corresponding cache area of 2.2756mm2. Meanwhile the lowest energy consumption is 441.777 pJ which is when the transistor widths are at their minimum.","PeriodicalId":270577,"journal":{"name":"2020 International SoC Design Conference (ISOCC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123410934","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-10-21DOI: 10.1109/ISOCC50952.2020.9333063
S. Venkataramanaiah, Shihui Yin, Yu Cao, Jae-sun Seo
In this invited paper, we present deep neural network (DNN) training accelerator designs in both ASIC and FPGA. The accelerators implements stochastic gradient descent based training algorithm in 16-bit fixed-point precision. A new cyclic weight storage and access scheme enables using the same off-the-shelf SRAMs for non-transpose and transpose operations during feed-forward and feed-backward phases, respectively, of the DNN training process. Including the cyclic weight scheme, the overall DNN training processor is implemented in both 65nm CMOS ASIC and Intel Stratix-10 FPGA hardware. We collectively report the ASIC and FPGA training accelerator results.
{"title":"Deep Neural Network Training Accelerator Designs in ASIC and FPGA","authors":"S. Venkataramanaiah, Shihui Yin, Yu Cao, Jae-sun Seo","doi":"10.1109/ISOCC50952.2020.9333063","DOIUrl":"https://doi.org/10.1109/ISOCC50952.2020.9333063","url":null,"abstract":"In this invited paper, we present deep neural network (DNN) training accelerator designs in both ASIC and FPGA. The accelerators implements stochastic gradient descent based training algorithm in 16-bit fixed-point precision. A new cyclic weight storage and access scheme enables using the same off-the-shelf SRAMs for non-transpose and transpose operations during feed-forward and feed-backward phases, respectively, of the DNN training process. Including the cyclic weight scheme, the overall DNN training processor is implemented in both 65nm CMOS ASIC and Intel Stratix-10 FPGA hardware. We collectively report the ASIC and FPGA training accelerator results.","PeriodicalId":270577,"journal":{"name":"2020 International SoC Design Conference (ISOCC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124012528","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-10-21DOI: 10.1109/ISOCC50952.2020.9333062
A. Mishra, Jinhyuk Kim, Dohyun Kim, J. Cha, Shiho Kim
Absence of human driver inside fully autonomous vehicle (FAV) essentially requires monitoring the in-cabin of such transportation systems. Although, previous researchers claimed inside monitoring of vehicle. However, mostly they have performed diver status monitoring. It is quite insufficient for FAV, and proper in-cabin monitoring is an essential demand to ensure safety and security to both, human and vehicle. In this paper, we have proposed a single artificial intelligence (AI) based camera to monitor and understand in-cabin occupants and their behaviors. Further, requirements of monitoring inside the vehicle cabin has been showcased and various irregular situations have demonstrated which should be considered to provide safe and secure ride to the occupants. Furthermore, we have developed our own database due to very few availabilities of such used cases and dataset. It is to facilitate more research in this domain.
{"title":"An Intelligent In-cabin Monitoring System in Fully Autonomous Vehicles","authors":"A. Mishra, Jinhyuk Kim, Dohyun Kim, J. Cha, Shiho Kim","doi":"10.1109/ISOCC50952.2020.9333062","DOIUrl":"https://doi.org/10.1109/ISOCC50952.2020.9333062","url":null,"abstract":"Absence of human driver inside fully autonomous vehicle (FAV) essentially requires monitoring the in-cabin of such transportation systems. Although, previous researchers claimed inside monitoring of vehicle. However, mostly they have performed diver status monitoring. It is quite insufficient for FAV, and proper in-cabin monitoring is an essential demand to ensure safety and security to both, human and vehicle. In this paper, we have proposed a single artificial intelligence (AI) based camera to monitor and understand in-cabin occupants and their behaviors. Further, requirements of monitoring inside the vehicle cabin has been showcased and various irregular situations have demonstrated which should be considered to provide safe and secure ride to the occupants. Furthermore, we have developed our own database due to very few availabilities of such used cases and dataset. It is to facilitate more research in this domain.","PeriodicalId":270577,"journal":{"name":"2020 International SoC Design Conference (ISOCC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125406336","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-10-21DOI: 10.1109/ISOCC50952.2020.9333117
Muhammad Basim, Danial Khan, Q. Ain, Khuram Shehzad, Muhammad Asif, Kangyoon Lee
In this paper, a self-threshold voltage compensated RF-DC converter operating at 902 MHz is proposed for RF energy harvesting applications. A voltage divider chain consisting of auxiliary transistors is used to provide optimum compensation voltage to the gates of rectifying devices in the main rectification chain. The proposed RF-DC converter is designed and simulated in 180 nm CMOS technology. The simulation results show that the proposed circuit achieves peak power conversion efficiency (PCE) of 40% at -12 dBm input power across 1 MΩ load resistance. The proposed scheme achieves a sensitivity of -20 dBm for 1 MΩ and produces 1 V output voltage.
{"title":"A High Efficient RF-DC Converter for RF Energy Harvesting Applications","authors":"Muhammad Basim, Danial Khan, Q. Ain, Khuram Shehzad, Muhammad Asif, Kangyoon Lee","doi":"10.1109/ISOCC50952.2020.9333117","DOIUrl":"https://doi.org/10.1109/ISOCC50952.2020.9333117","url":null,"abstract":"In this paper, a self-threshold voltage compensated RF-DC converter operating at 902 MHz is proposed for RF energy harvesting applications. A voltage divider chain consisting of auxiliary transistors is used to provide optimum compensation voltage to the gates of rectifying devices in the main rectification chain. The proposed RF-DC converter is designed and simulated in 180 nm CMOS technology. The simulation results show that the proposed circuit achieves peak power conversion efficiency (PCE) of 40% at -12 dBm input power across 1 MΩ load resistance. The proposed scheme achieves a sensitivity of -20 dBm for 1 MΩ and produces 1 V output voltage.","PeriodicalId":270577,"journal":{"name":"2020 International SoC Design Conference (ISOCC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130782527","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-10-21DOI: 10.1109/ISOCC50952.2020.9332918
Donggeun You, Hyunwoo Heo, Hyungseup Kim, Yongsu Kwon, H. Ko, Sangmin Lee
This paper proposes a current feedback instrumentation amplifier (CFIA) with current reuse and power line interference (PLI) mitigation technique for electrocardiogram (ECG) recording. The proposed PLI mitigation circuits are consisted of continuous time common mode current feedback circuit and DC servo loop. The proposed PLI mitigation circuits effectively remove PLI which has tens of volts without electrostatic discharge (ESD) diode saturation and a high-quality ECG signal can be achieved. The proposed current reused CFIA is robust to electrodes mismatch as the current feedback topology has high input impedance. Also, a current reuse scheme in CFIA enables to high Gm/Id efficiency. The proposed circuit is implemented in 180 nm bipolar complementary metal oxide semiconductor double diffused metal oxide semiconductor (BCDMOS).
{"title":"A Current Feedback Instrumentation Amplifier with Current Reuse and Power Line Interference Mitigation Technique for ECG Recording","authors":"Donggeun You, Hyunwoo Heo, Hyungseup Kim, Yongsu Kwon, H. Ko, Sangmin Lee","doi":"10.1109/ISOCC50952.2020.9332918","DOIUrl":"https://doi.org/10.1109/ISOCC50952.2020.9332918","url":null,"abstract":"This paper proposes a current feedback instrumentation amplifier (CFIA) with current reuse and power line interference (PLI) mitigation technique for electrocardiogram (ECG) recording. The proposed PLI mitigation circuits are consisted of continuous time common mode current feedback circuit and DC servo loop. The proposed PLI mitigation circuits effectively remove PLI which has tens of volts without electrostatic discharge (ESD) diode saturation and a high-quality ECG signal can be achieved. The proposed current reused CFIA is robust to electrodes mismatch as the current feedback topology has high input impedance. Also, a current reuse scheme in CFIA enables to high Gm/Id efficiency. The proposed circuit is implemented in 180 nm bipolar complementary metal oxide semiconductor double diffused metal oxide semiconductor (BCDMOS).","PeriodicalId":270577,"journal":{"name":"2020 International SoC Design Conference (ISOCC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115951330","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-10-21DOI: 10.1109/ISOCC50952.2020.9332936
Christian Joseph Dia, Ralfael Himor, A. Alvarez, J. Hizon, M. Rosales, Maria Patricia Rouelli Sabino-Santos, Christopher G. Santos, M. T. D. Leon
The design and implementation of a synchronous electric charge extraction (SECE) interface that is optimized in handling shock inputs for piezoelectric energy harvesters (PEH) is presented in this paper. The electrical efficiency of the system over time is analyzed across different amounts of shock inputs of the PEH. To improve the efficiency of the interface circuit, control signals are adjusted so that harvesting times are optimized based on the remaining energy in the shock input and on the system's power consumption. The average power consumption of the system is around 1.81µW. Overall, the interface circuit achieves at least 82.53 % harvesting efficiency by setting the count of harvesting cycles depending on the characteristics of the shock input.
{"title":"An Interface for Shock Inputs in Piezoelectric Energy Harvesting using Synchronous Electric Charge Extraction","authors":"Christian Joseph Dia, Ralfael Himor, A. Alvarez, J. Hizon, M. Rosales, Maria Patricia Rouelli Sabino-Santos, Christopher G. Santos, M. T. D. Leon","doi":"10.1109/ISOCC50952.2020.9332936","DOIUrl":"https://doi.org/10.1109/ISOCC50952.2020.9332936","url":null,"abstract":"The design and implementation of a synchronous electric charge extraction (SECE) interface that is optimized in handling shock inputs for piezoelectric energy harvesters (PEH) is presented in this paper. The electrical efficiency of the system over time is analyzed across different amounts of shock inputs of the PEH. To improve the efficiency of the interface circuit, control signals are adjusted so that harvesting times are optimized based on the remaining energy in the shock input and on the system's power consumption. The average power consumption of the system is around 1.81µW. Overall, the interface circuit achieves at least 82.53 % harvesting efficiency by setting the count of harvesting cycles depending on the characteristics of the shock input.","PeriodicalId":270577,"journal":{"name":"2020 International SoC Design Conference (ISOCC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116457760","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-10-21DOI: 10.1109/ISOCC50952.2020.9333064
Zelin Meng, Zhiyu Zhang, Lin Meng, Hiroyuki Tomiyama
This paper presents an case study which explored the classification performance of rubbing characters by utilizing deep neural networks. In the evaluation experiments, several mainstream deep neural networks are employed to realize the recognition of the rubbing characters. The purpose of this work is to examine the classification performance of the prevalent neural networks and collect the necessary information for our future works.
{"title":"A Case Study on Rubbing Character Recognition Based on Deep Learning","authors":"Zelin Meng, Zhiyu Zhang, Lin Meng, Hiroyuki Tomiyama","doi":"10.1109/ISOCC50952.2020.9333064","DOIUrl":"https://doi.org/10.1109/ISOCC50952.2020.9333064","url":null,"abstract":"This paper presents an case study which explored the classification performance of rubbing characters by utilizing deep neural networks. In the evaluation experiments, several mainstream deep neural networks are employed to realize the recognition of the rubbing characters. The purpose of this work is to examine the classification performance of the prevalent neural networks and collect the necessary information for our future works.","PeriodicalId":270577,"journal":{"name":"2020 International SoC Design Conference (ISOCC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125727032","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-10-21DOI: 10.1109/ISOCC50952.2020.9332975
Baek Sop Kim, Kangyoon Lee
This paper proposes a technique that uses the Sigma Delta modulator and oscillator to reduce the modulation reference clock in dedicated short range communication (DSRC) applications using Amplitude shift Keying (ASK) modulation. The digital modulator's reference clock is supplied from an oscillator that is frequency-tunable with current and capacitors. Sigma-delta modulator modulates the current of the oscillator to reduce the spur by clock-dithering the components of the digital modulator reference clock occurring at the TX output. The proposed structure is implemented using CMOS 130nm process and uses 1.2V supply power.
{"title":"ASK Modulator Spur reduction using Sigma Delta Modulator and Oscillator","authors":"Baek Sop Kim, Kangyoon Lee","doi":"10.1109/ISOCC50952.2020.9332975","DOIUrl":"https://doi.org/10.1109/ISOCC50952.2020.9332975","url":null,"abstract":"This paper proposes a technique that uses the Sigma Delta modulator and oscillator to reduce the modulation reference clock in dedicated short range communication (DSRC) applications using Amplitude shift Keying (ASK) modulation. The digital modulator's reference clock is supplied from an oscillator that is frequency-tunable with current and capacitors. Sigma-delta modulator modulates the current of the oscillator to reduce the spur by clock-dithering the components of the digital modulator reference clock occurring at the TX output. The proposed structure is implemented using CMOS 130nm process and uses 1.2V supply power.","PeriodicalId":270577,"journal":{"name":"2020 International SoC Design Conference (ISOCC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126749318","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-10-21DOI: 10.1109/ISOCC50952.2020.9333115
K. Bae, Jongsun Park
For an efficient data transmission between logic die and core die in HBM DRAM, Through-Silicon-Via (TSV) is an essential part that connects stacked memories. TSV is a vertical component which cannot be found in the conventional 2D memory. It plays an important role in improving integration in 3D memory structure. However, due to its temporal variation and technological weakness, error cases occur frequently in TSV. Following this, to increase the reliability of the memory operation, fault detection and correction method for TSV is a new challenge in 3D memory. For the efficient fault correction, fault detection method that classifies hard fault and soft error has been studied. In this paper, a new TSV fault detection method using error pattern analysis will be presented. As a result, the proposed scheme shows higher detection success rate with low area overhead, compared to the conventional scheme.
{"title":"Efficient TSV Fault Detection Scheme For High Bandwidth Memory Using Pattern Analysis","authors":"K. Bae, Jongsun Park","doi":"10.1109/ISOCC50952.2020.9333115","DOIUrl":"https://doi.org/10.1109/ISOCC50952.2020.9333115","url":null,"abstract":"For an efficient data transmission between logic die and core die in HBM DRAM, Through-Silicon-Via (TSV) is an essential part that connects stacked memories. TSV is a vertical component which cannot be found in the conventional 2D memory. It plays an important role in improving integration in 3D memory structure. However, due to its temporal variation and technological weakness, error cases occur frequently in TSV. Following this, to increase the reliability of the memory operation, fault detection and correction method for TSV is a new challenge in 3D memory. For the efficient fault correction, fault detection method that classifies hard fault and soft error has been studied. In this paper, a new TSV fault detection method using error pattern analysis will be presented. As a result, the proposed scheme shows higher detection success rate with low area overhead, compared to the conventional scheme.","PeriodicalId":270577,"journal":{"name":"2020 International SoC Design Conference (ISOCC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127781100","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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