Pub Date : 2020-10-21DOI: 10.1109/ISOCC50952.2020.9332961
Yoon Seok Yang, Yongtae Kim
Neuromorphic computing has been studied to implement functions inspired by the human brain such as low power, fine-grained parallel processing, and real-time learning beyond the limitations seen by a standard von Neumann processor. In this paper, Intel's Loihi neuromorphic research chip and its hardware systems are introduced and find out how they are applied and used in actual research fields.
{"title":"Recent Trend of Neuromorphic Computing Hardware: Intel's Neuromorphic System Perspective","authors":"Yoon Seok Yang, Yongtae Kim","doi":"10.1109/ISOCC50952.2020.9332961","DOIUrl":"https://doi.org/10.1109/ISOCC50952.2020.9332961","url":null,"abstract":"Neuromorphic computing has been studied to implement functions inspired by the human brain such as low power, fine-grained parallel processing, and real-time learning beyond the limitations seen by a standard von Neumann processor. In this paper, Intel's Loihi neuromorphic research chip and its hardware systems are introduced and find out how they are applied and used in actual research fields.","PeriodicalId":270577,"journal":{"name":"2020 International SoC Design Conference (ISOCC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134234971","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-10-21DOI: 10.1109/ISOCC50952.2020.9333061
Sunghyun Choi, Jongsun Park
Spiking neural network (SNN) is considered as one of the most promising candidates for designing neuromorphic hardware due to its low power computing capability. Since SNNs are made from imitating features of the human brain, bio-plausible spike-timing-dependent plasticity (STDP) learning rule can be adjusted to perform unsupervised learning of SNN. In this paper, we present a spike count based early termination technique for STDP learning in SNN. To reduce redundant timesteps and calculations, spike counts of output neurons can be used to terminate the training process beforehand, thus latency and energy can be decreased. The proposed scheme reduces 50.7% of timesteps and 51.1% of total weight update during training with 0.35% accuracy drop in MNIST application.
脉冲神经网络(SNN)由于其低功耗的计算能力而被认为是最有前途的神经形态硬件设计候选之一。由于SNN是模仿人类大脑的特征，因此可以调整生物似是而非的spike- time -dependent plasticity (STDP)学习规则来实现SNN的无监督学习。在本文中，我们提出了一种基于尖峰计数的SNN中STDP学习的早期终止技术。为了减少冗余的时间步长和计算，可以使用输出神经元的峰值计数来提前终止训练过程，从而降低延迟和能量。在MNIST应用中，该方案在训练过程中减少了50.7%的时间步长和51.1%的总权重更新，准确率下降了0.35%。
{"title":"Early Termination of STDP Learning with Spike Counts in Spiking Neural Networks","authors":"Sunghyun Choi, Jongsun Park","doi":"10.1109/ISOCC50952.2020.9333061","DOIUrl":"https://doi.org/10.1109/ISOCC50952.2020.9333061","url":null,"abstract":"Spiking neural network (SNN) is considered as one of the most promising candidates for designing neuromorphic hardware due to its low power computing capability. Since SNNs are made from imitating features of the human brain, bio-plausible spike-timing-dependent plasticity (STDP) learning rule can be adjusted to perform unsupervised learning of SNN. In this paper, we present a spike count based early termination technique for STDP learning in SNN. To reduce redundant timesteps and calculations, spike counts of output neurons can be used to terminate the training process beforehand, thus latency and energy can be decreased. The proposed scheme reduces 50.7% of timesteps and 51.1% of total weight update during training with 0.35% accuracy drop in MNIST application.","PeriodicalId":270577,"journal":{"name":"2020 International SoC Design Conference (ISOCC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126596603","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-10-21DOI: 10.1109/ISOCC50952.2020.9333024
Daehyun Koh, Dainel Jeong, Jeongho Hwang, D. Jeong
This paper introduces a 4-channel optical receiver front-end in 180 nm CMOS technology for active optical cable application. The receiver is composed of HDMI 2.0 configuration, occupying area of $2.52 mathrm{mm}^{2}$. Regulated-cascode transimpedance amplifier is used in the chip. Shared inductor and capacitive feedback techniques are applied in limiting amplifiers to enhance bandwidth. The receivers consumes power of 54 mW at the data rate of 6 Gb/s with the energy efficiency of 3 pJ/bit/channel.
{"title":"Optical Receiver Front-end for Active Optical Cable in 180 nm CMOS","authors":"Daehyun Koh, Dainel Jeong, Jeongho Hwang, D. Jeong","doi":"10.1109/ISOCC50952.2020.9333024","DOIUrl":"https://doi.org/10.1109/ISOCC50952.2020.9333024","url":null,"abstract":"This paper introduces a 4-channel optical receiver front-end in 180 nm CMOS technology for active optical cable application. The receiver is composed of HDMI 2.0 configuration, occupying area of $2.52 mathrm{mm}^{2}$. Regulated-cascode transimpedance amplifier is used in the chip. Shared inductor and capacitive feedback techniques are applied in limiting amplifiers to enhance bandwidth. The receivers consumes power of 54 mW at the data rate of 6 Gb/s with the energy efficiency of 3 pJ/bit/channel.","PeriodicalId":270577,"journal":{"name":"2020 International SoC Design Conference (ISOCC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131023497","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-10-21DOI: 10.1109/ISOCC50952.2020.9332927
Jihye Kim, Hayoung Lee, Seokjun Jang, Hogyeong Kim, Sungho Kang
Nanotechnology is considered important as an alternative technology to overcome the limitations of CMOS technology. While nanotechnology has advantages in terms of power, density and performance, it is essential to obtain defect tolerance using reconfiguration due to its high defect rate. To bypass defect elements, accurate defect diagnosis is important for circuit configuration. CMOL FPGAs are circuit structures combining advantages of CMOS and nanotechnology. In this paper, an accurate defect diagnosis method for CMOL FPGAs using an operation similar to the read of CMOL memory are proposed.
{"title":"Memory-like Defect Diagnosis for CMOL FPGAs","authors":"Jihye Kim, Hayoung Lee, Seokjun Jang, Hogyeong Kim, Sungho Kang","doi":"10.1109/ISOCC50952.2020.9332927","DOIUrl":"https://doi.org/10.1109/ISOCC50952.2020.9332927","url":null,"abstract":"Nanotechnology is considered important as an alternative technology to overcome the limitations of CMOS technology. While nanotechnology has advantages in terms of power, density and performance, it is essential to obtain defect tolerance using reconfiguration due to its high defect rate. To bypass defect elements, accurate defect diagnosis is important for circuit configuration. CMOL FPGAs are circuit structures combining advantages of CMOS and nanotechnology. In this paper, an accurate defect diagnosis method for CMOL FPGAs using an operation similar to the read of CMOL memory are proposed.","PeriodicalId":270577,"journal":{"name":"2020 International SoC Design Conference (ISOCC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132155508","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-10-21DOI: 10.1109/ISOCC50952.2020.9332952
Jaeik Cho, Youngmin Kim
In many applications such as multimedia processing, the power may need to be lowered. Error tolerant adder is used to study carry prediction and approximate multiplication in this paper. The delay of addition between partial products and the results of speculative counters is reduced by the optimized Three-Dimensional Matrix (TDM) suggested in [1] when the speculative counters make no error. The results of the optimized TDM trees are added by the speculative adder for error tolerant computations. The power dissipation is lowered by tolerating the generated errors in the computations deliberately. By the speculative adder, the parts of LSB are approximated in total calculation. Instead of making LSB inaccurate, the total power dissipation is lowered.
{"title":"Low Power Approximate Multiplier Using Error Tolerant Adder","authors":"Jaeik Cho, Youngmin Kim","doi":"10.1109/ISOCC50952.2020.9332952","DOIUrl":"https://doi.org/10.1109/ISOCC50952.2020.9332952","url":null,"abstract":"In many applications such as multimedia processing, the power may need to be lowered. Error tolerant adder is used to study carry prediction and approximate multiplication in this paper. The delay of addition between partial products and the results of speculative counters is reduced by the optimized Three-Dimensional Matrix (TDM) suggested in [1] when the speculative counters make no error. The results of the optimized TDM trees are added by the speculative adder for error tolerant computations. The power dissipation is lowered by tolerating the generated errors in the computations deliberately. By the speculative adder, the parts of LSB are approximated in total calculation. Instead of making LSB inaccurate, the total power dissipation is lowered.","PeriodicalId":270577,"journal":{"name":"2020 International SoC Design Conference (ISOCC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132178553","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-10-21DOI: 10.1109/ISOCC50952.2020.9333104
Yudai Abe, A. Iwabuchi, Jun-Ichi Matsuda, A. Kuwana, Takashi Ida, Y. Shibasaki, Haruo Kobayashi
This paper investigates a feasibility of an IGBT driver with current sources to obtain good trade-off between the switching loss and the output voltage overshoot. We consider here an employment of multiple-peak current mirror circuits for the current mode IGBT driver, which can control the current amount in time for pulling the charge from (turn-off case) and pushing one to (turn-on case) the IGBT gate capacitances. We have examined the IGBT turn-off case by pulling the charge from the IGBT gate capacitances, and SPICE simulation results show that our investigated IGBT driver with controlled current sources can achieve lower loss than the one with controlled voltage sources when keeping the overshoot voltage to be equal.
{"title":"Low Power Loss IGBT Driver Circuit Using Current Drive","authors":"Yudai Abe, A. Iwabuchi, Jun-Ichi Matsuda, A. Kuwana, Takashi Ida, Y. Shibasaki, Haruo Kobayashi","doi":"10.1109/ISOCC50952.2020.9333104","DOIUrl":"https://doi.org/10.1109/ISOCC50952.2020.9333104","url":null,"abstract":"This paper investigates a feasibility of an IGBT driver with current sources to obtain good trade-off between the switching loss and the output voltage overshoot. We consider here an employment of multiple-peak current mirror circuits for the current mode IGBT driver, which can control the current amount in time for pulling the charge from (turn-off case) and pushing one to (turn-on case) the IGBT gate capacitances. We have examined the IGBT turn-off case by pulling the charge from the IGBT gate capacitances, and SPICE simulation results show that our investigated IGBT driver with controlled current sources can achieve lower loss than the one with controlled voltage sources when keeping the overshoot voltage to be equal.","PeriodicalId":270577,"journal":{"name":"2020 International SoC Design Conference (ISOCC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132691980","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-10-21DOI: 10.1109/ISOCC50952.2020.9332955
Zubair Mehmood, M. Seo
This paper presents a high speed on-off Keying (OOK) demodulator using distributed approach which is implemented using 28 nm bulk CMOS process. A 100 GHz demodulator post layout full-wave EM simulation results are realized for the data-rate up to 30 Gbps to check the eye diagram at different power levels. The proposed demodulator achieved 50% of eye opening at 30 Gbps for -16 dBm input power. The design consumes 18.5 mW of power and occupies the chip area of 0.135 mm2-,
{"title":"A Wideband Distributed Demodulator at 100 GHz","authors":"Zubair Mehmood, M. Seo","doi":"10.1109/ISOCC50952.2020.9332955","DOIUrl":"https://doi.org/10.1109/ISOCC50952.2020.9332955","url":null,"abstract":"This paper presents a high speed on-off Keying (OOK) demodulator using distributed approach which is implemented using 28 nm bulk CMOS process. A 100 GHz demodulator post layout full-wave EM simulation results are realized for the data-rate up to 30 Gbps to check the eye diagram at different power levels. The proposed demodulator achieved 50% of eye opening at 30 Gbps for -16 dBm input power. The design consumes 18.5 mW of power and occupies the chip area of 0.135 mm2-,","PeriodicalId":270577,"journal":{"name":"2020 International SoC Design Conference (ISOCC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133250117","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-10-21DOI: 10.1109/ISOCC50952.2020.9333074
Hyeonchan Lim, Tae Hyun Kim, Seunghwan Kim, Sungho Kang
In order to improve yield of nanometer-scale chips, scan-based test and diagnosis are important. However, the scan chain can be subject to defects due to large hardware incurred by itself, which accounts for considerable portion of total chip area. Hence, scan chain test and diagnosis has played a critical role in recent years. In this paper, an efficient scan chain diagnosis method based on two-stage neural networks is proposed for not only stuck-at fault but also transition fault. Experimental results on benchmark circuits show that the proposed method is 10% more accurate than a previous work and CPU time for training the neural networks is also reduced dramatically.
{"title":"Diagnosis of Scan Chain Faults Based-on Machine-Learning","authors":"Hyeonchan Lim, Tae Hyun Kim, Seunghwan Kim, Sungho Kang","doi":"10.1109/ISOCC50952.2020.9333074","DOIUrl":"https://doi.org/10.1109/ISOCC50952.2020.9333074","url":null,"abstract":"In order to improve yield of nanometer-scale chips, scan-based test and diagnosis are important. However, the scan chain can be subject to defects due to large hardware incurred by itself, which accounts for considerable portion of total chip area. Hence, scan chain test and diagnosis has played a critical role in recent years. In this paper, an efficient scan chain diagnosis method based on two-stage neural networks is proposed for not only stuck-at fault but also transition fault. Experimental results on benchmark circuits show that the proposed method is 10% more accurate than a previous work and CPU time for training the neural networks is also reduced dramatically.","PeriodicalId":270577,"journal":{"name":"2020 International SoC Design Conference (ISOCC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134613438","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-10-21DOI: 10.1109/ISOCC50952.2020.9332913
Hyunju Kim, Youngmin Kim
Content-Addressable Memory (CAM) is a type of memory searches its contents with data and outputs addresses of matching words. Conventional CAM designs used dynamic CMOS architecture for high match speed and high density, but such implementation requires use of system clocks, and thus suffer from timing violations and design limitations such as charge sharing. Thus, we propose static based architecture for CAM, using Nano-Electro Mechanical (NEM) Memory Switch for nonvolatile data storage. We design the proposed CAM architectures on commercial 65 nm process with 1.2 V operating voltage.
{"title":"Binary Content-Addressable Memory System using Nanoelectromechanical Memory Switch","authors":"Hyunju Kim, Youngmin Kim","doi":"10.1109/ISOCC50952.2020.9332913","DOIUrl":"https://doi.org/10.1109/ISOCC50952.2020.9332913","url":null,"abstract":"Content-Addressable Memory (CAM) is a type of memory searches its contents with data and outputs addresses of matching words. Conventional CAM designs used dynamic CMOS architecture for high match speed and high density, but such implementation requires use of system clocks, and thus suffer from timing violations and design limitations such as charge sharing. Thus, we propose static based architecture for CAM, using Nano-Electro Mechanical (NEM) Memory Switch for nonvolatile data storage. We design the proposed CAM architectures on commercial 65 nm process with 1.2 V operating voltage.","PeriodicalId":270577,"journal":{"name":"2020 International SoC Design Conference (ISOCC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114593770","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-10-21DOI: 10.1109/ISOCC50952.2020.9332958
Sungrae Kim, Hyun Kim
There has been a breakthrough in the field of image classification and object detection, owing to the development of GPU and deep learning. However, because of the huge computation of deep learning, it is hard to use the deep learning algorithms in an embedded platform or a mobile device. Therefore, many compression studies have been conducted, and one of the most popular methods is a parameter quantization. In this paper, we propose an adaptive quantization scheme that reduces the loss of accuracy due to the quantization by properly mixing deterministic and stochastic quantization methods, while retaining the characteristics of the hardware-friendly fixed-point quantization method. By applying the proposed method to the weight parameters of image classification and object detection networks, the proposed method shows better mean average precision (mAP) of up to 0.44% in image classification and 0.91 % in object detection.
{"title":"Mixture of Deterministic and Stochastic Quantization Schemes for Lightweight CNN","authors":"Sungrae Kim, Hyun Kim","doi":"10.1109/ISOCC50952.2020.9332958","DOIUrl":"https://doi.org/10.1109/ISOCC50952.2020.9332958","url":null,"abstract":"There has been a breakthrough in the field of image classification and object detection, owing to the development of GPU and deep learning. However, because of the huge computation of deep learning, it is hard to use the deep learning algorithms in an embedded platform or a mobile device. Therefore, many compression studies have been conducted, and one of the most popular methods is a parameter quantization. In this paper, we propose an adaptive quantization scheme that reduces the loss of accuracy due to the quantization by properly mixing deterministic and stochastic quantization methods, while retaining the characteristics of the hardware-friendly fixed-point quantization method. By applying the proposed method to the weight parameters of image classification and object detection networks, the proposed method shows better mean average precision (mAP) of up to 0.44% in image classification and 0.91 % in object detection.","PeriodicalId":270577,"journal":{"name":"2020 International SoC Design Conference (ISOCC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117136275","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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