Pub Date : 2020-10-21DOI: 10.1109/ISOCC50952.2020.9333096
Sungsoo Cheon, Jongsun Park
SRAM-based In-Memory Computing (IMC) is one of the most promising technique to overcome the innate problems of von-Neumann architecture. However, simultaneously accessing multiple data results in inevitable read disturbance issue. To overcome this drawback, most of the previous works employ Word-Line Under-Drive (WLUD) technique in which Word-Line (WL) driver voltage is lowered. However, WLUD necessarily weakens the access transistors, consequently impairing the performance of the architecture. In this article, new design technique which involves short WL pulse and Bit-Line (BL) boosting scheme is introduced. The proposed architecture does not require much area overhead since it only needs a circuit consisting of only 4 transistors parallelly added to BL. With the proposed technique applied, BL discharge time was shortened to 16.4% at most compared to the conventional architecture.
{"title":"A Bit-Line Boosting Technique for Fast Bit-Line Computation without Read Disturbance","authors":"Sungsoo Cheon, Jongsun Park","doi":"10.1109/ISOCC50952.2020.9333096","DOIUrl":"https://doi.org/10.1109/ISOCC50952.2020.9333096","url":null,"abstract":"SRAM-based In-Memory Computing (IMC) is one of the most promising technique to overcome the innate problems of von-Neumann architecture. However, simultaneously accessing multiple data results in inevitable read disturbance issue. To overcome this drawback, most of the previous works employ Word-Line Under-Drive (WLUD) technique in which Word-Line (WL) driver voltage is lowered. However, WLUD necessarily weakens the access transistors, consequently impairing the performance of the architecture. In this article, new design technique which involves short WL pulse and Bit-Line (BL) boosting scheme is introduced. The proposed architecture does not require much area overhead since it only needs a circuit consisting of only 4 transistors parallelly added to BL. With the proposed technique applied, BL discharge time was shortened to 16.4% at most compared to the conventional architecture.","PeriodicalId":270577,"journal":{"name":"2020 International SoC Design Conference (ISOCC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123496448","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-10-21DOI: 10.1109/ISOCC50952.2020.9333055
Zongjie Shen, Chun Zhao, Li Yang, Cezhou Zhao
In this work, bionic synaptic application of OxRRAM (oxide RRAM) devices with various materials are provided and reviewed, mainly including transition metal oxides and non-metal oxides fabricated by different methodologies. It is possible to stimulate synaptic function in the human brain by electrical signals due to the typical ‘MIM’ sandwich structure and efficient fabrication process of OxRRAM devices. Based on elementary electrical characteristics including switching behavior, endurance performance and retention property, artificial synaptic behaviors mimicked by OxRRAM devices were under investigation, such as potentiation/depression response, long-/short-term plasticity (STP/LTP) and spike-time-dependent plasticity (STDP). In addition, the transition from short-term memory (STM) to longterm memory (LTM) of OxRRAM devices revealed the extensive prospect of its bionic application in artificial neuron network (ANN).
{"title":"Bionic Sypantic Application of OxRRAM Devices","authors":"Zongjie Shen, Chun Zhao, Li Yang, Cezhou Zhao","doi":"10.1109/ISOCC50952.2020.9333055","DOIUrl":"https://doi.org/10.1109/ISOCC50952.2020.9333055","url":null,"abstract":"In this work, bionic synaptic application of OxRRAM (oxide RRAM) devices with various materials are provided and reviewed, mainly including transition metal oxides and non-metal oxides fabricated by different methodologies. It is possible to stimulate synaptic function in the human brain by electrical signals due to the typical ‘MIM’ sandwich structure and efficient fabrication process of OxRRAM devices. Based on elementary electrical characteristics including switching behavior, endurance performance and retention property, artificial synaptic behaviors mimicked by OxRRAM devices were under investigation, such as potentiation/depression response, long-/short-term plasticity (STP/LTP) and spike-time-dependent plasticity (STDP). In addition, the transition from short-term memory (STM) to longterm memory (LTM) of OxRRAM devices revealed the extensive prospect of its bionic application in artificial neuron network (ANN).","PeriodicalId":270577,"journal":{"name":"2020 International SoC Design Conference (ISOCC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116821843","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-10-21DOI: 10.1109/ISOCC50952.2020.9332914
Seung-Yeong Lee, Jae-Hyoung Lee, Hyeonguk Jang, Woojoo Lee
Sadly, tragic accidents caused by leaving a child unattended in a vehicle continue to be reported. The need for systems to prevent such accidents has been raised, but nothing really exists. In this paper, a framework of development of detect the presence of an unattended child in a vehicle is proposed. This framework includes developments of system-on-chip (SoC) platforms, sensor networks, and smartphone applications. As a result of the proposed framework, a full system with a RISC-V core based SoC platform, a sensor network with a precise and energy efficient detection algorithm, and smartphone alarm application is presented. The functional correctness of the detection system is demonstrated with the FPGA prototyping.
{"title":"A Framework for Detecting the Presence of an Unattended Child in a Vehicle","authors":"Seung-Yeong Lee, Jae-Hyoung Lee, Hyeonguk Jang, Woojoo Lee","doi":"10.1109/ISOCC50952.2020.9332914","DOIUrl":"https://doi.org/10.1109/ISOCC50952.2020.9332914","url":null,"abstract":"Sadly, tragic accidents caused by leaving a child unattended in a vehicle continue to be reported. The need for systems to prevent such accidents has been raised, but nothing really exists. In this paper, a framework of development of detect the presence of an unattended child in a vehicle is proposed. This framework includes developments of system-on-chip (SoC) platforms, sensor networks, and smartphone applications. As a result of the proposed framework, a full system with a RISC-V core based SoC platform, a sensor network with a precise and energy efficient detection algorithm, and smartphone alarm application is presented. The functional correctness of the detection system is demonstrated with the FPGA prototyping.","PeriodicalId":270577,"journal":{"name":"2020 International SoC Design Conference (ISOCC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116848348","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-10-21DOI: 10.1109/ISOCC50952.2020.9332983
Youngchang Choi, Sunmean Kim, Seunghan Baek, Seokhyeong Kang
A current-steering ternary DAC is proposed to reduce the power consumption and size while retaining better resolution than conventional binary DACs. By applying the method proposed in this paper, a 4-trit ternary DAC is designed. It operates at 100MHz sampling rate and 1.8V supply voltage, and is implemented in 180nm CMOS technology. Compared to 6-bit binary DAC [5], it reduces power consumption by 31.69% to 30.64 %, and reduces area by 75.48 %.
{"title":"Low-Power 4-Trit Current-Steering DAC for Ternary Data Conversion","authors":"Youngchang Choi, Sunmean Kim, Seunghan Baek, Seokhyeong Kang","doi":"10.1109/ISOCC50952.2020.9332983","DOIUrl":"https://doi.org/10.1109/ISOCC50952.2020.9332983","url":null,"abstract":"A current-steering ternary DAC is proposed to reduce the power consumption and size while retaining better resolution than conventional binary DACs. By applying the method proposed in this paper, a 4-trit ternary DAC is designed. It operates at 100MHz sampling rate and 1.8V supply voltage, and is implemented in 180nm CMOS technology. Compared to 6-bit binary DAC [5], it reduces power consumption by 31.69% to 30.64 %, and reduces area by 75.48 %.","PeriodicalId":270577,"journal":{"name":"2020 International SoC Design Conference (ISOCC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120878353","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-10-21DOI: 10.1109/ISOCC50952.2020.9332931
Hayoung Lee, Donghyun Han, Hogyeong Kim, Sungho Kang
As the probability of fault occurrence increases with the advance of memory density and capacity, redundancy analysis (RA) is widely used for memory yield. However, the conventional RAs progress unnecessary solution search stages since they are applied per memory bank. It results in increase of the repair time. In this paper, redundancy analysis optimization with clustered known solutions (ROCK) is proposed for high speed repair. It progresses repair solution search considering multiple memory banks. During the repair solution search, RA using ROCK finds duplicated solution search stages based on a fault grouping method. After then, RA using ROCK enrolls the duplicated solution search stages as library and utilizes the library instead of progressing the duplicated solution search stages. It can highly reduce the repair time without any repair rate degradation.
{"title":"Redundancy Analysis Optimization with Clustered Known Solutions for High Speed Repair","authors":"Hayoung Lee, Donghyun Han, Hogyeong Kim, Sungho Kang","doi":"10.1109/ISOCC50952.2020.9332931","DOIUrl":"https://doi.org/10.1109/ISOCC50952.2020.9332931","url":null,"abstract":"As the probability of fault occurrence increases with the advance of memory density and capacity, redundancy analysis (RA) is widely used for memory yield. However, the conventional RAs progress unnecessary solution search stages since they are applied per memory bank. It results in increase of the repair time. In this paper, redundancy analysis optimization with clustered known solutions (ROCK) is proposed for high speed repair. It progresses repair solution search considering multiple memory banks. During the repair solution search, RA using ROCK finds duplicated solution search stages based on a fault grouping method. After then, RA using ROCK enrolls the duplicated solution search stages as library and utilizes the library instead of progressing the duplicated solution search stages. It can highly reduce the repair time without any repair rate degradation.","PeriodicalId":270577,"journal":{"name":"2020 International SoC Design Conference (ISOCC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124477752","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-10-21DOI: 10.1109/ISOCC50952.2020.9333105
Malik Summair Asghar, Saad Arslan, Hyungwon Kim
Spiking neural networks performs efficient learning and recognition tasks by mimicking the neural biology of human brain. To realize a large-scale network on chip for mobile applications an area and power optimized electronic neuron along with synapse is essential. In this paper we present an analog CMOS based implementation of neuron and synapse circuits realized using 180nm process. The neurons integrate input currents from the synapse inputs and generate a spike output event based on the membrane potential. The proposed circuits have been optimized for area and power consumption and therefore can be used as key components to form a large spiking neural network.
{"title":"Low Power Spiking Neural Network Circuit with Compact Synapse and Neuron Cells","authors":"Malik Summair Asghar, Saad Arslan, Hyungwon Kim","doi":"10.1109/ISOCC50952.2020.9333105","DOIUrl":"https://doi.org/10.1109/ISOCC50952.2020.9333105","url":null,"abstract":"Spiking neural networks performs efficient learning and recognition tasks by mimicking the neural biology of human brain. To realize a large-scale network on chip for mobile applications an area and power optimized electronic neuron along with synapse is essential. In this paper we present an analog CMOS based implementation of neuron and synapse circuits realized using 180nm process. The neurons integrate input currents from the synapse inputs and generate a spike output event based on the membrane potential. The proposed circuits have been optimized for area and power consumption and therefore can be used as key components to form a large spiking neural network.","PeriodicalId":270577,"journal":{"name":"2020 International SoC Design Conference (ISOCC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126152563","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-10-21DOI: 10.1109/ISOCC50952.2020.9333037
Jooyoon Kim, Jongsun Park
Due to limited scalability and leakage power of CMOS-based logic circuit, Spin Transfer Torque (STT) device, which has the characteristics of a low area, zero leakage power, nonvolatile and infinite endurance, is one of the strongest candidates to overcome limitations of CMOS. Based on these characteristics, efforts have been made to develop STT-device logic circuit. However, STT-device logic circuit has encountered the problem of read reliability. To address read reliability issue, we propose a new Sense amplifier, named variation-tolerant separated precharge sense amplifier. This circuit, by using transmission gate and feedback, is resilient to process variation and has high read reliability. Simulation using the 65nm process is conducted to show the performance of the proposed sensing circuit. Simulation results demonstrate that the reading error rate of the proposed sense amplifier decreased by 68% and 37% respectively, compared to the conventional SPCSA and RESPCSA.
{"title":"Variation-Tolerant Separated Pre-Charge Sense Amplifier for Resistive Non-Volatile logic circuit","authors":"Jooyoon Kim, Jongsun Park","doi":"10.1109/ISOCC50952.2020.9333037","DOIUrl":"https://doi.org/10.1109/ISOCC50952.2020.9333037","url":null,"abstract":"Due to limited scalability and leakage power of CMOS-based logic circuit, Spin Transfer Torque (STT) device, which has the characteristics of a low area, zero leakage power, nonvolatile and infinite endurance, is one of the strongest candidates to overcome limitations of CMOS. Based on these characteristics, efforts have been made to develop STT-device logic circuit. However, STT-device logic circuit has encountered the problem of read reliability. To address read reliability issue, we propose a new Sense amplifier, named variation-tolerant separated precharge sense amplifier. This circuit, by using transmission gate and feedback, is resilient to process variation and has high read reliability. Simulation using the 65nm process is conducted to show the performance of the proposed sensing circuit. Simulation results demonstrate that the reading error rate of the proposed sense amplifier decreased by 68% and 37% respectively, compared to the conventional SPCSA and RESPCSA.","PeriodicalId":270577,"journal":{"name":"2020 International SoC Design Conference (ISOCC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129461876","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-10-21DOI: 10.1109/ISOCC50952.2020.9333028
W. Jung, Jinhyung Lee, Kwangho Lee, Hyojun Kim, D. Jeong
This paper presents the design of the 8.4Gb/s transmitter with a two-tap feed-forward equalizer (FFE) and a 40:1 serializer. The transmitter includes an all-digital phased-locked-loop (ADPLL), a pre-driver and a driver. The simple architecture of the 5:1 serializer achieves low-power consumption by eliminating delay line buffers used to secure timing margin and the selection generator in the conventional 5:1 serializers. The prototype is fabricated in a 40-nm CMOS technology. It offers 72.5-ps eye width, which is 61% of the unit interval and exhibits energy efficiency of 1.66 pJ/bit at 8.4Gb/s.
{"title":"A 8.4Gb/s Low Power Transmitter with 1.66 pJ/b using 40:1 Serializer for DisplayPort Interface","authors":"W. Jung, Jinhyung Lee, Kwangho Lee, Hyojun Kim, D. Jeong","doi":"10.1109/ISOCC50952.2020.9333028","DOIUrl":"https://doi.org/10.1109/ISOCC50952.2020.9333028","url":null,"abstract":"This paper presents the design of the 8.4Gb/s transmitter with a two-tap feed-forward equalizer (FFE) and a 40:1 serializer. The transmitter includes an all-digital phased-locked-loop (ADPLL), a pre-driver and a driver. The simple architecture of the 5:1 serializer achieves low-power consumption by eliminating delay line buffers used to secure timing margin and the selection generator in the conventional 5:1 serializers. The prototype is fabricated in a 40-nm CMOS technology. It offers 72.5-ps eye width, which is 61% of the unit interval and exhibits energy efficiency of 1.66 pJ/bit at 8.4Gb/s.","PeriodicalId":270577,"journal":{"name":"2020 International SoC Design Conference (ISOCC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128269446","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-10-21DOI: 10.1109/ISOCC50952.2020.9333009
L. Chang, Siqi Yang, Jiahao Liu, J. Xiao, Jun Zhou
The reduction of data movement between on-chip and off-chip memory is critical to achieve low power consumption on local devices, such as Internet-of-things. A potential solution is to develop more memory into a single chip. However, the conventional static-random access memory (SRAM) induces high power consumption with large area-overhead for the six-transistor memory cell. The emerging of the one-transistor one resistance (1T1R) nonvolatile memory overcomes SRAM with nearly-zero leakage power, high-density, and non-volatility. In addition, the cross-point (Xpoint) memory without transistor involved into the memory cell becomes promising solution to design ultra-high density memory. In this work, we present a Xpoint-based magnetic RAM (MRAM) using spin-orbit torque magnetic tunnel junction (SOT-MTJ). We provide a balance write scheme to SOT-MTJ and an odd-even array structure to mitigate the sneak current. Moreover, we analyze the impact factors on scalability and stability. The simulation model is developed to evaluate the performance of the proposed Xpoint-based MRAM.
{"title":"Scalability Analysis and Modeling of XPoint-based MRAM","authors":"L. Chang, Siqi Yang, Jiahao Liu, J. Xiao, Jun Zhou","doi":"10.1109/ISOCC50952.2020.9333009","DOIUrl":"https://doi.org/10.1109/ISOCC50952.2020.9333009","url":null,"abstract":"The reduction of data movement between on-chip and off-chip memory is critical to achieve low power consumption on local devices, such as Internet-of-things. A potential solution is to develop more memory into a single chip. However, the conventional static-random access memory (SRAM) induces high power consumption with large area-overhead for the six-transistor memory cell. The emerging of the one-transistor one resistance (1T1R) nonvolatile memory overcomes SRAM with nearly-zero leakage power, high-density, and non-volatility. In addition, the cross-point (Xpoint) memory without transistor involved into the memory cell becomes promising solution to design ultra-high density memory. In this work, we present a Xpoint-based magnetic RAM (MRAM) using spin-orbit torque magnetic tunnel junction (SOT-MTJ). We provide a balance write scheme to SOT-MTJ and an odd-even array structure to mitigate the sneak current. Moreover, we analyze the impact factors on scalability and stability. The simulation model is developed to evaluate the performance of the proposed Xpoint-based MRAM.","PeriodicalId":270577,"journal":{"name":"2020 International SoC Design Conference (ISOCC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130873080","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-10-21DOI: 10.1109/ISOCC50952.2020.9333003
M. Kim, Kangyoon Lee
This paper proposes A Design of charge pump for fast rising and falling time and adequate for Sigma Delta Modulation (SDM). Low Noise Phase-Locked Loop (PLL) architecture using reference clock quadrature is shown. The degree of noise performance improvement that can be obtained using clock quadrature is expressed in an expression. To fulfill the speed of the quadrupled reference clock, fully differential charge pump (CP) architecture is used. Also, Implemented the design of a unity gain buffer in charge pump for the optimized operation for Sigma Delta Modulation (SDM) which is also adequate for wide bandwidth PLL because of the high bandwidth and the ability to handle high load current. The proposed structure is implemented using CMOS 40nm process and uses 1.1V supply power.
{"title":"A Design of Charge Pump for Low Noise Phase-Locked Loops using Clock Quadrature","authors":"M. Kim, Kangyoon Lee","doi":"10.1109/ISOCC50952.2020.9333003","DOIUrl":"https://doi.org/10.1109/ISOCC50952.2020.9333003","url":null,"abstract":"This paper proposes A Design of charge pump for fast rising and falling time and adequate for Sigma Delta Modulation (SDM). Low Noise Phase-Locked Loop (PLL) architecture using reference clock quadrature is shown. The degree of noise performance improvement that can be obtained using clock quadrature is expressed in an expression. To fulfill the speed of the quadrupled reference clock, fully differential charge pump (CP) architecture is used. Also, Implemented the design of a unity gain buffer in charge pump for the optimized operation for Sigma Delta Modulation (SDM) which is also adequate for wide bandwidth PLL because of the high bandwidth and the ability to handle high load current. The proposed structure is implemented using CMOS 40nm process and uses 1.1V supply power.","PeriodicalId":270577,"journal":{"name":"2020 International SoC Design Conference (ISOCC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131239468","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：