Pub Date : 2020-10-21DOI: 10.1109/ISOCC50952.2020.9333018
Cheng-Hsien Chen, Yeong-Kang Lai
For the human eye, the conversion of light intensity through optic nerve is a non-linear conversion. Therefore, the differences of color caused by light intensity will be reduced by this mechanism. However, the conversion of light for the photosensor in camera is linear conversion, which also causes great influence on the image. Semantic segmentation could be known as a pixel-wise classifier. This technique can be implemented by machine learning or deep learning. In deep learning, the difference in light intensity has a relatively low impact because of relatively strong learning ability. For machine learning algorithms, it will have a significant impact because the classification method is based on RGB values. In this study, the light intensity of the training data would be calibrated and then the random forest model trained from the processed datasets would be compared with the model trained from the unprocessed datasets.
{"title":"The Influence Measures of Light Intensity on Machine Learning for Semantic Segmentation","authors":"Cheng-Hsien Chen, Yeong-Kang Lai","doi":"10.1109/ISOCC50952.2020.9333018","DOIUrl":"https://doi.org/10.1109/ISOCC50952.2020.9333018","url":null,"abstract":"For the human eye, the conversion of light intensity through optic nerve is a non-linear conversion. Therefore, the differences of color caused by light intensity will be reduced by this mechanism. However, the conversion of light for the photosensor in camera is linear conversion, which also causes great influence on the image. Semantic segmentation could be known as a pixel-wise classifier. This technique can be implemented by machine learning or deep learning. In deep learning, the difference in light intensity has a relatively low impact because of relatively strong learning ability. For machine learning algorithms, it will have a significant impact because the classification method is based on RGB values. In this study, the light intensity of the training data would be calibrated and then the random forest model trained from the processed datasets would be compared with the model trained from the unprocessed datasets.","PeriodicalId":270577,"journal":{"name":"2020 International SoC Design Conference (ISOCC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124625625","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-10-21DOI: 10.1109/ISOCC50952.2020.9333014
Shiyu Yang, Peilin Liu, Jianwei Xue, Rongdi Sun, R. Ying
This paper presents a modified Izhikevich neuron model replacing complex multiplication and division operations with simple binary-based shift operations. A counter-based adder circuit is designed to address the problem that multiple neurons fire spikes simultaneously to one neuron. The proposed model is implemented on FPGA. Results show that the hardware resource utilization of the proposed model is reduced by 87.2% compared with that of the original model and the highest operating frequency is increased from 123.8MHz to 291.8MHz.
{"title":"An Efficient FPGA Implementation of Izhikevich Neuron Model","authors":"Shiyu Yang, Peilin Liu, Jianwei Xue, Rongdi Sun, R. Ying","doi":"10.1109/ISOCC50952.2020.9333014","DOIUrl":"https://doi.org/10.1109/ISOCC50952.2020.9333014","url":null,"abstract":"This paper presents a modified Izhikevich neuron model replacing complex multiplication and division operations with simple binary-based shift operations. A counter-based adder circuit is designed to address the problem that multiple neurons fire spikes simultaneously to one neuron. The proposed model is implemented on FPGA. Results show that the hardware resource utilization of the proposed model is reduced by 87.2% compared with that of the original model and the highest operating frequency is increased from 123.8MHz to 291.8MHz.","PeriodicalId":270577,"journal":{"name":"2020 International SoC Design Conference (ISOCC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129796853","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-10-21DOI: 10.1109/ISOCC50952.2020.9332915
Hyeokjoon Yang, Hyunbae Lee, Hanseul Kim, Sangwook Park, J. Burm
This paper presents a 2MS/$s$ 12-bit SAR ADC with RC two-step scheme. The SAR ADC has trade-off between size and high-resolution specification. The capacitor array has size problem because total capacitance of capacitor array increases exponentially as the ADC resolution increase. To overcome this issue, the proposed SAR ADC is used the resistor array with the capacitor array. Also, the proposed SAR ADC applied different bit-cycling time for each bit. A prototype ADC was implemented in a 28-nm CMOS technology. The chip consumes 221µW under a 1.0-V supply. The ADC core occupies an active area of 0.02mm x 0.79mm.
本文提出了一种采用RC两步法的2MS/$s$ 12位SAR ADC。SAR ADC需要在尺寸和高分辨率规格之间进行权衡。随着ADC分辨率的提高，电容阵列的总电容呈指数级增长，因此电容阵列存在尺寸问题。为了克服这一问题，本文提出的SAR ADC采用电阻阵列和电容阵列。此外，所提出的SAR ADC对每个比特采用不同的比特循环时间。采用28纳米CMOS技术实现了原型ADC。在1.0 v电源下，芯片功耗为221µW。ADC核心的有效面积为0.02mm x 0.79mm。
{"title":"A 12-b 2 MS/s R-C Two-Step SAR ADC with Bit-Cycling Time Control and LSB Correction Logic","authors":"Hyeokjoon Yang, Hyunbae Lee, Hanseul Kim, Sangwook Park, J. Burm","doi":"10.1109/ISOCC50952.2020.9332915","DOIUrl":"https://doi.org/10.1109/ISOCC50952.2020.9332915","url":null,"abstract":"This paper presents a 2MS/$s$ 12-bit SAR ADC with RC two-step scheme. The SAR ADC has trade-off between size and high-resolution specification. The capacitor array has size problem because total capacitance of capacitor array increases exponentially as the ADC resolution increase. To overcome this issue, the proposed SAR ADC is used the resistor array with the capacitor array. Also, the proposed SAR ADC applied different bit-cycling time for each bit. A prototype ADC was implemented in a 28-nm CMOS technology. The chip consumes 221µW under a 1.0-V supply. The ADC core occupies an active area of 0.02mm x 0.79mm.","PeriodicalId":270577,"journal":{"name":"2020 International SoC Design Conference (ISOCC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123877781","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-10-21DOI: 10.1109/ISOCC50952.2020.9333067
Takuma Hikida, Hiroki Nishikawa, H. Tomiyama
Dynamic scheduling of parallel tasks is one of efficient techniques to achieve high performance in multi-core systems where resources are managed at runtime. Most existing algorithms for dynamic task scheduling assume that a task runs on one of multiple cores. This paper presents heuristic algorithms for dynamic scheduling of parallel tasks, to which the number of cores assigned is flexible and decided at runtime. In the experiments, we compared the proposed algorithms with the existing ones.
{"title":"Heuristic Algorithms for Dynamic Scheduling of Moldable Tasks","authors":"Takuma Hikida, Hiroki Nishikawa, H. Tomiyama","doi":"10.1109/ISOCC50952.2020.9333067","DOIUrl":"https://doi.org/10.1109/ISOCC50952.2020.9333067","url":null,"abstract":"Dynamic scheduling of parallel tasks is one of efficient techniques to achieve high performance in multi-core systems where resources are managed at runtime. Most existing algorithms for dynamic task scheduling assume that a task runs on one of multiple cores. This paper presents heuristic algorithms for dynamic scheduling of parallel tasks, to which the number of cores assigned is flexible and decided at runtime. In the experiments, we compared the proposed algorithms with the existing ones.","PeriodicalId":270577,"journal":{"name":"2020 International SoC Design Conference (ISOCC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121205951","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-10-21DOI: 10.1109/ISOCC50952.2020.9333023
Y. Uwate, Y. Nishio, T. Ott
In this study, we focus on an effect of frustration to polygonal oscillatory network with stochastically coupling. We propose a coupled nonliear circuit network with stochastically coupling. Frustration as environmental factor is occurred by network topology which is composed from polygonal structure. We investigate synchronization of the proposed network using different frustration levels by changing the coupling strength. By using computer simulations, the effect of frustration to polygonal oscillatory networks with stochastically coupling is shown.
{"title":"Frustrated Complex Networks of Nonlinear Circuits With Stochastically Coupling","authors":"Y. Uwate, Y. Nishio, T. Ott","doi":"10.1109/ISOCC50952.2020.9333023","DOIUrl":"https://doi.org/10.1109/ISOCC50952.2020.9333023","url":null,"abstract":"In this study, we focus on an effect of frustration to polygonal oscillatory network with stochastically coupling. We propose a coupled nonliear circuit network with stochastically coupling. Frustration as environmental factor is occurred by network topology which is composed from polygonal structure. We investigate synchronization of the proposed network using different frustration levels by changing the coupling strength. By using computer simulations, the effect of frustration to polygonal oscillatory networks with stochastically coupling is shown.","PeriodicalId":270577,"journal":{"name":"2020 International SoC Design Conference (ISOCC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124515196","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-10-21DOI: 10.1109/ISOCC50952.2020.9333051
Seong-Bin Choi, Sang-Seol Lee, Jonghee Park, Sung-Joon Jang, Byung-Ho Choi
Recent advanced in CNN acceleration systems using hardware and software co-design for real-time object detection and recognition, the speedup of post processing can reduce the burden of designing the acceleration logic to meet the real-time goal. In this paper, we propose an optimization method that eliminates the operation of acquiring redundant bounding boxes without degrading performance. It is implemented on a Xilinx Zynq Ultrascale+ MPSoC ZCU106 and shows the performance improvement about 20% that of the conventional method.
{"title":"Efficient final output feature map processing method supporting real-time object detection and recognition","authors":"Seong-Bin Choi, Sang-Seol Lee, Jonghee Park, Sung-Joon Jang, Byung-Ho Choi","doi":"10.1109/ISOCC50952.2020.9333051","DOIUrl":"https://doi.org/10.1109/ISOCC50952.2020.9333051","url":null,"abstract":"Recent advanced in CNN acceleration systems using hardware and software co-design for real-time object detection and recognition, the speedup of post processing can reduce the burden of designing the acceleration logic to meet the real-time goal. In this paper, we propose an optimization method that eliminates the operation of acquiring redundant bounding boxes without degrading performance. It is implemented on a Xilinx Zynq Ultrascale+ MPSoC ZCU106 and shows the performance improvement about 20% that of the conventional method.","PeriodicalId":270577,"journal":{"name":"2020 International SoC Design Conference (ISOCC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124119857","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-10-21DOI: 10.1109/ISOCC50952.2020.9333025
Chung-Bin Wu, Y. Hwang, Yu-Cheng Hsueh, Yu-Kuan Hsiao
This paper proposes a neural network accelerator for Tiny-Yolo V2. The data format of input feature maps, output feature maps, and weight kernels are converted to uint8 through a quantization strategy to reduce the data size and make the hardware utilization more efficient. Moreover, we propose an input feature maps placement method to reduce bandwidth utilization and improve PE utilization. To verify the hardware implementation, the Xilinx ZCU102 platform is used to verify the hardware architecture. Synthesis results show that the proposed architecture implements in 90nm can achieve 14.4GOPS@100Mhz with area efficiency by 99 GOPS/M-gates.
{"title":"High Efficient Bandwidth Utilization Hardware Design and Implement for AI Deep Learning Accelerator","authors":"Chung-Bin Wu, Y. Hwang, Yu-Cheng Hsueh, Yu-Kuan Hsiao","doi":"10.1109/ISOCC50952.2020.9333025","DOIUrl":"https://doi.org/10.1109/ISOCC50952.2020.9333025","url":null,"abstract":"This paper proposes a neural network accelerator for Tiny-Yolo V2. The data format of input feature maps, output feature maps, and weight kernels are converted to uint8 through a quantization strategy to reduce the data size and make the hardware utilization more efficient. Moreover, we propose an input feature maps placement method to reduce bandwidth utilization and improve PE utilization. To verify the hardware implementation, the Xilinx ZCU102 platform is used to verify the hardware architecture. Synthesis results show that the proposed architecture implements in 90nm can achieve 14.4GOPS@100Mhz with area efficiency by 99 GOPS/M-gates.","PeriodicalId":270577,"journal":{"name":"2020 International SoC Design Conference (ISOCC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125731331","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-10-21DOI: 10.1109/ISOCC50952.2020.9333034
Quan-Dung Pham, X. Nguyen, Hyuk-Jae Lee, Hyun Kim
Light Detection and Ranging (LiDAR) sensors have relatively low resolutions, require considerable time to acquire the laser range measurement, and store large-scale point clouds. In order to address these issues, this paper presents a sampling algorithm which finds the optimal sampling rates in a region of interest (ROI) to minimize the total mean-absolute-error (MAE). Eventually, MAEs in both ROIs and overall scene decrease significantly. Experimental results show that the proposed scheme reduces the MAE in the object area by up to 63.3% and that in the overall scene by up to 34.2%.
{"title":"An MAE-aware ROI Sampling Model for LiDAR","authors":"Quan-Dung Pham, X. Nguyen, Hyuk-Jae Lee, Hyun Kim","doi":"10.1109/ISOCC50952.2020.9333034","DOIUrl":"https://doi.org/10.1109/ISOCC50952.2020.9333034","url":null,"abstract":"Light Detection and Ranging (LiDAR) sensors have relatively low resolutions, require considerable time to acquire the laser range measurement, and store large-scale point clouds. In order to address these issues, this paper presents a sampling algorithm which finds the optimal sampling rates in a region of interest (ROI) to minimize the total mean-absolute-error (MAE). Eventually, MAEs in both ROIs and overall scene decrease significantly. Experimental results show that the proposed scheme reduces the MAE in the object area by up to 63.3% and that in the overall scene by up to 34.2%.","PeriodicalId":270577,"journal":{"name":"2020 International SoC Design Conference (ISOCC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115944667","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-10-21DOI: 10.1109/ISOCC50952.2020.9333015
Tsuyoshi Isozaki, Takumi Nara, Y. Uwate, Y. Nishio
Complex networks have been the subject of great interest. Some characteristics of complex networks are closely related to the real world network and have been studied in terms of network topology and interactions between nodes. In this study, we build three networks which are composed of van der Pol oscillator and investigate synchronization phenomena in each network. As a result, it was confirmed that the synchronization states are different depending on the network structure.
{"title":"Analysis of Synchronization Phenomena in Complex Networks Consisting of van der Pol Oscillators","authors":"Tsuyoshi Isozaki, Takumi Nara, Y. Uwate, Y. Nishio","doi":"10.1109/ISOCC50952.2020.9333015","DOIUrl":"https://doi.org/10.1109/ISOCC50952.2020.9333015","url":null,"abstract":"Complex networks have been the subject of great interest. Some characteristics of complex networks are closely related to the real world network and have been studied in terms of network topology and interactions between nodes. In this study, we build three networks which are composed of van der Pol oscillator and investigate synchronization phenomena in each network. As a result, it was confirmed that the synchronization states are different depending on the network structure.","PeriodicalId":270577,"journal":{"name":"2020 International SoC Design Conference (ISOCC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130172024","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-10-21DOI: 10.1109/ISOCC50952.2020.9332926
Seungho Lee, Youngmin Kim
This paper suggests the efficient implementation of Modular Subtraction Unit for NTT-based polynomial multiplier on ASIC design. We will introduce the basic algorithms of Number Theoretic Transform (NTT) and the Modular Arithmetic briefly, compare the implementation of the modular subtraction unit with the one which suggested in [1] by intuitive way. We reduced about 30% transistors in 17-bit Modular Subtraction Unit.
{"title":"Implementation of Modular Subtraction Unit for NTT-based Polynomial Multiplier","authors":"Seungho Lee, Youngmin Kim","doi":"10.1109/ISOCC50952.2020.9332926","DOIUrl":"https://doi.org/10.1109/ISOCC50952.2020.9332926","url":null,"abstract":"This paper suggests the efficient implementation of Modular Subtraction Unit for NTT-based polynomial multiplier on ASIC design. We will introduce the basic algorithms of Number Theoretic Transform (NTT) and the Modular Arithmetic briefly, compare the implementation of the modular subtraction unit with the one which suggested in [1] by intuitive way. We reduced about 30% transistors in 17-bit Modular Subtraction Unit.","PeriodicalId":270577,"journal":{"name":"2020 International SoC Design Conference (ISOCC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134198919","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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