Pub Date : 1991-10-26DOI: 10.1109/TEST.1991.519792
C. Hawkins, Richard H. Williams
Times are changing. Products are more sophisticated; consumers expect higher quality, lower costs, and negligible hazards for people and environment; and competition dictates an ever reduced time between a product's concept and actual production. These changes demand that engineering education be re-evaluated. What are the relations between manufacturing and engineering education? Engineering education must put all components of manufacturing into context. It is not adversarial with the research and development component. Rather, we take the attitude of "concurrent engineering" [2] in placing R&D as a key member of a team with engineering design, manufacturing design, and the other disciplines.
{"title":"EE CURRICULUM - CONTINUOUS PROCESS IMPROVEMENT?","authors":"C. Hawkins, Richard H. Williams","doi":"10.1109/TEST.1991.519792","DOIUrl":"https://doi.org/10.1109/TEST.1991.519792","url":null,"abstract":"Times are changing. Products are more sophisticated; consumers expect higher quality, lower costs, and negligible hazards for people and environment; and competition dictates an ever reduced time between a product's concept and actual production. These changes demand that engineering education be re-evaluated. What are the relations between manufacturing and engineering education? Engineering education must put all components of manufacturing into context. It is not adversarial with the research and development component. Rather, we take the attitude of \"concurrent engineering\" [2] in placing R&D as a key member of a team with engineering design, manufacturing design, and the other disciplines.","PeriodicalId":272630,"journal":{"name":"1991, Proceedings. International Test Conference","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125600960","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-10-26DOI: 10.1109/TEST.1991.519900
M. Katoozi, Arnold Nordsiek
A method for the design of built-in testable (BIT) error detection and correction (EDAC) circuits is presented reducing test hardware by >50%. A lp CMOS, 16-bit EDAC designed and fabricated with this technique exhibits >99% fault coverage in 10 p at 25 MHz. Built-in test impacts the speed performance by only one gate delay regardless of the size of the EDAC. Various faults are injected into the chip to verifr the effectiveness of built-in test.
{"title":"Low overhead built-in testable error detection and correction with excellent fault coverage","authors":"M. Katoozi, Arnold Nordsiek","doi":"10.1109/TEST.1991.519900","DOIUrl":"https://doi.org/10.1109/TEST.1991.519900","url":null,"abstract":"A method for the design of built-in testable (BIT) error detection and correction (EDAC) circuits is presented reducing test hardware by >50%. A lp CMOS, 16-bit EDAC designed and fabricated with this technique exhibits >99% fault coverage in 10 p at 25 MHz. Built-in test impacts the speed performance by only one gate delay regardless of the size of the EDAC. Various faults are injected into the chip to verifr the effectiveness of built-in test.","PeriodicalId":272630,"journal":{"name":"1991, Proceedings. International Test Conference","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125971246","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-10-26DOI: 10.1109/TEST.1991.519757
K. De, P. Banerjee
{"title":"Logic Partitioning and Resynthesis for Testability","authors":"K. De, P. Banerjee","doi":"10.1109/TEST.1991.519757","DOIUrl":"https://doi.org/10.1109/TEST.1991.519757","url":null,"abstract":"","PeriodicalId":272630,"journal":{"name":"1991, Proceedings. International Test Conference","volume":"76 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125975674","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-10-26DOI: 10.1109/TEST.1991.519744
D. Keezer
A system hus been described [I -61 for testing digital ECL or GaAs devices at rates above 1 Gbps. This system utilizes GaAs multiplexers for combining data ffom several (4 or 8) tester channels to form high speed data sources which are then used as DUT stimuli. Until recently, one of the main limitations of this approach has been the lack of comparable performance &multiplexers or, alternatively real time comparator electronics. In place of these, multi-pass testing can be used if the test system comparators have a high enough bandwrdth [7]. In ths paper, recent enhancements to the data generation electronics of the UHF test system are first reviewed. Next, designs are presented for high speed comparison circuits. These perform real-time comparison of DUT output patterns with expected data at rates above 500 Mbps.
{"title":"REAL-TIME DATA COMPARISON FOR GIGAHERTZ DIGITAL TEST","authors":"D. Keezer","doi":"10.1109/TEST.1991.519744","DOIUrl":"https://doi.org/10.1109/TEST.1991.519744","url":null,"abstract":"A system hus been described [I -61 for testing digital ECL or GaAs devices at rates above 1 Gbps. This system utilizes GaAs multiplexers for combining data ffom several (4 or 8) tester channels to form high speed data sources which are then used as DUT stimuli. Until recently, one of the main limitations of this approach has been the lack of comparable performance &multiplexers or, alternatively real time comparator electronics. In place of these, multi-pass testing can be used if the test system comparators have a high enough bandwrdth [7]. In ths paper, recent enhancements to the data generation electronics of the UHF test system are first reviewed. Next, designs are presented for high speed comparison circuits. These perform real-time comparison of DUT output patterns with expected data at rates above 500 Mbps.","PeriodicalId":272630,"journal":{"name":"1991, Proceedings. International Test Conference","volume":"234 ","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113984002","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-10-26DOI: 10.1109/TEST.1991.519731
S. Mohan, P. Mazumder
Gallium Arsenide memories, which are now beginning to be used commercially, are subject to certain unusual parametric faults, not normally seen in silicon or other memory devices. This paper analyzes the causes of these parametric faults by first mapping the observed errors in the fabrication process to circuit behavior; these modified circuits are then shown to cause new types of pattern-sensitive faults and data retention problems. It is shown that by slightly modifying and reordering existing test procedures, all faults in these RAM’s can be adequately tesled.
{"title":"FAULT MODELING AND TESTING OF GaAs STATIC RANDOM ACCESS MEMORIES","authors":"S. Mohan, P. Mazumder","doi":"10.1109/TEST.1991.519731","DOIUrl":"https://doi.org/10.1109/TEST.1991.519731","url":null,"abstract":"Gallium Arsenide memories, which are now beginning to be used commercially, are subject to certain unusual parametric faults, not normally seen in silicon or other memory devices. This paper analyzes the causes of these parametric faults by first mapping the observed errors in the fabrication process to circuit behavior; these modified circuits are then shown to cause new types of pattern-sensitive faults and data retention problems. It is shown that by slightly modifying and reordering existing test procedures, all faults in these RAM’s can be adequately tesled.","PeriodicalId":272630,"journal":{"name":"1991, Proceedings. International Test Conference","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129537621","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-10-26DOI: 10.1109/TEST.1991.519504
J. Karlsson, U. Gunneflo, P. Lidén, J. Torin
Two fault injection techniques for experimental validation of fault handling mechanisms in computer systems are investigated and compared. One technique is based on irradiation of ICs with heavy-ion radiation from a 252Cf source. The other technique uses voltage sags injected in the power supply rails to ICs. Both techniques have been used for fault injection experiments with the MC6809E microprocessor. Most errors generated by the 252Cf method were seen first in the address bus, while the power supply disturbances most frequently affected the control signals. An error classification shows that both methods generate many control flow errors, while pure data errors are infrequent. Results from a simulation experiment show that that the low number data errors in the 252Cf experiments can be explained by the fact that many errors in data registers are overwritten owing to the normal program execution.
{"title":"TWO FAULT INJECTION TECHNIQUES FOR TEST OF FAULT HANDLING MECHANISMS","authors":"J. Karlsson, U. Gunneflo, P. Lidén, J. Torin","doi":"10.1109/TEST.1991.519504","DOIUrl":"https://doi.org/10.1109/TEST.1991.519504","url":null,"abstract":"Two fault injection techniques for experimental validation of fault handling mechanisms in computer systems are investigated and compared. One technique is based on irradiation of ICs with heavy-ion radiation from a 252Cf source. The other technique uses voltage sags injected in the power supply rails to ICs. Both techniques have been used for fault injection experiments with the MC6809E microprocessor. Most errors generated by the 252Cf method were seen first in the address bus, while the power supply disturbances most frequently affected the control signals. An error classification shows that both methods generate many control flow errors, while pure data errors are infrequent. Results from a simulation experiment show that that the low number data errors in the 252Cf experiments can be explained by the fact that many errors in data registers are overwritten owing to the normal program execution.","PeriodicalId":272630,"journal":{"name":"1991, Proceedings. International Test Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131305017","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-10-26DOI: 10.1109/TEST.1991.519517
K. Helmreich, P. Nagel, W. Wolz, K. Müller-Glaser
An innovative measurement and imaging technique for electron beam testers is introduced, that promises to expand the present applicability of such systems for chip-internal voltage measurements by the capability of chip-internal current measurement. The theoretical principles of the method are discussed and the effect is calculated analytically for a model arrangement. For more realistic measurement situations, the results of numerical calculations, showing the strength of the effect and its dependency of situational parameters, are presented. First experimental results are added. 1 MOTIVATION During the last years, the market share of mixed-signal designs could be observed to be continously increasing. This tendency led to the introduction of dedicated mixedsignal test systems. For prototype debugging of purely digital circuits, internal measurement tools like electron beam !esters (EBTs) have proved to be valuable and at the moment efforts are undertaken to enhance these tools also for application to mixed-signal circuils. The main task herewith is to improve the voltage resolution of the EBT by reducing system-inherent noise. Thus the measurement of analog voltage signals becomes available at an acceptable signal-to-noise ratio [Gar 871. However, information in analog circuitry is often carried by currents and therefore not accessible for measurement with an electron beam tester. On the other hand, the capability of measuring supply currents to chip internal function blocks would allow for some kind of chipinternal IDDQ technique also in digital circuits [Haw 891. But the task of current measurement on chip-internal wires has been ncglected so far. To date, no mechanism has been presented that allows contactless rno:iitoring and measurement of chip-internal currents using an electron beam technique. Neither the measuremenl of the voltage drop caused by the rcsistance of chip-internal wires nor the evaluation of the deflection of the primary beam due to the magnetic field around a current carrying wire (in the range of some pm/A) provides a practical access to chip-internal currents [He1 911. The following paper will describe a promising approach to such a technique, that exploits the interaction between the magnetic field around a current carrying wire and secondary electrons emitted from its surface. 2 PRINCIPLES The basic interaction between a current and a moving electron (e.g. secondary electron) is established by the magnetic field caused by this current. Therefore, the interaction process is described by Ampere's Law and the Lorentz force, aA at p = -e--eeV@+evx(ZZxAJ
介绍了一种新型电子束测试仪的测量成像技术，该技术有望通过测量芯片内部电流的能力，扩大现有电子束测试仪在芯片内部电压测量中的适用性。讨论了该方法的理论原理，并对模型布置的效果进行了解析计算。对于更实际的测量情况，给出了数值计算结果，显示了效应的强度及其对情景参数的依赖性。首先补充了实验结果。在过去的几年里，混合信号设计的市场份额不断增加。这种趋势导致了专用混合信号测试系统的引入。对于纯数字电路的原型调试，电子束酯(ebt)等内部测量工具已被证明是有价值的，目前正在努力增强这些工具，以应用于混合信号电路。本文的主要任务是通过降低系统固有噪声来提高EBT的电压分辨率。因此，模拟电压信号的测量在可接受的信噪比[Gar 871]下可用。然而，模拟电路中的信息通常由电流携带，因此无法用电子束测试仪进行测量。另一方面，测量芯片内部功能块的电源电流的能力将允许在数字电路中使用某种芯片内部IDDQ技术[ha891]。但是，芯片内部导线电流测量的工作一直被忽视。到目前为止，还没有一种机制允许使用电子束技术对芯片内部电流进行非接触监测和测量。无论是对芯片内部导线的电阻引起的电压降的测量，还是对载流导线周围的磁场(在一些pm/ a的范围内)引起的主波束偏转的评估，都不能提供对芯片内部电流的实际访问[He1 911]。下面的论文将描述一种很有前途的方法来实现这种技术，即利用载流导线周围的磁场和从其表面发射的二次电子之间的相互作用。电流和运动电子(如二次电子)之间的基本相互作用是由电流产生的磁场建立的。因此，相互作用过程可以用安培定律和洛伦兹力aA at p = -e—eeV@+evx(ZZxAJ)来描述
{"title":"AN APPROACH TO CHIP-INTERNAL CURRENT MONITORING AND MEASUREMENT USING AN ELECTRON BEAM TESTER","authors":"K. Helmreich, P. Nagel, W. Wolz, K. Müller-Glaser","doi":"10.1109/TEST.1991.519517","DOIUrl":"https://doi.org/10.1109/TEST.1991.519517","url":null,"abstract":"An innovative measurement and imaging technique for electron beam testers is introduced, that promises to expand the present applicability of such systems for chip-internal voltage measurements by the capability of chip-internal current measurement. The theoretical principles of the method are discussed and the effect is calculated analytically for a model arrangement. For more realistic measurement situations, the results of numerical calculations, showing the strength of the effect and its dependency of situational parameters, are presented. First experimental results are added. 1 MOTIVATION During the last years, the market share of mixed-signal designs could be observed to be continously increasing. This tendency led to the introduction of dedicated mixedsignal test systems. For prototype debugging of purely digital circuits, internal measurement tools like electron beam !esters (EBTs) have proved to be valuable and at the moment efforts are undertaken to enhance these tools also for application to mixed-signal circuils. The main task herewith is to improve the voltage resolution of the EBT by reducing system-inherent noise. Thus the measurement of analog voltage signals becomes available at an acceptable signal-to-noise ratio [Gar 871. However, information in analog circuitry is often carried by currents and therefore not accessible for measurement with an electron beam tester. On the other hand, the capability of measuring supply currents to chip internal function blocks would allow for some kind of chipinternal IDDQ technique also in digital circuits [Haw 891. But the task of current measurement on chip-internal wires has been ncglected so far. To date, no mechanism has been presented that allows contactless rno:iitoring and measurement of chip-internal currents using an electron beam technique. Neither the measuremenl of the voltage drop caused by the rcsistance of chip-internal wires nor the evaluation of the deflection of the primary beam due to the magnetic field around a current carrying wire (in the range of some pm/A) provides a practical access to chip-internal currents [He1 911. The following paper will describe a promising approach to such a technique, that exploits the interaction between the magnetic field around a current carrying wire and secondary electrons emitted from its surface. 2 PRINCIPLES The basic interaction between a current and a moving electron (e.g. secondary electron) is established by the magnetic field caused by this current. Therefore, the interaction process is described by Ampere's Law and the Lorentz force, aA at p = -e--eeV@+evx(ZZxAJ","PeriodicalId":272630,"journal":{"name":"1991, Proceedings. International Test Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128976597","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-10-26DOI: 10.1109/TEST.1991.519795
K. Rose
The short answer to the first question is that test engineers had better be seen by their managements as part of the solution rather than part of the problem. The long answer is that the drive to raise quality and lower cost in less time has definite implications for test engineering practice. Kaoru Ishikawa at the University of Tokyo has been a leader in adapting quality improvement techniques to the work place. He has suggested that quality management has evolved from final inspection to manufacturing control to design improvement Final inspection, testing, to determine whether a product should be selected or rejected does not, by itself, improve quality. However, a high reject rate does indicate poor quality and higher cost.
对第一个问题的简短回答是，测试工程师最好被他们的管理层视为解决方案的一部分，而不是问题的一部分。长期的答案是，在更短的时间内提高质量和降低成本的动力对测试工程实践具有明确的含义。东京大学(University of Tokyo)的石川薰(Kaoru Ishikawa)一直是将质量改进技术应用于工作场所的领军人物。他提出，质量管理已经从最终检验发展到制造控制，再到设计改进。最终检验、测试，以确定产品是否应被选择或拒绝，本身并不能提高质量。然而，高废品率确实表明质量差和成本高。
{"title":"Quality in test education?","authors":"K. Rose","doi":"10.1109/TEST.1991.519795","DOIUrl":"https://doi.org/10.1109/TEST.1991.519795","url":null,"abstract":"The short answer to the first question is that test engineers had better be seen by their managements as part of the solution rather than part of the problem. The long answer is that the drive to raise quality and lower cost in less time has definite implications for test engineering practice. Kaoru Ishikawa at the University of Tokyo has been a leader in adapting quality improvement techniques to the work place. He has suggested that quality management has evolved from final inspection to manufacturing control to design improvement Final inspection, testing, to determine whether a product should be selected or rejected does not, by itself, improve quality. However, a high reject rate does indicate poor quality and higher cost.","PeriodicalId":272630,"journal":{"name":"1991, Proceedings. International Test Conference","volume":"132 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128533957","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-10-26DOI: 10.1109/TEST.1991.519736
W. Jone
In this work, sequential statistical analysis has been applied to determine the defect level of random and pseudorandom testing. Results derived using worst case analysis show that the defect level of pseudorandom testing is always no larger than the defect level of random testing. We also find that the defect level of random testing is a good approximation to that of pseudorandom testing, only if either the yield or circuit detectability is high.
{"title":"Defect Level Estimation of Random and Pseudorandom Testing","authors":"W. Jone","doi":"10.1109/TEST.1991.519736","DOIUrl":"https://doi.org/10.1109/TEST.1991.519736","url":null,"abstract":"In this work, sequential statistical analysis has been applied to determine the defect level of random and pseudorandom testing. Results derived using worst case analysis show that the defect level of pseudorandom testing is always no larger than the defect level of random testing. We also find that the defect level of random testing is a good approximation to that of pseudorandom testing, only if either the yield or circuit detectability is high.","PeriodicalId":272630,"journal":{"name":"1991, Proceedings. International Test Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114188886","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-10-26DOI: 10.1109/TEST.1991.519771
Y. Tashiro, H. Yamauchi, T. Minami, T. Tajiri, Yutaka Suzuki
Our newly designed IDSP (Image Digita.1 Signal Processor)[1] requires a high throughput of at. least 300 NIOPS for real-time video signal processing systems (especially, for one-hoard CCITT standard p x 64 kb/s video codec ones) to enable both the parallel processing of plural pixel blocks and development in short TAT (turn-around-time). Moreover, t#he IDSP on the application systems requires soft,ware. IDSP testing, therefore, should be considered firmware testing, involving hardware and software verification. Iinpleinenting firmware test.ing, liowever, is a difficult task due to the necessity of verifying the real-time and parallel processing performance of’ the IDSP. The houiida.ry-scan tecliniciue devised by JTAG (Joint Test Action Group) is one attempt to debug a system wit11 multiprocessors.[’] 111 tliis t,echnique, a test bus controller assigns sciln paths on the system board that connects all processors’ and other devices’ scan paths and inputs and rea.ds serial data into a,nd from the a.ssigned scan path registers. However, scan path test pa,tterns, i.e., serial dat,a, have t.o he generakd for system testing. Generat,program-bus 1 programI sad-bus
我们新设计的IDSP(图像数字1信号处理器)[1]需要高吞吐量at。至少300 NIOPS用于实时视频信号处理系统(特别是对于一组CCITT标准p x 64 kb/s视频编解码器)，以实现多个像素块的并行处理和短TAT(周转时间)的开发。此外，应用系统上的IDSP需要软件。因此，IDSP测试应被视为固件测试，包括硬件和软件验证。实施固件测试。然而，由于需要验证IDSP的实时性和并行处理性能，因此测试是一项艰巨的任务。houiida。JTAG(联合测试行动组)设计的ry-scan技术是调试具有11个多处理器的系统的一种尝试。['] 1 .技术上，测试总线控制器在系统板上分配扫描路径，该路径连接所有处理器和其他设备的扫描路径、输入和接收。将串行数据转换为a，并从assigned扫描路径寄存器中读取。但是，扫描路径测试模式，即串行数据，a，必须用于系统测试。通用，程序总线1程序总线
{"title":"An Organized Firmware Verification Environment for the Programmable Image DSP","authors":"Y. Tashiro, H. Yamauchi, T. Minami, T. Tajiri, Yutaka Suzuki","doi":"10.1109/TEST.1991.519771","DOIUrl":"https://doi.org/10.1109/TEST.1991.519771","url":null,"abstract":"Our newly designed IDSP (Image Digita.1 Signal Processor)[1] requires a high throughput of at. least 300 NIOPS for real-time video signal processing systems (especially, for one-hoard CCITT standard p x 64 kb/s video codec ones) to enable both the parallel processing of plural pixel blocks and development in short TAT (turn-around-time). Moreover, t#he IDSP on the application systems requires soft,ware. IDSP testing, therefore, should be considered firmware testing, involving hardware and software verification. Iinpleinenting firmware test.ing, liowever, is a difficult task due to the necessity of verifying the real-time and parallel processing performance of’ the IDSP. The houiida.ry-scan tecliniciue devised by JTAG (Joint Test Action Group) is one attempt to debug a system wit11 multiprocessors.[’] 111 tliis t,echnique, a test bus controller assigns sciln paths on the system board that connects all processors’ and other devices’ scan paths and inputs and rea.ds serial data into a,nd from the a.ssigned scan path registers. However, scan path test pa,tterns, i.e., serial dat,a, have t.o he generakd for system testing. Generat,program-bus 1 programI sad-bus","PeriodicalId":272630,"journal":{"name":"1991, Proceedings. International Test Conference","volume":"49 9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126122512","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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