Pub Date : 1991-10-26DOI: 10.1109/TEST.1991.519762
P. Ryan, S. Rawat, W. Fuchs
A two-stage procedure for locating VLSI faults is presented. The approach utilizes dynamic fault dictionaries, test set partitioning, and reduced fault lists to achieve a reduction in size and complexity over classic static fault dictionaries. An industrial implementation is reported in which faults were injected and diagnosed in a VLSI chip and the perjiormunce of two-stage fault location was measured.
{"title":"TWO-STAGE FAULT LOCATION","authors":"P. Ryan, S. Rawat, W. Fuchs","doi":"10.1109/TEST.1991.519762","DOIUrl":"https://doi.org/10.1109/TEST.1991.519762","url":null,"abstract":"A two-stage procedure for locating VLSI faults is presented. The approach utilizes dynamic fault dictionaries, test set partitioning, and reduced fault lists to achieve a reduction in size and complexity over classic static fault dictionaries. An industrial implementation is reported in which faults were injected and diagnosed in a VLSI chip and the perjiormunce of two-stage fault location was measured.","PeriodicalId":272630,"journal":{"name":"1991, Proceedings. International Test Conference","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123829195","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-10-26DOI: 10.1109/TEST.1991.519775
M. Kanzaki, M. Ishida
This paper a!escribes the design and use of parallel pattern generaliors in a Memory Test System to achieve high speed testing of memory integrated circuitdr. Both the hardware design and the software design of this subsystem is described. This Test System has been put into practical use and has resulted in the evaluation and testing of very high speed memories in a signi,ficantly shorter time than with conventional systems.
{"title":"PROGRAMMING FOR PARALLEL PATTERN GENERATORS","authors":"M. Kanzaki, M. Ishida","doi":"10.1109/TEST.1991.519775","DOIUrl":"https://doi.org/10.1109/TEST.1991.519775","url":null,"abstract":"This paper a!escribes the design and use of parallel pattern generaliors in a Memory Test System to achieve high speed testing of memory integrated circuitdr. Both the hardware design and the software design of this subsystem is described. This Test System has been put into practical use and has resulted in the evaluation and testing of very high speed memories in a signi,ficantly shorter time than with conventional systems.","PeriodicalId":272630,"journal":{"name":"1991, Proceedings. International Test Conference","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133850067","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-10-26DOI: 10.1109/TEST.1991.519513
E. Bruls, F. Camerik, H. Kretschman, J. Jess
Nowadays, the IC features are still becoming smaller, the areas larger and the packing densities higher. Thus, the occurrence of defects has a growing impact on production yields. Defect monitoring systems are widely used to obtain information about these defects. This paper describes a process-independent method to develop such a defect monitoring system. This implies that rules are given for the design of the monitor, the required resistance measurements, the applied data processing and the data presentation. This method can be applied to design monitors for various applications. For example, the monitor can contain one or more layers and can be process or product-related. An application of the method is also shown.
{"title":"A GENERIC METHOD TO DEVELOP A DEFECT MONITORING SYSTEM FOR IC PROCESSES","authors":"E. Bruls, F. Camerik, H. Kretschman, J. Jess","doi":"10.1109/TEST.1991.519513","DOIUrl":"https://doi.org/10.1109/TEST.1991.519513","url":null,"abstract":"Nowadays, the IC features are still becoming smaller, the areas larger and the packing densities higher. Thus, the occurrence of defects has a growing impact on production yields. Defect monitoring systems are widely used to obtain information about these defects. This paper describes a process-independent method to develop such a defect monitoring system. This implies that rules are given for the design of the monitor, the required resistance measurements, the applied data processing and the data presentation. This method can be applied to design monitors for various applications. For example, the monitor can contain one or more layers and can be process or product-related. An application of the method is also shown.","PeriodicalId":272630,"journal":{"name":"1991, Proceedings. International Test Conference","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134185799","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-10-26DOI: 10.1109/TEST.1991.519777
Michael A. Perugini
The initial development costs of test programs and test hardvvare range from $5,000 to $30,000 or more. As device speeds or production needs increase, the need to test an existing device on a different tester often arises. A solution to minimize this development cost is to recycle the exixting test program, patterns and the device interface boards. This paper describes how the UNIX tools, LEX and YACC, were applied to solve this problem. In this case, Ando DIC 8035 test programs, paeterns and bad boards were used on a Credence Vista Series LT-1101 test system. The program ando2lt (Ando to LT) is the first of the test program crosscompilers using these tools. The flexibility of this approach led to the reuse of over 44% of the ando2lt code in the second cross-compiler sts2It.
测试程序和测试硬件的初始开发成本从5,000美元到30,000美元不等，甚至更多。随着设备速度或生产需求的增加，在不同的测试器上测试现有设备的需求经常出现。最小化开发成本的解决方案是回收现有的测试程序、模式和设备接口板。本文介绍了如何应用UNIX工具LEX和YACC来解决这一问题。在这种情况下，安藤DIC 8035测试程序，模式和坏板被用于Credence Vista系列LT-1101测试系统。程序ando2lt (Ando to LT)是使用这些工具的第一个测试程序交叉编译器。这种方法的灵活性导致在第二个交叉编译器sts2It中重用了超过44%的ando2lt代码。
{"title":"A FLEXIBLE APPROACH TO TEST PROGRAM CROSS COMPILERS","authors":"Michael A. Perugini","doi":"10.1109/TEST.1991.519777","DOIUrl":"https://doi.org/10.1109/TEST.1991.519777","url":null,"abstract":"The initial development costs of test programs and test hardvvare range from $5,000 to $30,000 or more. As device speeds or production needs increase, the need to test an existing device on a different tester often arises. A solution to minimize this development cost is to recycle the exixting test program, patterns and the device interface boards. This paper describes how the UNIX tools, LEX and YACC, were applied to solve this problem. In this case, Ando DIC 8035 test programs, paeterns and bad boards were used on a Credence Vista Series LT-1101 test system. The program ando2lt (Ando to LT) is the first of the test program crosscompilers using these tools. The flexibility of this approach led to the reuse of over 44% of the ando2lt code in the second cross-compiler sts2It.","PeriodicalId":272630,"journal":{"name":"1991, Proceedings. International Test Conference","volume":"9 4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131754041","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-10-26DOI: 10.1109/TEST.1991.519787
C. Stroud
DFT techniques, such as LSSD, emerged as a result of the rapid increase in circuit density and complexity in the LSI circuits of the 1970’s and provided high fault coverage at the device level of testing. BIST emerged circa 1980 with the widespread development of VLSI circuits and provided potentially high fault coverage at all levels of testing, from the device level through system diagnostics. One would think that, with the increased complexity of VLSI devices and circuit boards of the 1990’s, DFT and BIST techniques would be an integral part of current design methodologies. Yet, in some cases, circuit designers continue to be reluctant to incorporate DFT and BIST in their designs. This reluctance has traditionally been attributed to the area and performance penalties associated with DFT and BIST techniques. But, as a VLSI designer, CAD tool developer, and disciple of BIST, I believe that the history of DFT and BIST techniques has been marked by developments, related to VLSI design and testing, which have distracted designers from the incorporation of these techniques. For example, by the end of the 1970s, CAD tools were in place to provide automatic implementation and test pattern generation for LSSD. Area and performance penalties were minimized and could be further reduced by using partial scan design techniques. CAD tools for implementation and support of LSSD were developed to the point that DFT was probably the most automated aspect of system level VLSI design. Then along came BIST. BIST was attractive in that it offered an at-speed testing capability which could be use at all levels of testing since test pattern generation and output response compaction circuitry were an inherent part of the BIST scheme. And BIST provided elegant solutions to testing regular structures, such as memories, which had posed problems to LSSD. Throughout the 1980s, different BIST approaches for regular structures were developed based on the type of structure and BIST approaches for general sequential logic were proposed. But the various BIST techniques were disputed with respect to their effectiveness versus their area overhead, performance penalty, and difficulty of implementation. As a result of the trade-offs associated with the different approaches, the design community became confused to the extent that a certain level of expertise was required to effectively implement BIST in a given VLSI design. Projects with local experts in DFT and BIST were able to make essential plans and decisions while projects without this expertise suffered to the point of failing to implement any DFT. By the mid1980s, CAD tools for the automation of B E T in regular structures were developed but the lack of a generally accepted approach for sequential logic hindered the development of tools that would automate the various BIST implementations required for a complete VLSI design. Then along came high-level synthesis. High-level synthesis provided implementation of the gate or tr
{"title":"DISTRACTIONS IN DESIGN FOR TESTABILITY AND BUILT-IN SELF-TEST","authors":"C. Stroud","doi":"10.1109/TEST.1991.519787","DOIUrl":"https://doi.org/10.1109/TEST.1991.519787","url":null,"abstract":"DFT techniques, such as LSSD, emerged as a result of the rapid increase in circuit density and complexity in the LSI circuits of the 1970’s and provided high fault coverage at the device level of testing. BIST emerged circa 1980 with the widespread development of VLSI circuits and provided potentially high fault coverage at all levels of testing, from the device level through system diagnostics. One would think that, with the increased complexity of VLSI devices and circuit boards of the 1990’s, DFT and BIST techniques would be an integral part of current design methodologies. Yet, in some cases, circuit designers continue to be reluctant to incorporate DFT and BIST in their designs. This reluctance has traditionally been attributed to the area and performance penalties associated with DFT and BIST techniques. But, as a VLSI designer, CAD tool developer, and disciple of BIST, I believe that the history of DFT and BIST techniques has been marked by developments, related to VLSI design and testing, which have distracted designers from the incorporation of these techniques. For example, by the end of the 1970s, CAD tools were in place to provide automatic implementation and test pattern generation for LSSD. Area and performance penalties were minimized and could be further reduced by using partial scan design techniques. CAD tools for implementation and support of LSSD were developed to the point that DFT was probably the most automated aspect of system level VLSI design. Then along came BIST. BIST was attractive in that it offered an at-speed testing capability which could be use at all levels of testing since test pattern generation and output response compaction circuitry were an inherent part of the BIST scheme. And BIST provided elegant solutions to testing regular structures, such as memories, which had posed problems to LSSD. Throughout the 1980s, different BIST approaches for regular structures were developed based on the type of structure and BIST approaches for general sequential logic were proposed. But the various BIST techniques were disputed with respect to their effectiveness versus their area overhead, performance penalty, and difficulty of implementation. As a result of the trade-offs associated with the different approaches, the design community became confused to the extent that a certain level of expertise was required to effectively implement BIST in a given VLSI design. Projects with local experts in DFT and BIST were able to make essential plans and decisions while projects without this expertise suffered to the point of failing to implement any DFT. By the mid1980s, CAD tools for the automation of B E T in regular structures were developed but the lack of a generally accepted approach for sequential logic hindered the development of tools that would automate the various BIST implementations required for a complete VLSI design. Then along came high-level synthesis. High-level synthesis provided implementation of the gate or tr","PeriodicalId":272630,"journal":{"name":"1991, Proceedings. International Test Conference","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125279543","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-10-26DOI: 10.1109/TEST.1991.519773
D. Rosenthal
A 20 bit waveform source capable of producing waveforms for both ac anid dc testing of up to 18 bit analog to digital converters is described. Noise shaping technoliogy is ernployed in this design.
{"title":"A 20 BIT WAVEFORM SOURCE FOR A MIXED-SIGNAL AUTOMATIC TEST SYSTEM","authors":"D. Rosenthal","doi":"10.1109/TEST.1991.519773","DOIUrl":"https://doi.org/10.1109/TEST.1991.519773","url":null,"abstract":"A 20 bit waveform source capable of producing waveforms for both ac anid dc testing of up to 18 bit analog to digital converters is described. Noise shaping technoliogy is ernployed in this design.","PeriodicalId":272630,"journal":{"name":"1991, Proceedings. International Test Conference","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123601406","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-10-26DOI: 10.1109/TEST.1991.519746
D. Lambidonis, A. Ivanov, V. Agarwal
Compaction simulation time is a costly (CPU) process when performing fault simulation of BIST circuits. In this paper, we present a compaction simulation algorithm for linear compactors. Basic look-up operations are used to reduce compaction time significantly and memory requirements for the tables are small. With this algorithm, the compaction of an M-bit sequence by a k-bit linear compactor requires M + s2 7 k-bit words of memory where s, 1 and m can be any value such that T and f are integers, and where pAerr is the proportion of errors in the signature and pRSrr the proportion of errors in the CUT’S response. Both pRSTr and pAeTr range between [0,1]. However, for a large proportion of faults in a CUT, the detection probabilities are low, making pAS7? and pR,?? low as well. Simulation results demonstrating the speed of the compaction algorithm are given. + s pR.,, ) + operations and 12 x(‘ P A s r t
在对BIST电路进行故障仿真时，压缩仿真时间是一个昂贵的(CPU)过程。本文提出了一种线性压实机的压实仿真算法。使用基本的查找操作可以显著减少压缩时间，并且表的内存需求很小。使用该算法，k位线性压缩器压缩M位序列需要M + s2 7个k位的内存字，其中s, 1和M可以是任意值，使得T和f是整数，其中pAerr是签名中的错误比例，pRSrr是CUT响应中的错误比例。pRSTr和pAeTr的取值范围为[0,1]。然而，对于一个CUT中很大比例的故障，检测概率很低，使得pAS7?和公关,? ?也很低。仿真结果表明了压缩算法的速度。+ s pR.，，) +运算和12x (' pa ' s r t
{"title":"FAST SIGNATURE COMPUTATION FOR LINEAR COMPACTORS","authors":"D. Lambidonis, A. Ivanov, V. Agarwal","doi":"10.1109/TEST.1991.519746","DOIUrl":"https://doi.org/10.1109/TEST.1991.519746","url":null,"abstract":"Compaction simulation time is a costly (CPU) process when performing fault simulation of BIST circuits. In this paper, we present a compaction simulation algorithm for linear compactors. Basic look-up operations are used to reduce compaction time significantly and memory requirements for the tables are small. With this algorithm, the compaction of an M-bit sequence by a k-bit linear compactor requires M + s2 7 k-bit words of memory where s, 1 and m can be any value such that T and f are integers, and where pAerr is the proportion of errors in the signature and pRSrr the proportion of errors in the CUT’S response. Both pRSTr and pAeTr range between [0,1]. However, for a large proportion of faults in a CUT, the detection probabilities are low, making pAS7? and pR,?? low as well. Simulation results demonstrating the speed of the compaction algorithm are given. + s pR.,, ) + operations and 12 x(‘ P A s r t","PeriodicalId":272630,"journal":{"name":"1991, Proceedings. International Test Conference","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130861683","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-10-26DOI: 10.1109/TEST.1991.519730
Charles W. Buenzli, Robert Gonzalez
Comparison of current design and functional test practices for digital circuits versus analog circuits reveals a significant lag in the availability and sophistication of analog design tools, DFT techniques, design-to-test links, and diagnostic aides. Though hardware advances such as VXI and software advances such as the Standard Commands for Programmable Instruments (SCPI) reduce the time and expense of developing analog gobo go functional test programs, there has not been a similar advance in analog diagnostics. As a result, most electronic manufacturers and depots rely on skilled technicians to manually troubleshoot functional test failures. The scarcity and cost of skilled technicians and the increasing mix and complexity of analog (and mixed signal) circuits point to a strong need for automated analog diagnostics.
{"title":"A CASE STUDY OF MIXED SIGNAL FAULT ISOLATION: KNOWLEDGE BASED VS. DECISION TREE PROGRAMMING","authors":"Charles W. Buenzli, Robert Gonzalez","doi":"10.1109/TEST.1991.519730","DOIUrl":"https://doi.org/10.1109/TEST.1991.519730","url":null,"abstract":"Comparison of current design and functional test practices for digital circuits versus analog circuits reveals a significant lag in the availability and sophistication of analog design tools, DFT techniques, design-to-test links, and diagnostic aides. Though hardware advances such as VXI and software advances such as the Standard Commands for Programmable Instruments (SCPI) reduce the time and expense of developing analog gobo go functional test programs, there has not been a similar advance in analog diagnostics. As a result, most electronic manufacturers and depots rely on skilled technicians to manually troubleshoot functional test failures. The scarcity and cost of skilled technicians and the increasing mix and complexity of analog (and mixed signal) circuits point to a strong need for automated analog diagnostics.","PeriodicalId":272630,"journal":{"name":"1991, Proceedings. International Test Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130466585","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-10-26DOI: 10.1109/TEST.1991.519523
T. Storey, W. Maly, J. Andrews, M. Miske
This paper compares the effectiveness of Stuck Fault and Current Testing, as applied to CMOS ICs. The comparison is performed by testing sequential CMOS chips using patterns developed via both methodis, and evaluating their ability to identify faulty prciduct. The test results are then contrasted to a previous study in which a smaller, combinatorial chip was tested by the same means. The results indicate that, for the investigated set of chips, Current Testing provides a better screen of defective product for some classes of defects, while Stuck Fault Testing is more effective on others.
{"title":"STUCK FAULT AND CURRENT TESTING COMPARISON USING CMOS CHIP TEST","authors":"T. Storey, W. Maly, J. Andrews, M. Miske","doi":"10.1109/TEST.1991.519523","DOIUrl":"https://doi.org/10.1109/TEST.1991.519523","url":null,"abstract":"This paper compares the effectiveness of Stuck Fault and Current Testing, as applied to CMOS ICs. The comparison is performed by testing sequential CMOS chips using patterns developed via both methodis, and evaluating their ability to identify faulty prciduct. The test results are then contrasted to a previous study in which a smaller, combinatorial chip was tested by the same means. The results indicate that, for the investigated set of chips, Current Testing provides a better screen of defective product for some classes of defects, while Stuck Fault Testing is more effective on others.","PeriodicalId":272630,"journal":{"name":"1991, Proceedings. International Test Conference","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128295205","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-10-26DOI: 10.1109/TEST.1991.519719
A. Meixner, Wojciech Maly
The goal of the research described in this paper is to introduce a fault-modeling technique for simulating defective analog components in Mixed Analog/Digital Integrated Circuits. The proposed fault- modeling strategy has been implemented to develop analog fault models representing the effect of spot defects in CMOS circuits. Results from an initial study of opamps are summarized and detailed results from onc example are included as an illustration of the fault- modeling process. 1 Introduction Application of analog components within large digital systems - a typical configuration in modern mixed analog/digital IC's - generates many new challenges in both design and testing areas (l), (2), (3), (4). EspccialIy difficult to solve are testing problems due to the observability limitations caused by the nature of the boundary between the digital and analog components of mixed IC's. Although there are many mixcd IC testing problems, this paper focuses on only one of them - a strategy of fault simulation. More specifically, this paper introduces a fault- modeling methodology which could be applied to capture the malfunctioning of analog components in mixed IC's. The goal of the reported research is to develop fault models that enable efficient simulation of the entire mixed IC by using a technique that is as close as possible to traditional digital circuit simulation techniques. Hence, this paper concentrates solely on the fault- modeling technique. It is organized in the following way. In Section 2, the general fault-modeling methodology developed for analog components of mixed IC's is introduced. In Section 3, an implementation of this methodology for CMOS technology is described in morc detail. Finally, in Section 4, an attempt to generalize obtained results is made in order to determine the practicality of the proposed fault-modeling methodology. This section also gives a list of problems to be solved in the subsequent research dealing with testing of mixcd analog/digital integrated circuits.
{"title":"FAULT MODELING FOR THE TESTING OF MIXED INTEGRATED CIRCUITS","authors":"A. Meixner, Wojciech Maly","doi":"10.1109/TEST.1991.519719","DOIUrl":"https://doi.org/10.1109/TEST.1991.519719","url":null,"abstract":"The goal of the research described in this paper is to introduce a fault-modeling technique for simulating defective analog components in Mixed Analog/Digital Integrated Circuits. The proposed fault- modeling strategy has been implemented to develop analog fault models representing the effect of spot defects in CMOS circuits. Results from an initial study of opamps are summarized and detailed results from onc example are included as an illustration of the fault- modeling process. 1 Introduction Application of analog components within large digital systems - a typical configuration in modern mixed analog/digital IC's - generates many new challenges in both design and testing areas (l), (2), (3), (4). EspccialIy difficult to solve are testing problems due to the observability limitations caused by the nature of the boundary between the digital and analog components of mixed IC's. Although there are many mixcd IC testing problems, this paper focuses on only one of them - a strategy of fault simulation. More specifically, this paper introduces a fault- modeling methodology which could be applied to capture the malfunctioning of analog components in mixed IC's. The goal of the reported research is to develop fault models that enable efficient simulation of the entire mixed IC by using a technique that is as close as possible to traditional digital circuit simulation techniques. Hence, this paper concentrates solely on the fault- modeling technique. It is organized in the following way. In Section 2, the general fault-modeling methodology developed for analog components of mixed IC's is introduced. In Section 3, an implementation of this methodology for CMOS technology is described in morc detail. Finally, in Section 4, an attempt to generalize obtained results is made in order to determine the practicality of the proposed fault-modeling methodology. This section also gives a list of problems to be solved in the subsequent research dealing with testing of mixcd analog/digital integrated circuits.","PeriodicalId":272630,"journal":{"name":"1991, Proceedings. International Test Conference","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128329264","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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