Pub Date : 1991-10-26DOI: 10.1109/TEST.1991.519762
P. Ryan, S. Rawat, W. Fuchs
A two-stage procedure for locating VLSI faults is presented. The approach utilizes dynamic fault dictionaries, test set partitioning, and reduced fault lists to achieve a reduction in size and complexity over classic static fault dictionaries. An industrial implementation is reported in which faults were injected and diagnosed in a VLSI chip and the perjiormunce of two-stage fault location was measured.
{"title":"TWO-STAGE FAULT LOCATION","authors":"P. Ryan, S. Rawat, W. Fuchs","doi":"10.1109/TEST.1991.519762","DOIUrl":"https://doi.org/10.1109/TEST.1991.519762","url":null,"abstract":"A two-stage procedure for locating VLSI faults is presented. The approach utilizes dynamic fault dictionaries, test set partitioning, and reduced fault lists to achieve a reduction in size and complexity over classic static fault dictionaries. An industrial implementation is reported in which faults were injected and diagnosed in a VLSI chip and the perjiormunce of two-stage fault location was measured.","PeriodicalId":272630,"journal":{"name":"1991, Proceedings. International Test Conference","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123829195","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-10-26DOI: 10.1109/TEST.1991.519775
M. Kanzaki, M. Ishida
This paper a!escribes the design and use of parallel pattern generaliors in a Memory Test System to achieve high speed testing of memory integrated circuitdr. Both the hardware design and the software design of this subsystem is described. This Test System has been put into practical use and has resulted in the evaluation and testing of very high speed memories in a signi,ficantly shorter time than with conventional systems.
{"title":"PROGRAMMING FOR PARALLEL PATTERN GENERATORS","authors":"M. Kanzaki, M. Ishida","doi":"10.1109/TEST.1991.519775","DOIUrl":"https://doi.org/10.1109/TEST.1991.519775","url":null,"abstract":"This paper a!escribes the design and use of parallel pattern generaliors in a Memory Test System to achieve high speed testing of memory integrated circuitdr. Both the hardware design and the software design of this subsystem is described. This Test System has been put into practical use and has resulted in the evaluation and testing of very high speed memories in a signi,ficantly shorter time than with conventional systems.","PeriodicalId":272630,"journal":{"name":"1991, Proceedings. International Test Conference","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133850067","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-10-26DOI: 10.1109/TEST.1991.519744
D. Keezer
A system hus been described [I -61 for testing digital ECL or GaAs devices at rates above 1 Gbps. This system utilizes GaAs multiplexers for combining data ffom several (4 or 8) tester channels to form high speed data sources which are then used as DUT stimuli. Until recently, one of the main limitations of this approach has been the lack of comparable performance &multiplexers or, alternatively real time comparator electronics. In place of these, multi-pass testing can be used if the test system comparators have a high enough bandwrdth [7]. In ths paper, recent enhancements to the data generation electronics of the UHF test system are first reviewed. Next, designs are presented for high speed comparison circuits. These perform real-time comparison of DUT output patterns with expected data at rates above 500 Mbps.
{"title":"REAL-TIME DATA COMPARISON FOR GIGAHERTZ DIGITAL TEST","authors":"D. Keezer","doi":"10.1109/TEST.1991.519744","DOIUrl":"https://doi.org/10.1109/TEST.1991.519744","url":null,"abstract":"A system hus been described [I -61 for testing digital ECL or GaAs devices at rates above 1 Gbps. This system utilizes GaAs multiplexers for combining data ffom several (4 or 8) tester channels to form high speed data sources which are then used as DUT stimuli. Until recently, one of the main limitations of this approach has been the lack of comparable performance &multiplexers or, alternatively real time comparator electronics. In place of these, multi-pass testing can be used if the test system comparators have a high enough bandwrdth [7]. In ths paper, recent enhancements to the data generation electronics of the UHF test system are first reviewed. Next, designs are presented for high speed comparison circuits. These perform real-time comparison of DUT output patterns with expected data at rates above 500 Mbps.","PeriodicalId":272630,"journal":{"name":"1991, Proceedings. International Test Conference","volume":"234 ","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113984002","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-10-26DOI: 10.1109/TEST.1991.519773
D. Rosenthal
A 20 bit waveform source capable of producing waveforms for both ac anid dc testing of up to 18 bit analog to digital converters is described. Noise shaping technoliogy is ernployed in this design.
{"title":"A 20 BIT WAVEFORM SOURCE FOR A MIXED-SIGNAL AUTOMATIC TEST SYSTEM","authors":"D. Rosenthal","doi":"10.1109/TEST.1991.519773","DOIUrl":"https://doi.org/10.1109/TEST.1991.519773","url":null,"abstract":"A 20 bit waveform source capable of producing waveforms for both ac anid dc testing of up to 18 bit analog to digital converters is described. Noise shaping technoliogy is ernployed in this design.","PeriodicalId":272630,"journal":{"name":"1991, Proceedings. International Test Conference","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123601406","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-10-26DOI: 10.1109/TEST.1991.519787
C. Stroud
DFT techniques, such as LSSD, emerged as a result of the rapid increase in circuit density and complexity in the LSI circuits of the 1970’s and provided high fault coverage at the device level of testing. BIST emerged circa 1980 with the widespread development of VLSI circuits and provided potentially high fault coverage at all levels of testing, from the device level through system diagnostics. One would think that, with the increased complexity of VLSI devices and circuit boards of the 1990’s, DFT and BIST techniques would be an integral part of current design methodologies. Yet, in some cases, circuit designers continue to be reluctant to incorporate DFT and BIST in their designs. This reluctance has traditionally been attributed to the area and performance penalties associated with DFT and BIST techniques. But, as a VLSI designer, CAD tool developer, and disciple of BIST, I believe that the history of DFT and BIST techniques has been marked by developments, related to VLSI design and testing, which have distracted designers from the incorporation of these techniques. For example, by the end of the 1970s, CAD tools were in place to provide automatic implementation and test pattern generation for LSSD. Area and performance penalties were minimized and could be further reduced by using partial scan design techniques. CAD tools for implementation and support of LSSD were developed to the point that DFT was probably the most automated aspect of system level VLSI design. Then along came BIST. BIST was attractive in that it offered an at-speed testing capability which could be use at all levels of testing since test pattern generation and output response compaction circuitry were an inherent part of the BIST scheme. And BIST provided elegant solutions to testing regular structures, such as memories, which had posed problems to LSSD. Throughout the 1980s, different BIST approaches for regular structures were developed based on the type of structure and BIST approaches for general sequential logic were proposed. But the various BIST techniques were disputed with respect to their effectiveness versus their area overhead, performance penalty, and difficulty of implementation. As a result of the trade-offs associated with the different approaches, the design community became confused to the extent that a certain level of expertise was required to effectively implement BIST in a given VLSI design. Projects with local experts in DFT and BIST were able to make essential plans and decisions while projects without this expertise suffered to the point of failing to implement any DFT. By the mid1980s, CAD tools for the automation of B E T in regular structures were developed but the lack of a generally accepted approach for sequential logic hindered the development of tools that would automate the various BIST implementations required for a complete VLSI design. Then along came high-level synthesis. High-level synthesis provided implementation of the gate or tr
{"title":"DISTRACTIONS IN DESIGN FOR TESTABILITY AND BUILT-IN SELF-TEST","authors":"C. Stroud","doi":"10.1109/TEST.1991.519787","DOIUrl":"https://doi.org/10.1109/TEST.1991.519787","url":null,"abstract":"DFT techniques, such as LSSD, emerged as a result of the rapid increase in circuit density and complexity in the LSI circuits of the 1970’s and provided high fault coverage at the device level of testing. BIST emerged circa 1980 with the widespread development of VLSI circuits and provided potentially high fault coverage at all levels of testing, from the device level through system diagnostics. One would think that, with the increased complexity of VLSI devices and circuit boards of the 1990’s, DFT and BIST techniques would be an integral part of current design methodologies. Yet, in some cases, circuit designers continue to be reluctant to incorporate DFT and BIST in their designs. This reluctance has traditionally been attributed to the area and performance penalties associated with DFT and BIST techniques. But, as a VLSI designer, CAD tool developer, and disciple of BIST, I believe that the history of DFT and BIST techniques has been marked by developments, related to VLSI design and testing, which have distracted designers from the incorporation of these techniques. For example, by the end of the 1970s, CAD tools were in place to provide automatic implementation and test pattern generation for LSSD. Area and performance penalties were minimized and could be further reduced by using partial scan design techniques. CAD tools for implementation and support of LSSD were developed to the point that DFT was probably the most automated aspect of system level VLSI design. Then along came BIST. BIST was attractive in that it offered an at-speed testing capability which could be use at all levels of testing since test pattern generation and output response compaction circuitry were an inherent part of the BIST scheme. And BIST provided elegant solutions to testing regular structures, such as memories, which had posed problems to LSSD. Throughout the 1980s, different BIST approaches for regular structures were developed based on the type of structure and BIST approaches for general sequential logic were proposed. But the various BIST techniques were disputed with respect to their effectiveness versus their area overhead, performance penalty, and difficulty of implementation. As a result of the trade-offs associated with the different approaches, the design community became confused to the extent that a certain level of expertise was required to effectively implement BIST in a given VLSI design. Projects with local experts in DFT and BIST were able to make essential plans and decisions while projects without this expertise suffered to the point of failing to implement any DFT. By the mid1980s, CAD tools for the automation of B E T in regular structures were developed but the lack of a generally accepted approach for sequential logic hindered the development of tools that would automate the various BIST implementations required for a complete VLSI design. Then along came high-level synthesis. High-level synthesis provided implementation of the gate or tr","PeriodicalId":272630,"journal":{"name":"1991, Proceedings. International Test Conference","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125279543","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-10-26DOI: 10.1109/TEST.1991.519731
S. Mohan, P. Mazumder
Gallium Arsenide memories, which are now beginning to be used commercially, are subject to certain unusual parametric faults, not normally seen in silicon or other memory devices. This paper analyzes the causes of these parametric faults by first mapping the observed errors in the fabrication process to circuit behavior; these modified circuits are then shown to cause new types of pattern-sensitive faults and data retention problems. It is shown that by slightly modifying and reordering existing test procedures, all faults in these RAM’s can be adequately tesled.
{"title":"FAULT MODELING AND TESTING OF GaAs STATIC RANDOM ACCESS MEMORIES","authors":"S. Mohan, P. Mazumder","doi":"10.1109/TEST.1991.519731","DOIUrl":"https://doi.org/10.1109/TEST.1991.519731","url":null,"abstract":"Gallium Arsenide memories, which are now beginning to be used commercially, are subject to certain unusual parametric faults, not normally seen in silicon or other memory devices. This paper analyzes the causes of these parametric faults by first mapping the observed errors in the fabrication process to circuit behavior; these modified circuits are then shown to cause new types of pattern-sensitive faults and data retention problems. It is shown that by slightly modifying and reordering existing test procedures, all faults in these RAM’s can be adequately tesled.","PeriodicalId":272630,"journal":{"name":"1991, Proceedings. International Test Conference","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129537621","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-10-26DOI: 10.1109/TEST.1991.519523
T. Storey, W. Maly, J. Andrews, M. Miske
This paper compares the effectiveness of Stuck Fault and Current Testing, as applied to CMOS ICs. The comparison is performed by testing sequential CMOS chips using patterns developed via both methodis, and evaluating their ability to identify faulty prciduct. The test results are then contrasted to a previous study in which a smaller, combinatorial chip was tested by the same means. The results indicate that, for the investigated set of chips, Current Testing provides a better screen of defective product for some classes of defects, while Stuck Fault Testing is more effective on others.
{"title":"STUCK FAULT AND CURRENT TESTING COMPARISON USING CMOS CHIP TEST","authors":"T. Storey, W. Maly, J. Andrews, M. Miske","doi":"10.1109/TEST.1991.519523","DOIUrl":"https://doi.org/10.1109/TEST.1991.519523","url":null,"abstract":"This paper compares the effectiveness of Stuck Fault and Current Testing, as applied to CMOS ICs. The comparison is performed by testing sequential CMOS chips using patterns developed via both methodis, and evaluating their ability to identify faulty prciduct. The test results are then contrasted to a previous study in which a smaller, combinatorial chip was tested by the same means. The results indicate that, for the investigated set of chips, Current Testing provides a better screen of defective product for some classes of defects, while Stuck Fault Testing is more effective on others.","PeriodicalId":272630,"journal":{"name":"1991, Proceedings. International Test Conference","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128295205","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-10-26DOI: 10.1109/TEST.1991.519746
D. Lambidonis, A. Ivanov, V. Agarwal
Compaction simulation time is a costly (CPU) process when performing fault simulation of BIST circuits. In this paper, we present a compaction simulation algorithm for linear compactors. Basic look-up operations are used to reduce compaction time significantly and memory requirements for the tables are small. With this algorithm, the compaction of an M-bit sequence by a k-bit linear compactor requires M + s2 7 k-bit words of memory where s, 1 and m can be any value such that T and f are integers, and where pAerr is the proportion of errors in the signature and pRSrr the proportion of errors in the CUT’S response. Both pRSTr and pAeTr range between [0,1]. However, for a large proportion of faults in a CUT, the detection probabilities are low, making pAS7? and pR,?? low as well. Simulation results demonstrating the speed of the compaction algorithm are given. + s pR.,, ) + operations and 12 x(‘ P A s r t
在对BIST电路进行故障仿真时，压缩仿真时间是一个昂贵的(CPU)过程。本文提出了一种线性压实机的压实仿真算法。使用基本的查找操作可以显著减少压缩时间，并且表的内存需求很小。使用该算法，k位线性压缩器压缩M位序列需要M + s2 7个k位的内存字，其中s, 1和M可以是任意值，使得T和f是整数，其中pAerr是签名中的错误比例，pRSrr是CUT响应中的错误比例。pRSTr和pAeTr的取值范围为[0,1]。然而，对于一个CUT中很大比例的故障，检测概率很低，使得pAS7?和公关,? ?也很低。仿真结果表明了压缩算法的速度。+ s pR.，，) +运算和12x (' pa ' s r t
{"title":"FAST SIGNATURE COMPUTATION FOR LINEAR COMPACTORS","authors":"D. Lambidonis, A. Ivanov, V. Agarwal","doi":"10.1109/TEST.1991.519746","DOIUrl":"https://doi.org/10.1109/TEST.1991.519746","url":null,"abstract":"Compaction simulation time is a costly (CPU) process when performing fault simulation of BIST circuits. In this paper, we present a compaction simulation algorithm for linear compactors. Basic look-up operations are used to reduce compaction time significantly and memory requirements for the tables are small. With this algorithm, the compaction of an M-bit sequence by a k-bit linear compactor requires M + s2 7 k-bit words of memory where s, 1 and m can be any value such that T and f are integers, and where pAerr is the proportion of errors in the signature and pRSrr the proportion of errors in the CUT’S response. Both pRSTr and pAeTr range between [0,1]. However, for a large proportion of faults in a CUT, the detection probabilities are low, making pAS7? and pR,?? low as well. Simulation results demonstrating the speed of the compaction algorithm are given. + s pR.,, ) + operations and 12 x(‘ P A s r t","PeriodicalId":272630,"journal":{"name":"1991, Proceedings. International Test Conference","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130861683","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-10-26DOI: 10.1109/TEST.1991.519504
J. Karlsson, U. Gunneflo, P. Lidén, J. Torin
Two fault injection techniques for experimental validation of fault handling mechanisms in computer systems are investigated and compared. One technique is based on irradiation of ICs with heavy-ion radiation from a 252Cf source. The other technique uses voltage sags injected in the power supply rails to ICs. Both techniques have been used for fault injection experiments with the MC6809E microprocessor. Most errors generated by the 252Cf method were seen first in the address bus, while the power supply disturbances most frequently affected the control signals. An error classification shows that both methods generate many control flow errors, while pure data errors are infrequent. Results from a simulation experiment show that that the low number data errors in the 252Cf experiments can be explained by the fact that many errors in data registers are overwritten owing to the normal program execution.
{"title":"TWO FAULT INJECTION TECHNIQUES FOR TEST OF FAULT HANDLING MECHANISMS","authors":"J. Karlsson, U. Gunneflo, P. Lidén, J. Torin","doi":"10.1109/TEST.1991.519504","DOIUrl":"https://doi.org/10.1109/TEST.1991.519504","url":null,"abstract":"Two fault injection techniques for experimental validation of fault handling mechanisms in computer systems are investigated and compared. One technique is based on irradiation of ICs with heavy-ion radiation from a 252Cf source. The other technique uses voltage sags injected in the power supply rails to ICs. Both techniques have been used for fault injection experiments with the MC6809E microprocessor. Most errors generated by the 252Cf method were seen first in the address bus, while the power supply disturbances most frequently affected the control signals. An error classification shows that both methods generate many control flow errors, while pure data errors are infrequent. Results from a simulation experiment show that that the low number data errors in the 252Cf experiments can be explained by the fact that many errors in data registers are overwritten owing to the normal program execution.","PeriodicalId":272630,"journal":{"name":"1991, Proceedings. International Test Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131305017","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-10-26DOI: 10.1109/TEST.1991.519900
M. Katoozi, Arnold Nordsiek
A method for the design of built-in testable (BIT) error detection and correction (EDAC) circuits is presented reducing test hardware by >50%. A lp CMOS, 16-bit EDAC designed and fabricated with this technique exhibits >99% fault coverage in 10 p at 25 MHz. Built-in test impacts the speed performance by only one gate delay regardless of the size of the EDAC. Various faults are injected into the chip to verifr the effectiveness of built-in test.
{"title":"Low overhead built-in testable error detection and correction with excellent fault coverage","authors":"M. Katoozi, Arnold Nordsiek","doi":"10.1109/TEST.1991.519900","DOIUrl":"https://doi.org/10.1109/TEST.1991.519900","url":null,"abstract":"A method for the design of built-in testable (BIT) error detection and correction (EDAC) circuits is presented reducing test hardware by >50%. A lp CMOS, 16-bit EDAC designed and fabricated with this technique exhibits >99% fault coverage in 10 p at 25 MHz. Built-in test impacts the speed performance by only one gate delay regardless of the size of the EDAC. Various faults are injected into the chip to verifr the effectiveness of built-in test.","PeriodicalId":272630,"journal":{"name":"1991, Proceedings. International Test Conference","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125971246","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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