Pub Date : 1991-10-26DOI: 10.1109/TEST.1991.519714
Stephen M. Lorusso, P. N. Bompastore, M.T. Fertsch
This paper presents our findings on inserting the CrossCheckl test technology into Raytheon's CMOS, sub-micron, sea-of-gates COMPTest gate-array product family. Crosscheck's proprietary technology coupied with our integrated CAD software environment provided extremely high test coverage accommodating complex fault models. Our evaluation of scan versus Crosscheck demonstrated that Crosscheck is a superior testmethodology. Fewer constraints were imposed on the design, a substantial reduction in tester vectors resulted, and high stuck-at NO fault coverage (>99%) was attained with relative ease. Introduction Integrated circuit complexities have risen at an exponential rate over the past decade. System requirements such as tight area constraints and substantial inter-chip signal propagation delays necessitate that more functionality be resident on a single integrated circuit. Large designs which were once 2-5 thousand gates in size are now over 100 thousand gates in size. Some projections indicate the number of gates per chip will approach 2 million by 1995. The performance requirements of integrated circuits have also been rapidly accelerating. ASIC designers today are presented with challenging projects which require the development of high speed (>50 MHz), high density ASICs in an ever shrinking design cycle window. The testability of these large, high performance circuits has become an increasing industry concern. The cost of testing these devices has become a major obstacle to their widespread use. Several surveys have been conducted to assess these cost factors. [l-41 Figure 1 illustrates a defect curve for integrated circuits. The defect level is defined as the percentage of devices which pass testing but actually contain physical defects. Crosscheck is a trademark of Crosscheck Technology, Inc. This parameter is a function of fault coverage and yield. As the graph shows, to keep the defect percentage below 0.1 percent it is necessary to achieve fault coverages in excess of 99%. With simple ad hoc fault detection techniques this has proven to be an extremely difficult achievement. As a result, structured design techniques, such as scan, have emerged in an attempt to facilitate the generation of tests which produce high fault coverage.
{"title":"INTEGRATING CROSSCHECK TECHNOLOGY INTO THE RAYTHEON TEST ENVIRONMENT","authors":"Stephen M. Lorusso, P. N. Bompastore, M.T. Fertsch","doi":"10.1109/TEST.1991.519714","DOIUrl":"https://doi.org/10.1109/TEST.1991.519714","url":null,"abstract":"This paper presents our findings on inserting the CrossCheckl test technology into Raytheon's CMOS, sub-micron, sea-of-gates COMPTest gate-array product family. Crosscheck's proprietary technology coupied with our integrated CAD software environment provided extremely high test coverage accommodating complex fault models. Our evaluation of scan versus Crosscheck demonstrated that Crosscheck is a superior testmethodology. Fewer constraints were imposed on the design, a substantial reduction in tester vectors resulted, and high stuck-at NO fault coverage (>99%) was attained with relative ease. Introduction Integrated circuit complexities have risen at an exponential rate over the past decade. System requirements such as tight area constraints and substantial inter-chip signal propagation delays necessitate that more functionality be resident on a single integrated circuit. Large designs which were once 2-5 thousand gates in size are now over 100 thousand gates in size. Some projections indicate the number of gates per chip will approach 2 million by 1995. The performance requirements of integrated circuits have also been rapidly accelerating. ASIC designers today are presented with challenging projects which require the development of high speed (>50 MHz), high density ASICs in an ever shrinking design cycle window. The testability of these large, high performance circuits has become an increasing industry concern. The cost of testing these devices has become a major obstacle to their widespread use. Several surveys have been conducted to assess these cost factors. [l-41 Figure 1 illustrates a defect curve for integrated circuits. The defect level is defined as the percentage of devices which pass testing but actually contain physical defects. Crosscheck is a trademark of Crosscheck Technology, Inc. This parameter is a function of fault coverage and yield. As the graph shows, to keep the defect percentage below 0.1 percent it is necessary to achieve fault coverages in excess of 99%. With simple ad hoc fault detection techniques this has proven to be an extremely difficult achievement. As a result, structured design techniques, such as scan, have emerged in an attempt to facilitate the generation of tests which produce high fault coverage.","PeriodicalId":272630,"journal":{"name":"1991, Proceedings. International Test Conference","volume":"177 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115905879","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-10-26DOI: 10.1109/TEST.1991.519496
Toshinobu Ono, Masaaki Yoshida
This paper presents a novel deterministic test pattern generation method for sequential circuits. The proposed method has several advantages over conventional methods, particularly in its maximum utilization of internal states. Such utilization permits shorter computational time, reduced test pattern length and fewer timing problems. In this method, the type of fault targeted for the next pattern generation is that which, on the basis of the current internal state of the circuit, is determined to be the easiest type to detect, and during pattern generation, the only value transitions traced are those which are necessary for a particular fault's detection. Experimental results show the proposed method to be efficient.
{"title":"A test generation method for sequential circuits based on maximum utilization of internal states","authors":"Toshinobu Ono, Masaaki Yoshida","doi":"10.1109/TEST.1991.519496","DOIUrl":"https://doi.org/10.1109/TEST.1991.519496","url":null,"abstract":"This paper presents a novel deterministic test pattern generation method for sequential circuits. The proposed method has several advantages over conventional methods, particularly in its maximum utilization of internal states. Such utilization permits shorter computational time, reduced test pattern length and fewer timing problems. In this method, the type of fault targeted for the next pattern generation is that which, on the basis of the current internal state of the circuit, is determined to be the easiest type to detect, and during pattern generation, the only value transitions traced are those which are necessary for a particular fault's detection. Experimental results show the proposed method to be efficient.","PeriodicalId":272630,"journal":{"name":"1991, Proceedings. International Test Conference","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121890301","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-10-26DOI: 10.1109/TEST.1991.519697
J. Leenstra, L. Spaanenburg
In this paper a novel hierarchical test program development approach is presented for scan testable circuits. We will show how the test program for scan designs can be developed incrementally, in-line with the hierarchical construction ofthesystem netlist, by differentiating between interior and exlerior tests for each model. Furthermore, it will be shown that byintroducing test assembly, such an hierarchical test program development approach is also applicable when nwcros requiring dedicated test procedures are in use. Therefore itprovides an attractive enhancement of the Macro Testing technique.
{"title":"Hierarchical Test Program Development for Scan Testable Circuits","authors":"J. Leenstra, L. Spaanenburg","doi":"10.1109/TEST.1991.519697","DOIUrl":"https://doi.org/10.1109/TEST.1991.519697","url":null,"abstract":"In this paper a novel hierarchical test program development approach is presented for scan testable circuits. We will show how the test program for scan designs can be developed incrementally, in-line with the hierarchical construction ofthesystem netlist, by differentiating between interior and exlerior tests for each model. Furthermore, it will be shown that byintroducing test assembly, such an hierarchical test program development approach is also applicable when nwcros requiring dedicated test procedures are in use. Therefore itprovides an attractive enhancement of the Macro Testing technique.","PeriodicalId":272630,"journal":{"name":"1991, Proceedings. International Test Conference","volume":"76 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124932005","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-10-26DOI: 10.1109/TEST.1991.519507
M. Abramovici, J. J. Kulikowski, R. Roy
The full-scan and the nonscan versions of a circuit This paper presents a new algorithm for selecting the best flip-flops to scan for achieving maximum fault coverage in a partial-scan circuit. The algorithm, called PASCAL (PArtial Scan AnaLysis), ranks the flip-flops based on their contribution to the fault coverage. The results of PASCAL provide a global view of the entire partial-scan design spectrum (from no scan to full scan), and allow the designer to estimate the fault coverage achievable with any number of scanned flip-flops and to select the minimal subset of flip-flops to scan for obtaining a desired fault coverage. The number of scanned flip-flops can be reduced by taking into account faults detected by functional tests.
{"title":"The Best Flip-Flops to Scan","authors":"M. Abramovici, J. J. Kulikowski, R. Roy","doi":"10.1109/TEST.1991.519507","DOIUrl":"https://doi.org/10.1109/TEST.1991.519507","url":null,"abstract":"The full-scan and the nonscan versions of a circuit This paper presents a new algorithm for selecting the best flip-flops to scan for achieving maximum fault coverage in a partial-scan circuit. The algorithm, called PASCAL (PArtial Scan AnaLysis), ranks the flip-flops based on their contribution to the fault coverage. The results of PASCAL provide a global view of the entire partial-scan design spectrum (from no scan to full scan), and allow the designer to estimate the fault coverage achievable with any number of scanned flip-flops and to select the minimal subset of flip-flops to scan for obtaining a desired fault coverage. The number of scanned flip-flops can be reduced by taking into account faults detected by functional tests.","PeriodicalId":272630,"journal":{"name":"1991, Proceedings. International Test Conference","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129459967","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-10-26DOI: 10.1109/TEST.1991.519793
Wojciech Maly
Summary Testing has always been an inherent calmponent of electronics. Therefore it should be viewed as a very successfully evolving field deserving a sizable portion of the credit usually given to design and manufacturing for the spectacular progress of the entire electronics area. Why, then, is it necessary to question and analyze the quality of testing education? Is testing really suffering because inadequate attention has been paid by the academic institution to testing related engineering ancl theoretical problems? The answer for the above question seems to be "yes." But the primary reason for this situation should not be attributed to academia alone. Industry also seems to be responsible for the inadequate production of high quality researchers and engineers who can effectively cope with complicated testing issues of modern electronic systems. The essence of the above problem is in the compartmentalization of the testing field, which, while convenient from administration point of view, promotes an inefficiency in communication between the various parties forming the testing community. These communication bottlenecks have led to the formation of contradicting views of the testing field.
{"title":"IMPROVING THE QUALITY OF TEST EDUCATION","authors":"Wojciech Maly","doi":"10.1109/TEST.1991.519793","DOIUrl":"https://doi.org/10.1109/TEST.1991.519793","url":null,"abstract":"Summary Testing has always been an inherent calmponent of electronics. Therefore it should be viewed as a very successfully evolving field deserving a sizable portion of the credit usually given to design and manufacturing for the spectacular progress of the entire electronics area. Why, then, is it necessary to question and analyze the quality of testing education? Is testing really suffering because inadequate attention has been paid by the academic institution to testing related engineering ancl theoretical problems? The answer for the above question seems to be \"yes.\" But the primary reason for this situation should not be attributed to academia alone. Industry also seems to be responsible for the inadequate production of high quality researchers and engineers who can effectively cope with complicated testing issues of modern electronic systems. The essence of the above problem is in the compartmentalization of the testing field, which, while convenient from administration point of view, promotes an inefficiency in communication between the various parties forming the testing community. These communication bottlenecks have led to the formation of contradicting views of the testing field.","PeriodicalId":272630,"journal":{"name":"1991, Proceedings. International Test Conference","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124513358","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-10-26DOI: 10.1109/TEST.1991.519789
N. E. Donlin
{"title":"IS BURN-IN BURNED OUT?","authors":"N. E. Donlin","doi":"10.1109/TEST.1991.519789","DOIUrl":"https://doi.org/10.1109/TEST.1991.519789","url":null,"abstract":"","PeriodicalId":272630,"journal":{"name":"1991, Proceedings. International Test Conference","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126414752","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-10-26DOI: 10.1109/TEST.1991.519768
Y. Shiran
This paper describes a new algorithm for parallel design verification. Its data model is that of tlhe data flow methodology and is based on the partitioning of the design verification cycle into independent tasks that can be run concurrently. The signihance of this methodology is that, unlike other concepts that connot use the existing sequential code and can only run on a an expensive specialpurpose hardware, the new approach does not require any code development and can be accommlodated by a ,standard Unix distributed network or a miiltiprocessor . The paper presents experimental results for performing 52 design rule checks on 1.3 million polygons (12 layers) on both a multiprocessor configuration and a distributed network.
{"title":"Distributed Layout Verification Using Sequential Software and Standard Hardware","authors":"Y. Shiran","doi":"10.1109/TEST.1991.519768","DOIUrl":"https://doi.org/10.1109/TEST.1991.519768","url":null,"abstract":"This paper describes a new algorithm for parallel design verification. Its data model is that of tlhe data flow methodology and is based on the partitioning of the design verification cycle into independent tasks that can be run concurrently. The signihance of this methodology is that, unlike other concepts that connot use the existing sequential code and can only run on a an expensive specialpurpose hardware, the new approach does not require any code development and can be accommlodated by a ,standard Unix distributed network or a miiltiprocessor . The paper presents experimental results for performing 52 design rule checks on 1.3 million polygons (12 layers) on both a multiprocessor configuration and a distributed network.","PeriodicalId":272630,"journal":{"name":"1991, Proceedings. International Test Conference","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132086997","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-10-26DOI: 10.1109/TEST.1991.519712
J. Sousa, F. Gonçalves, João Paulo Teixeira
High quality IC design involves not only performance and silicon area, but also testability. Product quality, measured by low dejects levels (as low as 100 p.p.m.), requires that test patterns must detect nearly all circuit faults caused by likely physical defects. This requires a careful examination of the testability of the physical design, and its enhancement. The purpose of this contribution is to present a methodology for physical testability evaluation, and to demonstrate its usefulness. The methodology allows realistic fault extraction and classification, and the identification of hard to detect faults, their layout location and physical origin, prior to simulation. Measures of physical testability and fault hardness are introduced. When possible, suggestions for design improvement by layout reconfiguration, are provided, as a better solution than simple test improvement, either by test pattern refinement, or by using more sophisticated detection techniques, like current testing. Simulation results, with several design examples, show that layout styles exhibit characteristic pat.terns, in terms of t,he incidence of faults caused by the different, physical defects. Hence, for each layout style, the sensivity of physical designs to each physical defect can be analysed and decreased. Moreover, simulation results with a new cell library demonstrate that physical design improvements can significantly enhance the circuit’s qualit,y and testability.
{"title":"IC DEFECTS-BASED TESTABILITY ANALYSIS","authors":"J. Sousa, F. Gonçalves, João Paulo Teixeira","doi":"10.1109/TEST.1991.519712","DOIUrl":"https://doi.org/10.1109/TEST.1991.519712","url":null,"abstract":"High quality IC design involves not only performance and silicon area, but also testability. Product quality, measured by low dejects levels (as low as 100 p.p.m.), requires that test patterns must detect nearly all circuit faults caused by likely physical defects. This requires a careful examination of the testability of the physical design, and its enhancement. The purpose of this contribution is to present a methodology for physical testability evaluation, and to demonstrate its usefulness. The methodology allows realistic fault extraction and classification, and the identification of hard to detect faults, their layout location and physical origin, prior to simulation. Measures of physical testability and fault hardness are introduced. When possible, suggestions for design improvement by layout reconfiguration, are provided, as a better solution than simple test improvement, either by test pattern refinement, or by using more sophisticated detection techniques, like current testing. Simulation results, with several design examples, show that layout styles exhibit characteristic pat.terns, in terms of t,he incidence of faults caused by the different, physical defects. Hence, for each layout style, the sensivity of physical designs to each physical defect can be analysed and decreased. Moreover, simulation results with a new cell library demonstrate that physical design improvements can significantly enhance the circuit’s qualit,y and testability.","PeriodicalId":272630,"journal":{"name":"1991, Proceedings. International Test Conference","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132556381","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-10-26DOI: 10.1109/TEST.1991.519769
Sungju Park, S. Akers
Parity bit checking and pseudo-exhaustive testing are two design techniques which have been widely discussed in the BIST literature but have seldom been employed in practice because of the exponential nature of the processes involved. In this paper we describe several procedures designed to avoid these exponential explosions. Specifically we show how the parity of a large combinational function can (often) be quickly calculated. This is accomplished by an examination of the circuit realization itself particularly with regard to the connectivity between the various inputs and outputs. We then show how this same approach can be used to partition circuits so that they can be tested efficiently with a relatively small number of test patterns. Using these methods we were able to calculate the parity bits for more than 80% of ISCAS benchmark circuits' outputs. Interestingly enough, only 15% of these outputs were found to be parity-odd, but for these cases high fault coverage was invariably found to result. Several examples are included.
{"title":"Parity Bit Calculation and Test Signal Compaction for BTST Applications","authors":"Sungju Park, S. Akers","doi":"10.1109/TEST.1991.519769","DOIUrl":"https://doi.org/10.1109/TEST.1991.519769","url":null,"abstract":"Parity bit checking and pseudo-exhaustive testing are two design techniques which have been widely discussed in the BIST literature but have seldom been employed in practice because of the exponential nature of the processes involved. In this paper we describe several procedures designed to avoid these exponential explosions. Specifically we show how the parity of a large combinational function can (often) be quickly calculated. This is accomplished by an examination of the circuit realization itself particularly with regard to the connectivity between the various inputs and outputs. We then show how this same approach can be used to partition circuits so that they can be tested efficiently with a relatively small number of test patterns. Using these methods we were able to calculate the parity bits for more than 80% of ISCAS benchmark circuits' outputs. Interestingly enough, only 15% of these outputs were found to be parity-odd, but for these cases high fault coverage was invariably found to result. Several examples are included.","PeriodicalId":272630,"journal":{"name":"1991, Proceedings. International Test Conference","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114671679","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-10-26DOI: 10.1109/TEST.1991.519495
Hyunwoo Cho, G. Hachtel, F. Somenzi
The knowledge of the State Transition Graph (STG) of a sequential circuit helps in generating test sequences. For instance, by determining that a set of states is not reachable from the reset state, it is possible to identify a certain type of sequentially untestable faults. However, until recently, the ability of algorithms to store the STG of a sequential circuit has been limited to small instances. Recent advances in sequential circuit verification, based on the use of binary decision diagrams and new powerful implicit enumeration algorithms, have dramatically improved our ability to deal with large numbers of states. In this paper we report on the application of these algorithms to the problems of generating justification sequences, identifying redundancies, and dealing with hard-to-detect faults. Our experiments show substantial improvements over previously published results.
{"title":"Fast sequential ATPG based on implicit state enumeration","authors":"Hyunwoo Cho, G. Hachtel, F. Somenzi","doi":"10.1109/TEST.1991.519495","DOIUrl":"https://doi.org/10.1109/TEST.1991.519495","url":null,"abstract":"The knowledge of the State Transition Graph (STG) of a sequential circuit helps in generating test sequences. For instance, by determining that a set of states is not reachable from the reset state, it is possible to identify a certain type of sequentially untestable faults. However, until recently, the ability of algorithms to store the STG of a sequential circuit has been limited to small instances. Recent advances in sequential circuit verification, based on the use of binary decision diagrams and new powerful implicit enumeration algorithms, have dramatically improved our ability to deal with large numbers of states. In this paper we report on the application of these algorithms to the problems of generating justification sequences, identifying redundancies, and dealing with hard-to-detect faults. Our experiments show substantial improvements over previously published results.","PeriodicalId":272630,"journal":{"name":"1991, Proceedings. International Test Conference","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124178658","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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